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imx: imx9: clock: Add DDR clock support
Implement the DDR driver clock interfaces for set DDR rate and bypass DDR PLL Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
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2 changed files with 44 additions and 0 deletions
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@ -213,6 +213,9 @@ void init_clk_usdhc(u32 index);
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int enable_i2c_clk(unsigned char enable, u32 i2c_num);
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u32 imx_get_i2cclk(u32 i2c_num);
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u32 mxc_get_clock(enum mxc_clock clk);
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void dram_pll_init(ulong pll_val);
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void dram_enable_bypass(ulong clk_val);
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void dram_disable_bypass(void);
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int ccm_clk_src_on(enum ccm_clk_src oscpll, bool enable);
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int ccm_clk_src_auto(enum ccm_clk_src oscpll, bool enable);
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@ -626,6 +626,47 @@ void enable_usboh3_clk(unsigned char enable)
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}
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}
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#ifdef CONFIG_SPL_BUILD
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void dram_pll_init(ulong pll_val)
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{
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configure_fracpll(DRAM_PLL_CLK, pll_val);
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}
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void dram_enable_bypass(ulong clk_val)
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{
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switch (clk_val) {
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case MHZ(400):
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ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 2);
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break;
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case MHZ(333):
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ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD0, 3);
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break;
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case MHZ(200):
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ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 4);
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break;
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case MHZ(100):
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ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 8);
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break;
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default:
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printf("No matched freq table %lu\n", clk_val);
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return;
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}
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/* Set DRAM APB to 133Mhz */
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ccm_clk_root_cfg(DRAM_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
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/* Switch from DRAM clock root from PLL to CCM */
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ccm_shared_gpr_set(SHARED_GPR_DRAM_CLK, SHARED_GPR_DRAM_CLK_SEL_CCM);
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}
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void dram_disable_bypass(void)
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{
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/* Set DRAM APB to 133Mhz */
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ccm_clk_root_cfg(DRAM_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
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/* Switch from DRAM clock root from CCM to PLL */
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ccm_shared_gpr_set(SHARED_GPR_DRAM_CLK, SHARED_GPR_DRAM_CLK_SEL_PLL);
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}
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#endif
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int clock_init(void)
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{
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int i;
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