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global: Migrate CONFIG_SAR2_REG to CFG
Perform a simple rename of CONFIG_SAR2_REG to CFG_SAR2_REG Signed-off-by: Tom Rini <trini@konsulko.com>
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3db78c830f
commit
f9932d38a3
2 changed files with 5 additions and 5 deletions
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@ -195,7 +195,7 @@ void get_sar_freq(struct sar_freq_modes *sar_freq)
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int i;
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#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_MSYS)
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val = readl(CONFIG_SAR2_REG); /* SAR - Sample At Reset */
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val = readl(CFG_SAR2_REG); /* SAR - Sample At Reset */
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#else
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val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
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#endif
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@ -205,7 +205,7 @@ void get_sar_freq(struct sar_freq_modes *sar_freq)
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* Shift CPU0 clock frequency select bit from SAR2 register
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* into correct position
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*/
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freq |= ((readl(CONFIG_SAR2_REG) & SAR2_CPU_FREQ_MASK)
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freq |= ((readl(CFG_SAR2_REG) & SAR2_CPU_FREQ_MASK)
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>> SAR2_CPU_FREQ_OFFS) << 3;
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#endif
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for (i = 0; sar_freq_tab[i].val != 0xff; i++) {
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@ -135,7 +135,7 @@
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#if defined(CONFIG_ARMADA_375)
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/* SAR values for Armada 375 */
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#define CONFIG_SAR_REG (MVEBU_REGISTER(0xe8200))
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#define CONFIG_SAR2_REG (MVEBU_REGISTER(0xe8204))
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#define CFG_SAR2_REG (MVEBU_REGISTER(0xe8204))
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#define SAR_CPU_FREQ_OFFS 17
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#define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS)
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@ -174,7 +174,7 @@
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#elif defined(CONFIG_ARMADA_MSYS)
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/* SAR values for MSYS */
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#define CONFIG_SAR_REG (MBUS_DFX_BASE + 0xf8200)
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#define CONFIG_SAR2_REG (MBUS_DFX_BASE + 0xf8204)
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#define CFG_SAR2_REG (MBUS_DFX_BASE + 0xf8204)
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#define SAR_CPU_FREQ_OFFS 18
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#define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS)
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@ -192,7 +192,7 @@
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#elif defined(CONFIG_ARMADA_XP)
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/* SAR values for Armada XP */
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#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230))
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#define CONFIG_SAR2_REG (MVEBU_REGISTER(0x18234))
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#define CFG_SAR2_REG (MVEBU_REGISTER(0x18234))
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#define SAR_CPU_FREQ_OFFS 21
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#define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS)
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