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arch: rockchip: Add cru header for rv1126
Add clock and reset unit header include for rv1126. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Jagan Teki
Kever Yang
parent
8430a87502
commit
f4ca986e29
1 changed files with 459 additions and 0 deletions
459
arch/arm/include/asm/arch-rockchip/cru_rv1126.h
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459
arch/arm/include/asm/arch-rockchip/cru_rv1126.h
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 Rockchip Electronics Co. Ltd.
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* Author: Finley Xiao <finley.xiao@rock-chips.com>
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*/
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#ifndef _ASM_ARCH_CRU_RV1126_H
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#define _ASM_ARCH_CRU_RV1126_H
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#define MHz 1000000
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#define KHz 1000
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#define OSC_HZ (24 * MHz)
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#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT)
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#define APLL_HZ (1008 * MHz)
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#else
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#define APLL_HZ (816 * MHz)
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#endif
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#define GPLL_HZ (1188 * MHz)
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#define CPLL_HZ (500 * MHz)
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#define HPLL_HZ (1400 * MHz)
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#define PCLK_PDPMU_HZ (100 * MHz)
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#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT)
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#define ACLK_PDBUS_HZ (396 * MHz)
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#else
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#define ACLK_PDBUS_HZ (500 * MHz)
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#endif
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#define HCLK_PDBUS_HZ (200 * MHz)
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#define PCLK_PDBUS_HZ (100 * MHz)
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#define ACLK_PDPHP_HZ (300 * MHz)
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#define HCLK_PDPHP_HZ (200 * MHz)
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#define HCLK_PDCORE_HZ (200 * MHz)
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#define HCLK_PDAUDIO_HZ (150 * MHz)
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#define CLK_OSC0_DIV_HZ (32768)
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#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT)
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#define ACLK_PDVI_HZ (297 * MHz)
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#define CLK_ISP_HZ (297 * MHz)
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#define ACLK_PDISPP_HZ (297 * MHz)
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#define CLK_ISPP_HZ (237 * MHz)
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#define ACLK_VOP_HZ (300 * MHz)
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#define DCLK_VOP_HZ (65 * MHz)
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#endif
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/* RV1126 pll id */
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enum rv1126_pll_id {
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APLL,
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DPLL,
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CPLL,
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HPLL,
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GPLL,
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PLL_COUNT,
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};
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struct rv1126_clk_info {
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unsigned long id;
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char *name;
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bool is_cru;
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};
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/* Private data for the clock driver - used by rockchip_get_cru() */
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struct rv1126_pmuclk_priv {
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struct rv1126_pmucru *pmucru;
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ulong gpll_hz;
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};
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struct rv1126_clk_priv {
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struct rv1126_cru *cru;
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struct rv1126_grf *grf;
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ulong gpll_hz;
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ulong cpll_hz;
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ulong hpll_hz;
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ulong armclk_hz;
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ulong armclk_enter_hz;
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ulong armclk_init_hz;
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bool sync_kernel;
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bool set_armclk_rate;
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};
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struct rv1126_pll {
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unsigned int con0;
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unsigned int con1;
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unsigned int con2;
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unsigned int con3;
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unsigned int con4;
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unsigned int con5;
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unsigned int con6;
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unsigned int reserved0[1];
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};
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struct rv1126_pmucru {
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unsigned int pmu_mode;
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unsigned int reserved1[3];
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struct rv1126_pll pll;
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unsigned int offsetcal_status;
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unsigned int reserved2[51];
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unsigned int pmu_clksel_con[14];
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unsigned int reserved3[18];
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unsigned int pmu_clkgate_con[3];
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unsigned int reserved4[29];
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unsigned int pmu_softrst_con[2];
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unsigned int reserved5[14];
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unsigned int pmu_autocs_con[2];
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};
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check_member(rv1126_pmucru, pmu_autocs_con[1], 0x244);
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struct rv1126_cru {
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struct rv1126_pll pll[4];
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unsigned int offsetcal_status[4];
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unsigned int mode;
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unsigned int reserved1[27];
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unsigned int clksel_con[78];
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unsigned int reserved2[18];
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unsigned int clkgate_con[25];
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unsigned int reserved3[7];
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unsigned int softrst_con[15];
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unsigned int reserved4[17];
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unsigned int ssgtbl[32];
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unsigned int glb_cnt_th;
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unsigned int glb_rst_st;
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unsigned int glb_srst_fst;
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unsigned int glb_srst_snd;
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unsigned int glb_rst_con;
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unsigned int reserved5[11];
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unsigned int sdmmc_con[2];
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unsigned int sdio_con[2];
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unsigned int emmc_con[2];
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unsigned int reserved6[2];
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unsigned int gmac_con;
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unsigned int misc[2];
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unsigned int reserved7[45];
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unsigned int autocs_con[26];
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};
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check_member(rv1126_cru, autocs_con[25], 0x584);
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struct pll_rate_table {
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unsigned long rate;
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unsigned int fbdiv;
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unsigned int postdiv1;
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unsigned int refdiv;
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unsigned int postdiv2;
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unsigned int dsmpd;
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unsigned int frac;
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};
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struct cpu_rate_table {
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unsigned long rate;
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unsigned int aclk_div;
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unsigned int pclk_div;
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};
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#define RV1126_PMU_MODE 0x0
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#define RV1126_PMU_PLL_CON(x) ((x) * 0x4 + 0x10)
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#define RV1126_PLL_CON(x) ((x) * 0x4)
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#define RV1126_MODE_CON 0x90
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enum {
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/* CRU_PMU_CLK_SEL0_CON */
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RTC32K_SEL_SHIFT = 7,
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RTC32K_SEL_MASK = 0x3 << RTC32K_SEL_SHIFT,
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RTC32K_SEL_PMUPVTM = 0,
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RTC32K_SEL_OSC1_32K,
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RTC32K_SEL_OSC0_DIV32K,
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/* CRU_PMU_CLK_SEL1_CON */
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PCLK_PDPMU_DIV_SHIFT = 0,
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PCLK_PDPMU_DIV_MASK = 0x1f,
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/* CRU_PMU_CLK_SEL2_CON */
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CLK_I2C0_DIV_SHIFT = 0,
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CLK_I2C0_DIV_MASK = 0x7f,
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/* CRU_PMU_CLK_SEL3_CON */
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CLK_I2C2_DIV_SHIFT = 0,
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CLK_I2C2_DIV_MASK = 0x7f,
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/* CRU_PMU_CLK_SEL6_CON */
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CLK_PWM1_SEL_SHIFT = 15,
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CLK_PWM1_SEL_MASK = 1 << CLK_PWM1_SEL_SHIFT,
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CLK_PWM1_SEL_XIN24M = 0,
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CLK_PWM1_SEL_GPLL,
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CLK_PWM1_DIV_SHIFT = 8,
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CLK_PWM1_DIV_MASK = 0x7f << CLK_PWM1_DIV_SHIFT,
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CLK_PWM0_SEL_SHIFT = 7,
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CLK_PWM0_SEL_MASK = 1 << CLK_PWM0_SEL_SHIFT,
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CLK_PWM0_SEL_XIN24M = 0,
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CLK_PWM0_SEL_GPLL,
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CLK_PWM0_DIV_SHIFT = 0,
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CLK_PWM0_DIV_MASK = 0x7f,
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/* CRU_PMU_CLK_SEL9_CON */
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CLK_SPI0_SEL_SHIFT = 7,
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CLK_SPI0_SEL_MASK = 1 << CLK_SPI0_SEL_SHIFT,
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CLK_SPI0_SEL_GPLL = 0,
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CLK_SPI0_SEL_XIN24M,
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CLK_SPI0_DIV_SHIFT = 0,
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CLK_SPI0_DIV_MASK = 0x7f,
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/* CRU_PMU_CLK_SEL13_CON */
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CLK_RTC32K_FRAC_NUMERATOR_SHIFT = 16,
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CLK_RTC32K_FRAC_NUMERATOR_MASK = 0xffff << 16,
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CLK_RTC32K_FRAC_DENOMINATOR_SHIFT = 0,
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CLK_RTC32K_FRAC_DENOMINATOR_MASK = 0xffff,
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/* CRU_CLK_SEL0_CON */
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CORE_HCLK_DIV_SHIFT = 8,
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CORE_HCLK_DIV_MASK = 0x1f << CORE_HCLK_DIV_SHIFT,
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/* CRU_CLK_SEL1_CON */
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CORE_ACLK_DIV_SHIFT = 4,
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CORE_ACLK_DIV_MASK = 0xf << CORE_ACLK_DIV_SHIFT,
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CORE_DBG_DIV_SHIFT = 0,
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CORE_DBG_DIV_MASK = 0x7,
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/* CRU_CLK_SEL2_CON */
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HCLK_PDBUS_SEL_SHIFT = 15,
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HCLK_PDBUS_SEL_MASK = 1 << HCLK_PDBUS_SEL_SHIFT,
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HCLK_PDBUS_SEL_GPLL = 0,
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HCLK_PDBUS_SEL_CPLL,
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HCLK_PDBUS_DIV_SHIFT = 8,
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HCLK_PDBUS_DIV_MASK = 0x1f << HCLK_PDBUS_DIV_SHIFT,
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ACLK_PDBUS_SEL_SHIFT = 6,
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ACLK_PDBUS_SEL_MASK = 0x3 << ACLK_PDBUS_SEL_SHIFT,
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ACLK_PDBUS_SEL_GPLL = 0,
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ACLK_PDBUS_SEL_CPLL,
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ACLK_PDBUS_SEL_DPLL,
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ACLK_PDBUS_DIV_SHIFT = 0,
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ACLK_PDBUS_DIV_MASK = 0x1f,
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/* CRU_CLK_SEL3_CON */
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CLK_SCR1_SEL_SHIFT = 15,
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CLK_SCR1_SEL_MASK = 1 << CLK_SCR1_SEL_SHIFT,
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CLK_SCR1_SEL_GPLL = 0,
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CLK_SCR1_SEL_CPLL,
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CLK_SCR1_DIV_SHIFT = 8,
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CLK_SCR1_DIV_MASK = 0x1f << CLK_SCR1_DIV_SHIFT,
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PCLK_PDBUS_SEL_SHIFT = 7,
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PCLK_PDBUS_SEL_MASK = 1 << PCLK_PDBUS_SEL_SHIFT,
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PCLK_PDBUS_SEL_GPLL = 0,
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PCLK_PDBUS_SEL_CPLL,
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PCLK_PDBUS_DIV_SHIFT = 0,
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PCLK_PDBUS_DIV_MASK = 0x1f,
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/* CRU_CLK_SEL4_CON */
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ACLK_CRYPTO_SEL_SHIFT = 7,
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ACLK_CRYPTO_SEL_MASK = 1 << ACLK_CRYPTO_SEL_SHIFT,
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ACLK_CRYPTO_SEL_GPLL = 0,
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ACLK_CRYPTO_SEL_CPLL,
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ACLK_CRYPTO_DIV_SHIFT = 0,
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ACLK_CRYPTO_DIV_MASK = 0x1f,
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/* CRU_CLK_SEL5_CON */
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CLK_I2C3_DIV_SHIFT = 8,
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CLK_I2C3_DIV_MASK = 0x7f << CLK_I2C3_DIV_SHIFT,
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CLK_I2C1_DIV_SHIFT = 0,
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CLK_I2C1_DIV_MASK = 0x7f,
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/* CRU_CLK_SEL6_CON */
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CLK_I2C5_DIV_SHIFT = 8,
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CLK_I2C5_DIV_MASK = 0x7f << CLK_I2C5_DIV_SHIFT,
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CLK_I2C4_DIV_SHIFT = 0,
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CLK_I2C4_DIV_MASK = 0x7f,
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/* CRU_CLK_SEL7_CON */
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CLK_CRYPTO_PKA_SEL_SHIFT = 15,
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CLK_CRYPTO_PKA_SEL_MASK = 1 << CLK_CRYPTO_PKA_SEL_SHIFT,
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CLK_CRYPTO_PKA_SEL_GPLL = 0,
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CLK_CRYPTO_PKA_SEL_CPLL,
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CLK_CRYPTO_PKA_DIV_SHIFT = 8,
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CLK_CRYPTO_PKA_DIV_MASK = 0x1f << CLK_CRYPTO_PKA_DIV_SHIFT,
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CLK_CRYPTO_CORE_SEL_SHIFT = 7,
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CLK_CRYPTO_CORE_SEL_MASK = 1 << CLK_CRYPTO_CORE_SEL_SHIFT,
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CLK_CRYPTO_CORE_SEL_GPLL = 0,
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CLK_CRYPTO_CORE_SEL_CPLL,
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CLK_CRYPTO_CORE_DIV_SHIFT = 0,
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CLK_CRYPTO_CORE_DIV_MASK = 0x1f,
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/* CRU_CLK_SEL8_CON */
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CLK_SPI1_SEL_SHIFT = 8,
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CLK_SPI1_SEL_MASK = 1 << CLK_SPI1_SEL_SHIFT,
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CLK_SPI1_SEL_GPLL = 0,
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CLK_SPI1_SEL_XIN24M,
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CLK_SPI1_DIV_SHIFT = 0,
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CLK_SPI1_DIV_MASK = 0x7f,
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/* CRU_CLK_SEL9_CON */
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CLK_PWM2_SEL_SHIFT = 15,
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CLK_PWM2_SEL_MASK = 1 << CLK_PWM2_SEL_SHIFT,
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CLK_PWM2_SEL_XIN24M = 0,
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CLK_PWM2_SEL_GPLL,
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CLK_PWM2_DIV_SHIFT = 8,
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CLK_PWM2_DIV_MASK = 0x7f << CLK_PWM2_DIV_SHIFT,
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/* CRU_CLK_SEL20_CON */
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CLK_SARADC_DIV_SHIFT = 0,
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CLK_SARADC_DIV_MASK = 0x7ff,
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/* CRU_CLK_SEL25_CON */
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DCLK_DECOM_SEL_SHIFT = 15,
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DCLK_DECOM_SEL_MASK = 1 << DCLK_DECOM_SEL_SHIFT,
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DCLK_DECOM_SEL_GPLL = 0,
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DCLK_DECOM_SEL_CPLL,
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DCLK_DECOM_DIV_SHIFT = 8,
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DCLK_DECOM_DIV_MASK = 0x7f << DCLK_DECOM_DIV_SHIFT,
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/* CRU_CLK_SEL26_CON */
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HCLK_PDAUDIO_DIV_SHIFT = 0,
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HCLK_PDAUDIO_DIV_MASK = 0x1f,
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/* CRU_CLK_SEL45_CON */
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ACLK_PDVO_SEL_SHIFT = 7,
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ACLK_PDVO_SEL_MASK = 1 << ACLK_PDVO_SEL_SHIFT,
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ACLK_PDVO_SEL_GPLL = 0,
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ACLK_PDVO_SEL_CPLL,
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ACLK_PDVO_DIV_SHIFT = 0,
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ACLK_PDVO_DIV_MASK = 0x1f,
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/* CRU_CLK_SEL47_CON */
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DCLK_VOP_SEL_SHIFT = 8,
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DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT,
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DCLK_VOP_SEL_GPLL = 0,
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DCLK_VOP_SEL_CPLL,
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DCLK_VOP_DIV_SHIFT = 0,
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DCLK_VOP_DIV_MASK = 0xff,
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#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT)
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/* CRU_CLK_SEL49_CON */
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ACLK_PDVI_SEL_SHIFT = 6,
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ACLK_PDVI_SEL_MASK = 0x3 << ACLK_PDVI_SEL_SHIFT,
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ACLK_PDVI_SEL_CPLL = 0,
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ACLK_PDVI_SEL_GPLL,
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ACLK_PDVI_SEL_HPLL,
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ACLK_PDVI_DIV_SHIFT = 0,
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ACLK_PDVI_DIV_MASK = 0x1f,
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/* CRU_CLK_SEL50_CON */
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CLK_ISP_SEL_SHIFT = 6,
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CLK_ISP_SEL_MASK = 0x3 << CLK_ISP_SEL_SHIFT,
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CLK_ISP_SEL_GPLL = 0,
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CLK_ISP_SEL_CPLL,
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CLK_ISP_SEL_HPLL,
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CLK_ISP_DIV_SHIFT = 0,
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CLK_ISP_DIV_MASK = 0x1f,
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#endif
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/* CRU_CLK_SEL53_CON */
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HCLK_PDPHP_DIV_SHIFT = 8,
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HCLK_PDPHP_DIV_MASK = 0x1f << HCLK_PDPHP_DIV_SHIFT,
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ACLK_PDPHP_SEL_SHIFT = 7,
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ACLK_PDPHP_SEL_MASK = 1 << ACLK_PDPHP_SEL_SHIFT,
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ACLK_PDPHP_SEL_GPLL = 0,
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ACLK_PDPHP_SEL_CPLL,
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ACLK_PDPHP_DIV_SHIFT = 0,
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ACLK_PDPHP_DIV_MASK = 0x1f,
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/* CRU_CLK_SEL57_CON */
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EMMC_SEL_SHIFT = 14,
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EMMC_SEL_MASK = 0x3 << EMMC_SEL_SHIFT,
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EMMC_SEL_GPLL = 0,
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EMMC_SEL_CPLL,
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EMMC_SEL_XIN24M,
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EMMC_DIV_SHIFT = 0,
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EMMC_DIV_MASK = 0xff,
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/* CRU_CLK_SEL58_CON */
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SCLK_SFC_SEL_SHIFT = 15,
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SCLK_SFC_SEL_MASK = 0x1 << SCLK_SFC_SEL_SHIFT,
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SCLK_SFC_SEL_CPLL = 0,
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SCLK_SFC_SEL_GPLL,
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SCLK_SFC_DIV_SHIFT = 0,
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SCLK_SFC_DIV_MASK = 0xff,
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/* CRU_CLK_SEL59_CON */
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CLK_NANDC_SEL_SHIFT = 15,
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CLK_NANDC_SEL_MASK = 0x1 << CLK_NANDC_SEL_SHIFT,
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CLK_NANDC_SEL_GPLL = 0,
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CLK_NANDC_SEL_CPLL,
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CLK_NANDC_DIV_SHIFT = 0,
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CLK_NANDC_DIV_MASK = 0xff,
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/* CRU_CLK_SEL61_CON */
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CLK_GMAC_OUT_SEL_SHIFT = 15,
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CLK_GMAC_OUT_SEL_MASK = 0x1 << CLK_GMAC_OUT_SEL_SHIFT,
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CLK_GMAC_OUT_SEL_CPLL = 0,
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CLK_GMAC_OUT_SEL_GPLL,
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CLK_GMAC_OUT_DIV_SHIFT = 8,
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CLK_GMAC_OUT_DIV_MASK = 0x1f << CLK_GMAC_OUT_DIV_SHIFT,
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/* CRU_CLK_SEL63_CON */
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PCLK_GMAC_DIV_SHIFT = 8,
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PCLK_GMAC_DIV_MASK = 0x1f << PCLK_GMAC_DIV_SHIFT,
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CLK_GMAC_SRC_SEL_SHIFT = 7,
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CLK_GMAC_SRC_SEL_MASK = 0x1 << CLK_GMAC_SRC_SEL_SHIFT,
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CLK_GMAC_SRC_SEL_CPLL = 0,
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CLK_GMAC_SRC_SEL_GPLL,
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CLK_GMAC_SRC_DIV_SHIFT = 0,
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CLK_GMAC_SRC_DIV_MASK = 0x1f << CLK_GMAC_SRC_DIV_SHIFT,
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#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT)
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/* CRU_CLK_SEL68_CON */
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ACLK_PDISPP_SEL_SHIFT = 6,
|
||||
ACLK_PDISPP_SEL_MASK = 0x3 << ACLK_PDISPP_SEL_SHIFT,
|
||||
ACLK_PDISPP_SEL_CPLL = 0,
|
||||
ACLK_PDISPP_SEL_GPLL,
|
||||
ACLK_PDISPP_SEL_HPLL,
|
||||
ACLK_PDISPP_DIV_SHIFT = 0,
|
||||
ACLK_PDISPP_DIV_MASK = 0x1f,
|
||||
|
||||
/* CRU_CLK_SEL69_CON */
|
||||
CLK_ISPP_SEL_SHIFT = 6,
|
||||
CLK_ISPP_SEL_MASK = 0x3 << CLK_ISPP_SEL_SHIFT,
|
||||
CLK_ISPP_SEL_CPLL = 0,
|
||||
CLK_ISPP_SEL_GPLL,
|
||||
CLK_ISPP_SEL_HPLL,
|
||||
CLK_ISPP_DIV_SHIFT = 0,
|
||||
CLK_ISPP_DIV_MASK = 0x1f,
|
||||
|
||||
/* CRU_CLK_SEL73_CON */
|
||||
MIPICSI_OUT_SEL_SHIFT = 10,
|
||||
MIPICSI_OUT_SEL_MASK = 0x3 << MIPICSI_OUT_SEL_SHIFT,
|
||||
MIPICSI_OUT_SEL_XIN24M = 0,
|
||||
MIPICSI_OUT_SEL_DIV,
|
||||
MIPICSI_OUT_SEL_FRACDIV,
|
||||
MIPICSI_OUT_DIV_SHIFT = 0,
|
||||
MIPICSI_OUT_DIV_MASK = 0x1f,
|
||||
#endif
|
||||
|
||||
/* CRU_GMAC_CON */
|
||||
GMAC_SRC_M1_SEL_SHIFT = 5,
|
||||
GMAC_SRC_M1_SEL_MASK = 0x1 << GMAC_SRC_M1_SEL_SHIFT,
|
||||
GMAC_SRC_M1_SEL_INT = 0,
|
||||
GMAC_SRC_M1_SEL_EXT,
|
||||
GMAC_MODE_SEL_SHIFT = 4,
|
||||
GMAC_MODE_SEL_MASK = 0x1 << GMAC_MODE_SEL_SHIFT,
|
||||
GMAC_RGMII_MODE = 0,
|
||||
GMAC_RMII_MODE,
|
||||
RGMII_CLK_SEL_SHIFT = 2,
|
||||
RGMII_CLK_SEL_MASK = 0x3 << RGMII_CLK_SEL_SHIFT,
|
||||
RGMII_CLK_DIV0 = 0,
|
||||
RGMII_CLK_DIV1,
|
||||
RGMII_CLK_DIV50,
|
||||
RGMII_CLK_DIV5,
|
||||
RMII_CLK_SEL_SHIFT = 1,
|
||||
RMII_CLK_SEL_MASK = 0x1 << RMII_CLK_SEL_SHIFT,
|
||||
RMII_CLK_DIV20 = 0,
|
||||
RMII_CLK_DIV2,
|
||||
GMAC_SRC_M0_SEL_SHIFT = 0,
|
||||
GMAC_SRC_M0_SEL_MASK = 0x1,
|
||||
GMAC_SRC_M0_SEL_INT = 0,
|
||||
GMAC_SRC_M0_SEL_EXT,
|
||||
|
||||
/* GRF_IOFUNC_CON1 */
|
||||
GMAC_SRC_SEL_SHIFT = 12,
|
||||
GMAC_SRC_SEL_MASK = 1 << GMAC_SRC_SEL_SHIFT,
|
||||
GMAC_SRC_SEL_M0 = 0,
|
||||
GMAC_SRC_SEL_M1,
|
||||
};
|
||||
#endif
|
||||
Loading…
Reference in a new issue