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arm64: zynqmp: Describe TI phy as ethernet-phy-id
TI DP83867 is using strapping based on MIO pins. Tristate setup can influce PHY address. That's why switch description with ethernet-phy-id compatible string which enable calling reset. PHY itself setups phy address after power up or reset. Reset description will be added in separate commit. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/52bf9ac0453d4e4896d8edd2618e684bb1ff6012.1662721547.git.michal.simek@amd.com
This commit is contained in:
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0fb7fd865b
commit
13622c7a9d
6 changed files with 73 additions and 38 deletions
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@ -200,13 +200,19 @@
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phy-mode = "rgmii-id";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gem3_default>;
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phy0: ethernet-phy@21 {
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reg = <21>;
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ti,rx-internal-delay = <0x8>;
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ti,tx-internal-delay = <0xa>;
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ti,fifo-depth = <0x1>;
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ti,dp83867-rxctrl-strap-quirk;
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/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
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mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@21 {
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#phy-cells = <1>;
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compatible = "ethernet-phy-id2000.a231";
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reg = <21>;
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ti,rx-internal-delay = <0x8>;
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ti,tx-internal-delay = <0xa>;
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ti,fifo-depth = <0x1>;
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ti,dp83867-rxctrl-strap-quirk;
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/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
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};
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};
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};
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@ -109,12 +109,18 @@
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phy-mode = "rgmii-id";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gem3_default>;
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phy0: ethernet-phy@c {
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reg = <0xc>;
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ti,rx-internal-delay = <0x8>;
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ti,tx-internal-delay = <0xa>;
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ti,fifo-depth = <0x1>;
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ti,dp83867-rxctrl-strap-quirk;
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mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@c {
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#phy-cells = <1>;
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compatible = "ethernet-phy-id2000.a231";
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reg = <0xc>;
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ti,rx-internal-delay = <0x8>;
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ti,tx-internal-delay = <0xa>;
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ti,fifo-depth = <0x1>;
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ti,dp83867-rxctrl-strap-quirk;
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};
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};
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};
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@ -114,12 +114,18 @@
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phy-mode = "rgmii-id";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gem3_default>;
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phy0: ethernet-phy@c {
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reg = <0xc>;
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ti,rx-internal-delay = <0x8>;
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ti,tx-internal-delay = <0xa>;
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ti,fifo-depth = <0x1>;
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ti,dp83867-rxctrl-strap-quirk;
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mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@c {
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#phy-cells = <1>;
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compatible = "ethernet-phy-id2000.a231";
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reg = <0xc>;
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ti,rx-internal-delay = <0x8>;
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ti,tx-internal-delay = <0xa>;
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ti,fifo-depth = <0x1>;
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ti,dp83867-rxctrl-strap-quirk;
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};
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};
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};
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@ -172,12 +172,18 @@
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phy-mode = "rgmii-id";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gem3_default>;
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phy0: ethernet-phy@c {
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reg = <0xc>;
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ti,rx-internal-delay = <0x8>;
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ti,tx-internal-delay = <0xa>;
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ti,fifo-depth = <0x1>;
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ti,dp83867-rxctrl-strap-quirk;
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mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@c {
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#phy-cells = <1>;
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compatible = "ethernet-phy-id2000.a231";
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reg = <0xc>;
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ti,rx-internal-delay = <0x8>;
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ti,tx-internal-delay = <0xa>;
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ti,fifo-depth = <0x1>;
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ti,dp83867-rxctrl-strap-quirk;
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};
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};
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};
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@ -169,12 +169,18 @@
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status = "okay";
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phy-handle = <&phy0>;
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phy-mode = "rgmii-id";
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phy0: ethernet-phy@c {
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reg = <0xc>;
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ti,rx-internal-delay = <0x8>;
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ti,tx-internal-delay = <0xa>;
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ti,fifo-depth = <0x1>;
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ti,dp83867-rxctrl-strap-quirk;
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mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@c {
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#phy-cells = <1>;
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compatible = "ethernet-phy-id2000.a231";
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reg = <0xc>;
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ti,rx-internal-delay = <0x8>;
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ti,tx-internal-delay = <0xa>;
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ti,fifo-depth = <0x1>;
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ti,dp83867-rxctrl-strap-quirk;
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};
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};
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};
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@ -176,15 +176,20 @@
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status = "okay";
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phy-handle = <&phy0>;
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phy-mode = "rgmii-id";
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phy0: ethernet-phy@c {
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reg = <0xc>;
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ti,rx-internal-delay = <0x8>;
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ti,tx-internal-delay = <0xa>;
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ti,fifo-depth = <0x1>;
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ti,dp83867-rxctrl-strap-quirk;
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mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@c {
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#phy-cells = <1>;
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compatible = "ethernet-phy-id2000.a231";
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reg = <0xc>;
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ti,rx-internal-delay = <0x8>;
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ti,tx-internal-delay = <0xa>;
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ti,fifo-depth = <0x1>;
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ti,dp83867-rxctrl-strap-quirk;
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};
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};
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};
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&gpio {
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status = "okay";
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gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */
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