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global: Move remaining CONFIG_SYS_NAND_* to CFG_SYS_NAND_*

Browse source 
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NAND
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Tom Rini 2022-11-12 17:36:51 -05:00
parent 0cd0325964
commit 4e5909450e
175 changed files with 1102 additions and 1102 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
README
View file

@ -1364,18 +1364,18 @@ The following options need to be configured:
CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,
CONFIG_SYS_NAND_ECCPOS, CONFIG_SYS_NAND_ECCSIZE,
CONFIG_SYS_NAND_ECCBYTES
CFG_SYS_NAND_ECCPOS, CFG_SYS_NAND_ECCSIZE,
CFG_SYS_NAND_ECCBYTES
Defines the size and behavior of the NAND that SPL uses
to read U-Boot
CONFIG_SYS_NAND_U_BOOT_DST
CFG_SYS_NAND_U_BOOT_DST
Location in memory to load U-Boot to
CONFIG_SYS_NAND_U_BOOT_SIZE
CFG_SYS_NAND_U_BOOT_SIZE
Size of image to load
CONFIG_SYS_NAND_U_BOOT_START
CFG_SYS_NAND_U_BOOT_START
Entry point in loaded image to jump to
CONFIG_SPL_RAM_DEVICE

8
arch/arm/include/asm/arch-lpc32xx/config.h
View file

@ -32,17 +32,17 @@
#define NAND_SMALL_BLOCK_PAGE_SIZE 0x200
#if (CONFIG_SYS_NAND_PAGE_SIZE == NAND_LARGE_BLOCK_PAGE_SIZE)
#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
#define CFG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }
#elif (CONFIG_SYS_NAND_PAGE_SIZE == NAND_SMALL_BLOCK_PAGE_SIZE)
#define CONFIG_SYS_NAND_ECCPOS { 10, 11, 12, 13, 14, 15, }
#define CFG_SYS_NAND_ECCPOS { 10, 11, 12, 13, 14, 15, }
#else
#error "CONFIG_SYS_NAND_PAGE_SIZE set to an invalid value"
#endif
#define CONFIG_SYS_NAND_ECCSIZE 0x100
#define CONFIG_SYS_NAND_ECCBYTES 3
#define CFG_SYS_NAND_ECCSIZE 0x100
#define CFG_SYS_NAND_ECCBYTES 3
#endif /* CONFIG_NAND_LPC32XX_SLC */
/* NOR Flash */

8
arch/arm/include/asm/ti-common/davinci_nand.h
View file

@ -18,13 +18,13 @@
#define MASK_CLE 0x10
#define MASK_ALE 0x08
#ifdef CONFIG_SYS_NAND_MASK_CLE
#ifdef CFG_SYS_NAND_MASK_CLE
#undef MASK_CLE
#define MASK_CLE CONFIG_SYS_NAND_MASK_CLE
#define MASK_CLE CFG_SYS_NAND_MASK_CLE
#endif
#ifdef CONFIG_SYS_NAND_MASK_ALE
#ifdef CFG_SYS_NAND_MASK_ALE
#undef MASK_ALE
#define MASK_ALE CONFIG_SYS_NAND_MASK_ALE
#define MASK_ALE CFG_SYS_NAND_MASK_ALE
#endif
struct davinci_emif_regs {

2
arch/arm/mach-kirkwood/include/mach/config.h
View file

@ -35,7 +35,7 @@
*/
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_KIRKWOOD
#define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */
#define CFG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */
#define NAND_ALLOW_ERASE_ALL 1
#endif

2
arch/arm/mach-omap2/mem-common.c
View file

@ -135,7 +135,7 @@ void set_gpmc_cs0(int flash_type)
#if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_CMD_NAND)
case MTD_DEV_TYPE_NAND:
gpmc_regs = gpmc_regs_nand;
base = CONFIG_SYS_NAND_BASE;
base = CFG_SYS_NAND_BASE;
size = GPMC_SIZE_16M;
break;
#endif

20
arch/powerpc/cpu/mpc83xx/elbc/elbc.h
View file

@ -1,16 +1,16 @@
#if defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_0)
#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_1)
#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_2)
#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR2_PRELIM
#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR2_PRELIM
#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR2_PRELIM
#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR2_PRELIM
#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_3)
#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR3_PRELIM
#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR3_PRELIM
#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR3_PRELIM
#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR3_PRELIM
#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_4)
#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR4_PRELIM
#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR4_PRELIM
#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR4_PRELIM
#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR4_PRELIM
#endif

10
arch/powerpc/cpu/mpc83xx/spl_minimal.c
View file

@ -71,16 +71,16 @@ void cpu_init_f (volatile immap_t * im)
* has been determined
*/
#if defined(CONFIG_SYS_NAND_BR_PRELIM) \
&& defined(CONFIG_SYS_NAND_OR_PRELIM) \
#if defined(CFG_SYS_NAND_BR_PRELIM) \
&& defined(CFG_SYS_NAND_OR_PRELIM) \
&& defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \
&& defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM)
set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
set_lbc_br(0, CFG_SYS_NAND_BR_PRELIM);
set_lbc_or(0, CFG_SYS_NAND_OR_PRELIM);
im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM;
im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM;
#else
#error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined
#error CFG_SYS_NAND_BR_PRELIM, CFG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined
#endif
}

4
board/atmel/at91sam9260ek/at91sam9260ek.c
View file

@ -56,10 +56,10 @@ static void at91sam9260ek_nand_hw_init(void)
&smc->cs[3].mode);
/* Configure RDY/BSY */
at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
}
#endif

4
board/atmel/at91sam9261ek/at91sam9261ek.c
View file

@ -78,10 +78,10 @@ static void at91sam9261ek_nand_hw_init(void)
at91_periph_clk_enable(ATMEL_ID_PIOC);
/* Configure RDY/BSY */
at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */

4
board/atmel/at91sam9263ek/at91sam9263ek.c
View file

@ -69,10 +69,10 @@ static void at91sam9263ek_nand_hw_init(void)
at91_periph_clk_enable(ATMEL_ID_PIOCDE);
/* Configure RDY/BSY */
at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
}
#endif

4
board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
View file

@ -63,10 +63,10 @@ void at91sam9m10g45ek_nand_hw_init(void)
at91_periph_clk_enable(ATMEL_ID_PIOC);
/* Configure RDY/BSY */
at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
}
#endif

4
board/atmel/at91sam9rlek/at91sam9rlek.c
View file

@ -64,10 +64,10 @@ static void at91sam9rlek_nand_hw_init(void)
at91_periph_clk_enable(ATMEL_ID_PIOD);
/* Configure RDY/BSY */
at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */
at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */

4
board/atmel/at91sam9x5ek/at91sam9x5ek.c
View file

@ -65,9 +65,9 @@ static void at91sam9x5ek_nand_hw_init(void)
at91_periph_clk_enable(ATMEL_ID_PIOCD);
/* Configure RDY/BSY */
at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */

4
board/atmel/sam9x60ek/sam9x60ek.c
View file

@ -36,9 +36,9 @@ static void sam9x60ek_nand_hw_init(void)
at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 0); /* NAND ALE */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 0); /* NAND CLE */
/* Enable NandFlash */
at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
/* Configure RDY/BSY */
at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);

8
board/bluewater/gurnard/gurnard.c
View file

@ -100,16 +100,16 @@ static int gurnard_nand_hw_init(void)
AT91_SMC_MODE_TDF_CYCLE(3),
&smc->cs[3].mode);
ret = gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand_rdy");
ret = gpio_request(CFG_SYS_NAND_READY_PIN, "nand_rdy");
if (ret)
return ret;
gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
gpio_direction_input(CFG_SYS_NAND_READY_PIN);
/* Enable NandFlash */
ret = gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand_ce");
ret = gpio_request(CFG_SYS_NAND_ENABLE_PIN, "nand_ce");
if (ret)
return ret;
gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
return 0;
}

8
board/calao/usb_a9263/usb_a9263.c
View file

@ -54,12 +54,12 @@ static void usb_a9263_nand_hw_init(void)
at91_periph_clk_enable(ATMEL_ID_PIOCDE);
/* Configure RDY/BSY */
gpio_request(CONFIG_SYS_NAND_READY_PIN, "NAND ready/busy");
gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
gpio_request(CFG_SYS_NAND_READY_PIN, "NAND ready/busy");
gpio_direction_input(CFG_SYS_NAND_READY_PIN);
/* Enable NandFlash */
gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "NAND enable");
gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
gpio_request(CFG_SYS_NAND_ENABLE_PIN, "NAND enable");
gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
}
#endif

6
board/egnite/ethernut5/ethernut5.c
View file

@ -117,11 +117,11 @@ static void ethernut5_nand_hw_init(void)
AT91_SMC_MODE_TDF_CYCLE(2),
&smc->cs[3].mode);
#ifdef CONFIG_SYS_NAND_READY_PIN
#ifdef CFG_SYS_NAND_READY_PIN
/* Ready pin is optional. */
at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
at91_set_pio_input(CFG_SYS_NAND_READY_PIN, 1);
#endif
gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
}
#endif

4
board/esd/meesc/meesc.c
View file

@ -84,10 +84,10 @@ static void meesc_nand_hw_init(void)
&smc->cs[3].mode);
/* Configure RDY/BSY */
gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
gpio_direction_input(CFG_SYS_NAND_READY_PIN);
/* Enable NandFlash */
gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
}
#endif /* CONFIG_CMD_NAND */

4
board/freescale/common/p_corenet/law.c
View file

@ -28,8 +28,8 @@ struct law_entry law_table[] = {
/* Limit DCSR to 32M to access NPC Trace Buffer */
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
#endif
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#ifdef CFG_SYS_NAND_BASE_PHYS
SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#endif
};

4
board/freescale/common/p_corenet/tlb.c
View file

@ -135,13 +135,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 13, BOOKE_PAGESZ_4M, 1),
#endif
#ifdef CONFIG_SYS_NAND_BASE
#ifdef CFG_SYS_NAND_BASE
/*
* *I*G - NAND
* entry 14 and 15 has been used hard coded, they will be disabled
* in cpu_init_f, so we use entry 16 for nand.
*/
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 16, BOOKE_PAGESZ_1M, 1),
#endif

32
board/freescale/ls1043aqds/ls1043aqds.c
View file

@ -84,15 +84,15 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
},
{
"nand",
CONFIG_SYS_NAND_CSPR,
CONFIG_SYS_NAND_CSPR_EXT,
CONFIG_SYS_NAND_AMASK,
CONFIG_SYS_NAND_CSOR,
CFG_SYS_NAND_CSPR,
CFG_SYS_NAND_CSPR_EXT,
CFG_SYS_NAND_AMASK,
CFG_SYS_NAND_CSOR,
{
CONFIG_SYS_NAND_FTIM0,
CONFIG_SYS_NAND_FTIM1,
CONFIG_SYS_NAND_FTIM2,
CONFIG_SYS_NAND_FTIM3
CFG_SYS_NAND_FTIM0,
CFG_SYS_NAND_FTIM1,
CFG_SYS_NAND_FTIM2,
CFG_SYS_NAND_FTIM3
},
},
{
@ -113,15 +113,15 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
{
"nand",
CONFIG_SYS_NAND_CSPR,
CONFIG_SYS_NAND_CSPR_EXT,
CONFIG_SYS_NAND_AMASK,
CONFIG_SYS_NAND_CSOR,
CFG_SYS_NAND_CSPR,
CFG_SYS_NAND_CSPR_EXT,
CFG_SYS_NAND_AMASK,
CFG_SYS_NAND_CSOR,
{
CONFIG_SYS_NAND_FTIM0,
CONFIG_SYS_NAND_FTIM1,
CONFIG_SYS_NAND_FTIM2,
CONFIG_SYS_NAND_FTIM3
CFG_SYS_NAND_FTIM0,
CFG_SYS_NAND_FTIM1,
CFG_SYS_NAND_FTIM2,
CFG_SYS_NAND_FTIM3
},
},
{

34
board/freescale/ls1043ardb/ls1043ardb.c
View file

@ -47,15 +47,15 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
},
{
"nand",
CONFIG_SYS_NAND_CSPR,
CONFIG_SYS_NAND_CSPR_EXT,
CONFIG_SYS_NAND_AMASK,
CONFIG_SYS_NAND_CSOR,
CFG_SYS_NAND_CSPR,
CFG_SYS_NAND_CSPR_EXT,
CFG_SYS_NAND_AMASK,
CFG_SYS_NAND_CSOR,
{
CONFIG_SYS_NAND_FTIM0,
CONFIG_SYS_NAND_FTIM1,
CONFIG_SYS_NAND_FTIM2,
CONFIG_SYS_NAND_FTIM3
CFG_SYS_NAND_FTIM0,
CFG_SYS_NAND_FTIM1,
CFG_SYS_NAND_FTIM2,
CFG_SYS_NAND_FTIM3
},
},
{
@ -76,15 +76,15 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
{
"nand",
CONFIG_SYS_NAND_CSPR,
CONFIG_SYS_NAND_CSPR_EXT,
CONFIG_SYS_NAND_AMASK,
CONFIG_SYS_NAND_CSOR,
CFG_SYS_NAND_CSPR,
CFG_SYS_NAND_CSPR_EXT,
CFG_SYS_NAND_AMASK,
CFG_SYS_NAND_CSOR,
{
CONFIG_SYS_NAND_FTIM0,
CONFIG_SYS_NAND_FTIM1,
CONFIG_SYS_NAND_FTIM2,
CONFIG_SYS_NAND_FTIM3
CFG_SYS_NAND_FTIM0,
CFG_SYS_NAND_FTIM1,
CFG_SYS_NAND_FTIM2,
CFG_SYS_NAND_FTIM3
},
},
{
@ -355,7 +355,7 @@ void nand_fixup(void)
return;
/* Change NAND Flash PGS/SPRZ configuration */
csor = CONFIG_SYS_NAND_CSOR;
csor = CFG_SYS_NAND_CSOR;
if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_2K)
csor = (csor & ~(CSOR_NAND_PGS_MASK)) | CSOR_NAND_PGS_4K;

32
board/freescale/ls1046aqds/ls1046aqds.c
View file

@ -68,15 +68,15 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
},
{
"nand",
CONFIG_SYS_NAND_CSPR,
CONFIG_SYS_NAND_CSPR_EXT,
CONFIG_SYS_NAND_AMASK,
CONFIG_SYS_NAND_CSOR,
CFG_SYS_NAND_CSPR,
CFG_SYS_NAND_CSPR_EXT,
CFG_SYS_NAND_AMASK,
CFG_SYS_NAND_CSOR,
{
CONFIG_SYS_NAND_FTIM0,
CONFIG_SYS_NAND_FTIM1,
CONFIG_SYS_NAND_FTIM2,
CONFIG_SYS_NAND_FTIM3
CFG_SYS_NAND_FTIM0,
CFG_SYS_NAND_FTIM1,
CFG_SYS_NAND_FTIM2,
CFG_SYS_NAND_FTIM3
},
},
{
@ -97,15 +97,15 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
{
"nand",
CONFIG_SYS_NAND_CSPR,
CONFIG_SYS_NAND_CSPR_EXT,
CONFIG_SYS_NAND_AMASK,
CONFIG_SYS_NAND_CSOR,
CFG_SYS_NAND_CSPR,
CFG_SYS_NAND_CSPR_EXT,
CFG_SYS_NAND_AMASK,
CFG_SYS_NAND_CSOR,
{
CONFIG_SYS_NAND_FTIM0,
CONFIG_SYS_NAND_FTIM1,
CONFIG_SYS_NAND_FTIM2,
CONFIG_SYS_NAND_FTIM3
CFG_SYS_NAND_FTIM0,
CFG_SYS_NAND_FTIM1,
CFG_SYS_NAND_FTIM2,
CFG_SYS_NAND_FTIM3
},
},
{

32
board/freescale/ls1088a/ls1088a.c
View file

@ -73,15 +73,15 @@ struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
},
{
"nand",
CONFIG_SYS_NAND_CSPR,
CONFIG_SYS_NAND_CSPR_EXT,
CONFIG_SYS_NAND_AMASK,
CONFIG_SYS_NAND_CSOR,
CFG_SYS_NAND_CSPR,
CFG_SYS_NAND_CSPR_EXT,
CFG_SYS_NAND_AMASK,
CFG_SYS_NAND_CSOR,
{
CONFIG_SYS_NAND_FTIM0,
CONFIG_SYS_NAND_FTIM1,
CONFIG_SYS_NAND_FTIM2,
CONFIG_SYS_NAND_FTIM3
CFG_SYS_NAND_FTIM0,
CFG_SYS_NAND_FTIM1,
CFG_SYS_NAND_FTIM2,
CFG_SYS_NAND_FTIM3
},
},
{
@ -105,15 +105,15 @@ struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
{
"nand",
CONFIG_SYS_NAND_CSPR,
CONFIG_SYS_NAND_CSPR_EXT,
CONFIG_SYS_NAND_AMASK,
CONFIG_SYS_NAND_CSOR,
CFG_SYS_NAND_CSPR,
CFG_SYS_NAND_CSPR_EXT,
CFG_SYS_NAND_AMASK,
CFG_SYS_NAND_CSOR,
{
CONFIG_SYS_NAND_FTIM0,
CONFIG_SYS_NAND_FTIM1,
CONFIG_SYS_NAND_FTIM2,
CONFIG_SYS_NAND_FTIM3
CFG_SYS_NAND_FTIM0,
CFG_SYS_NAND_FTIM1,
CFG_SYS_NAND_FTIM2,
CFG_SYS_NAND_FTIM3
},
},
{

2
board/freescale/p1010rdb/law.c
View file

@ -10,7 +10,7 @@
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_IFC),
SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
};
int num_law_entries = ARRAY_SIZE(law_table);

6
board/freescale/p1010rdb/spl_minimal.c
View file

@ -22,9 +22,9 @@ void board_init_f(ulong bootflag)
u32 plat_ratio;
ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
#if defined(CFG_SYS_NAND_BR_PRELIM) && defined(CFG_SYS_NAND_OR_PRELIM)
set_lbc_br(0, CFG_SYS_NAND_BR_PRELIM);
set_lbc_or(0, CFG_SYS_NAND_OR_PRELIM);
#endif
/* initialize selected port with appropriate baud rate */

2
board/freescale/p1010rdb/tlb.c
View file

@ -68,7 +68,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_256K, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_1M, 1),

4
board/freescale/p1_p2_rdb_pc/law.c
View file

@ -13,8 +13,8 @@ struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#endif
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
#ifdef CFG_SYS_NAND_BASE_PHYS
SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
#endif
};

6
board/freescale/p1_p2_rdb_pc/spl_minimal.c
View file

@ -21,9 +21,9 @@ void board_init_f(ulong bootflag)
u32 plat_ratio;
ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
#if defined(CFG_SYS_NAND_BR_PRELIM) && defined(CFG_SYS_NAND_OR_PRELIM)
set_lbc_br(0, CFG_SYS_NAND_BR_PRELIM);
set_lbc_or(0, CFG_SYS_NAND_OR_PRELIM);
#endif
/* initialize selected port with appropriate baud rate */

4
board/freescale/p1_p2_rdb_pc/tlb.c
View file

@ -67,9 +67,9 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_1M, 1),
#ifdef CONFIG_SYS_NAND_BASE
#ifdef CFG_SYS_NAND_BASE
/* *I*G - NAND */
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_1M, 1),
#endif

4
board/freescale/t102xrdb/law.c
View file

@ -23,8 +23,8 @@ struct law_entry law_table[] = {
#ifdef CONFIG_SYS_DCSRBAR_PHYS
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
#endif
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
#ifdef CFG_SYS_NAND_BASE_PHYS
SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
#endif
};

4
board/freescale/t102xrdb/tlb.c
View file

@ -88,8 +88,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 9, BOOKE_PAGESZ_4M, 1),
#endif
#ifdef CONFIG_SYS_NAND_BASE
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
#ifdef CFG_SYS_NAND_BASE
SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 10, BOOKE_PAGESZ_64K, 1),
#endif

4
board/freescale/t104xrdb/law.c
View file

@ -23,8 +23,8 @@ struct law_entry law_table[] = {
#ifdef CONFIG_SYS_DCSRBAR_PHYS
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
#endif
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
#ifdef CFG_SYS_NAND_BASE_PHYS
SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
#endif
};

4
board/freescale/t104xrdb/tlb.c
View file

@ -101,13 +101,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 9, BOOKE_PAGESZ_4M, 1),
#endif
#ifdef CONFIG_SYS_NAND_BASE
#ifdef CFG_SYS_NAND_BASE
/*
* *I*G - NAND
* entry 14 and 15 has been used hard coded, they will be disabled
* in cpu_init_f, so we use entry 16 for nand.
*/
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 10, BOOKE_PAGESZ_64K, 1),
#endif

4
board/freescale/t208xqds/law.c
View file

@ -25,8 +25,8 @@ struct law_entry law_table[] = {
/* Limit DCSR to 32M to access NPC Trace Buffer */
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
#endif
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
#ifdef CFG_SYS_NAND_BASE_PHYS
SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
#endif
};

4
board/freescale/t208xqds/tlb.c
View file

@ -116,13 +116,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 13, BOOKE_PAGESZ_32M, 1),
#endif
#ifdef CONFIG_SYS_NAND_BASE
#ifdef CFG_SYS_NAND_BASE
/*
* *I*G - NAND
* entry 14 and 15 has been used hard coded, they will be disabled
* in cpu_init_f, so we use entry 16 for nand.
*/
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 16, BOOKE_PAGESZ_64K, 1),
#endif

4
board/freescale/t208xrdb/law.c
View file

@ -25,8 +25,8 @@ struct law_entry law_table[] = {
/* Limit DCSR to 32M to access NPC Trace Buffer */
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
#endif
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
#ifdef CFG_SYS_NAND_BASE_PHYS
SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
#endif
};

4
board/freescale/t208xrdb/tlb.c
View file

@ -116,13 +116,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 13, BOOKE_PAGESZ_32M, 1),
#endif
#ifdef CONFIG_SYS_NAND_BASE
#ifdef CFG_SYS_NAND_BASE
/*
* *I*G - NAND
* entry 14 and 15 has been used hard coded, they will be disabled
* in cpu_init_f, so we use entry 16 for nand.
*/
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 16, BOOKE_PAGESZ_64K, 1),
#endif

4
board/freescale/t4rdb/law.c
View file

@ -22,8 +22,8 @@ struct law_entry law_table[] = {
/* Limit DCSR to 32M to access NPC Trace Buffer */
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
#endif
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
#ifdef CFG_SYS_NAND_BASE_PHYS
SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
#endif
};

4
board/freescale/t4rdb/tlb.c
View file

@ -98,13 +98,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 13, BOOKE_PAGESZ_32M, 1),
#endif
#ifdef CONFIG_SYS_NAND_BASE
#ifdef CFG_SYS_NAND_BASE
/*
* *I*G - NAND
* entry 14 and 15 has been used hard coded, they will be disabled
* in cpu_init_f, so we use entry 16 for nand.
*/
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 16, BOOKE_PAGESZ_64K, 1),
#endif

4
board/gardena/smart-gateway-at91sam/spl.c
View file

@ -53,10 +53,10 @@ static void at91sam9x5ek_nand_hw_init(void)
at91_periph_clk_enable(ATMEL_ID_PIOCD);
/* Configure RDY/BSY */
at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */

2
board/keymile/kmcent2/law.c
View file

@ -14,7 +14,7 @@ struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC),
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
SET_LAW(CONFIG_SYS_QRIO_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
SET_LAW(SYS_LAWAPP_BASE_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_IFC),
/* other application LAW are not used in u-boot */

2
board/keymile/kmcent2/tlb.c
View file

@ -76,7 +76,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
0, 9, BOOKE_PAGESZ_4M, 1),
/* *I*G - NAND */
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 10, BOOKE_PAGESZ_64K, 1),
/* QRIO */

4
board/ronetix/pm9261/pm9261.c
View file

@ -66,10 +66,10 @@ static void pm9261_nand_hw_init(void)
at91_periph_clk_enable(ATMEL_ID_PIOC);
/* Configure RDY/BSY */
gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
gpio_direction_input(CFG_SYS_NAND_READY_PIN);
/* Enable NandFlash */
gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* NANDOE */
at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* NANDWE */

4
board/ronetix/pm9263/pm9263.c
View file

@ -62,10 +62,10 @@ static void pm9263_nand_hw_init(void)
&smc->cs[3].mode);
/* Configure RDY/BSY */
gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
gpio_direction_input(CFG_SYS_NAND_READY_PIN);
/* Enable NandFlash */
gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
}
#endif

6
board/ronetix/pm9g45/pm9g45.c
View file

@ -65,13 +65,13 @@ static void pm9g45_nand_hw_init(void)
at91_periph_clk_enable(ATMEL_ID_PIOC);
#ifdef CONFIG_SYS_NAND_READY_PIN
#ifdef CFG_SYS_NAND_READY_PIN
/* Configure RDY/BSY */
gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
gpio_direction_input(CFG_SYS_NAND_READY_PIN);
#endif
/* Enable NandFlash */
gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
}
#endif

8
board/siemens/corvus/board.c
View file

@ -40,8 +40,8 @@ DECLARE_GLOBAL_DATA_PTR;
static void corvus_request_gpio(void)
{
gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena");
gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy");
gpio_request(CFG_SYS_NAND_ENABLE_PIN, "nand ena");
gpio_request(CFG_SYS_NAND_READY_PIN, "nand rdy");
gpio_request(AT91_PIN_PD7, "d0");
gpio_request(AT91_PIN_PD8, "d1");
gpio_request(AT91_PIN_PA12, "d2");
@ -110,8 +110,8 @@ static void corvus_nand_hw_init(void)
at91_periph_clk_enable(ATMEL_ID_PIOA);
/* Enable NandFlash */
at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
}
#if defined(CONFIG_SPL_BUILD)

8
board/siemens/smartweb/smartweb.c
View file

@ -42,8 +42,8 @@ DECLARE_GLOBAL_DATA_PTR;
static void smartweb_request_gpio(void)
{
gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena");
gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy");
gpio_request(CFG_SYS_NAND_ENABLE_PIN, "nand ena");
gpio_request(CFG_SYS_NAND_READY_PIN, "nand rdy");
gpio_request(AT91_PIN_PA26, "ena PHY");
}
@ -72,10 +72,10 @@ static void smartweb_nand_hw_init(void)
&smc->cs[3].mode);
/* Configure RDY/BSY */
at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
}
static void smartweb_macb_hw_init(void)

10
board/siemens/taurus/taurus.c
View file

@ -41,8 +41,8 @@ DECLARE_GLOBAL_DATA_PTR;
static void taurus_request_gpio(void)
{
gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena");
gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy");
gpio_request(CFG_SYS_NAND_ENABLE_PIN, "nand ena");
gpio_request(CFG_SYS_NAND_READY_PIN, "nand rdy");
gpio_request(AT91_PIN_PA25, "ena PHY");
}
@ -73,10 +73,10 @@ static void taurus_nand_hw_init(void)
&smc->cs[3].mode);
/* Configure RDY/BSY */
at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
}
#if defined(CONFIG_SPL_BUILD)
@ -149,7 +149,7 @@ void spl_board_init(void)
} else {
puts("erase spi flash sector 0\n");
spi_flash_erase(flash, 0,
CONFIG_SYS_NAND_U_BOOT_SIZE);
CFG_SYS_NAND_U_BOOT_SIZE);
}
}
}

2
board/socrates/nand.c
View file

@ -6,7 +6,7 @@
#include <common.h>
#if defined(CONFIG_SYS_NAND_BASE)
#if defined(CFG_SYS_NAND_BASE)
#include <nand.h>
#include <linux/errno.h>
#include <linux/mtd/rawnand.h>

8
common/spl/spl_nand.c
View file

@ -26,12 +26,12 @@ static int spl_nand_load_image(struct spl_image_info *spl_image,
nand_init();
printf("Loading U-Boot from 0x%08x (size 0x%08x) to 0x%08x\n",
CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
CONFIG_SYS_NAND_U_BOOT_DST);
CONFIG_SYS_NAND_U_BOOT_OFFS, CFG_SYS_NAND_U_BOOT_SIZE,
CFG_SYS_NAND_U_BOOT_DST);
nand_spl_load_image(spl_nand_get_uboot_raw_page(),
CONFIG_SYS_NAND_U_BOOT_SIZE,
(void *)CONFIG_SYS_NAND_U_BOOT_DST);
CFG_SYS_NAND_U_BOOT_SIZE,
(void *)CFG_SYS_NAND_U_BOOT_DST);
spl_set_header_raw_uboot(spl_image);
nand_deselect();

8
doc/README.arm-relocation
View file

@ -53,8 +53,8 @@ c) end executes this code
d) this initialize CPU, RAM, ... and copy itself to RAM
(this bin must fit in one page, so board_init_f()
don;t fit in it ... )
e) there it copy u-boot to CONFIG_SYS_NAND_U_BOOT_DST and
starts this image @ CONFIG_SYS_NAND_U_BOOT_START
e) there it copy u-boot to CFG_SYS_NAND_U_BOOT_DST and
starts this image @ CFG_SYS_NAND_U_BOOT_START
f) u-boot code steps through board_init_f() and calculates
the relocation address and copy itself to it
@ -86,8 +86,8 @@ Relocation with SPL (example for the tx25 booting from NAND Flash):
- The First page contains u-boot code from drivers/mtd/nand/raw/mxc_nand_spl.c
which inits the dram, cpu registers, reloacte itself to CONFIG_SPL_TEXT_BASE and loads
the "real" u-boot to CONFIG_SYS_NAND_U_BOOT_DST and starts execution
@CONFIG_SYS_NAND_U_BOOT_START
the "real" u-boot to CFG_SYS_NAND_U_BOOT_DST and starts execution
@CFG_SYS_NAND_U_BOOT_START
- This u-boot does no RAM init, nor CPU register setup. Just look
where it has to copy and relocate itself to this address. If

6
doc/README.omap3
View file

@ -146,11 +146,11 @@ implementation for OMAP3 works for you so the u-boot version should also.
When you require the SPL to read with BCH8 there are two more configs to
change:
* CONFIG_SYS_NAND_ECCPOS (must be the same as .eccpos in
* CFG_SYS_NAND_ECCPOS (must be the same as .eccpos in
GPMC_NAND_HW_BCH8_ECC_LAYOUT defined in
arch/arm/include/asm/arch-omap3/omap_gpmc.h)
* CONFIG_SYS_NAND_ECCSIZE must be 512
* CONFIG_SYS_NAND_ECCBYTES must be 13 for this BCH8 setup
* CFG_SYS_NAND_ECCSIZE must be 512
* CFG_SYS_NAND_ECCBYTES must be 13 for this BCH8 setup
Acknowledgements
================

2
doc/board/ti/am335x_evm.rst
View file

@ -54,7 +54,7 @@ Step-1: Building u-boot for NAND boot
CONFIG_SYS_NAND_PAGE_SIZE number of main bytes in NAND page
CONFIG_SYS_NAND_OOBSIZE number of OOB bytes in NAND page
CONFIG_SYS_NAND_BLOCK_SIZE number of bytes in NAND erase-block
CONFIG_SYS_NAND_ECCPOS ECC map for NAND page
CFG_SYS_NAND_ECCPOS ECC map for NAND page
CONFIG_NAND_OMAP_ECCSCHEME (refer doc/README.nand)
Step-2: Flashing NAND via MMC/SD

12
drivers/mtd/nand/raw/am335x_spl_bch.c
View file

@ -16,13 +16,13 @@
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/rawnand.h>
static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
static int nand_ecc_pos[] = CFG_SYS_NAND_ECCPOS;
static struct mtd_info *mtd;
static struct nand_chip nand_chip;
#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
CONFIG_SYS_NAND_ECCSIZE)
#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
CFG_SYS_NAND_ECCSIZE)
#define ECCTOTAL (ECCSTEPS * CFG_SYS_NAND_ECCBYTES)
/*
@ -155,8 +155,8 @@ static int nand_read_page(int block, int page, void *dst)
u_char ecc_code[ECCTOTAL];
u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
int i;
int eccsize = CONFIG_SYS_NAND_ECCSIZE;
int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
int eccsize = CFG_SYS_NAND_ECCSIZE;
int eccbytes = CFG_SYS_NAND_ECCBYTES;
int eccsteps = ECCSTEPS;
uint8_t *p = dst;
uint32_t data_pos = 0;
@ -207,7 +207,7 @@ void nand_init(void)
*/
mtd = nand_to_mtd(&nand_chip);
nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
(void __iomem *)CONFIG_SYS_NAND_BASE;
(void __iomem *)CFG_SYS_NAND_BASE;
board_nand_init(&nand_chip);
if (nand_chip.select_chip)

40
drivers/mtd/nand/raw/atmel_nand.c
View file

@ -1227,16 +1227,16 @@ static void at91_nand_hwcontrol(struct mtd_info *mtd,
if (ctrl & NAND_CTRL_CHANGE) {
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
| CONFIG_SYS_NAND_MASK_CLE);
IO_ADDR_W &= ~(CFG_SYS_NAND_MASK_ALE
| CFG_SYS_NAND_MASK_CLE);
if (ctrl & NAND_CLE)
IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
IO_ADDR_W |= CFG_SYS_NAND_MASK_CLE;
if (ctrl & NAND_ALE)
IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
IO_ADDR_W |= CFG_SYS_NAND_MASK_ALE;
#ifdef CONFIG_SYS_NAND_ENABLE_PIN
at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN,
#ifdef CFG_SYS_NAND_ENABLE_PIN
at91_set_gpio_value(CFG_SYS_NAND_ENABLE_PIN,
!(ctrl & NAND_NCE));
#endif
this->IO_ADDR_W = (void *) IO_ADDR_W;
@ -1246,10 +1246,10 @@ static void at91_nand_hwcontrol(struct mtd_info *mtd,
writeb(cmd, this->IO_ADDR_W);
}
#ifdef CONFIG_SYS_NAND_READY_PIN
#ifdef CFG_SYS_NAND_READY_PIN
static int at91_nand_ready(struct mtd_info *mtd)
{
return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN);
return at91_get_gpio_value(CFG_SYS_NAND_READY_PIN);
}
#endif
@ -1314,10 +1314,10 @@ static int nand_is_bad_block(int block)
}
#ifdef CONFIG_SPL_NAND_ECC
static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
static int nand_ecc_pos[] = CFG_SYS_NAND_ECCPOS;
#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
CONFIG_SYS_NAND_ECCSIZE)
#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
CFG_SYS_NAND_ECCSIZE)
#define ECCTOTAL (ECCSTEPS * CFG_SYS_NAND_ECCBYTES)
static int nand_read_page(int block, int page, void *dst)
{
@ -1325,8 +1325,8 @@ static int nand_read_page(int block, int page, void *dst)
u_char ecc_calc[ECCTOTAL];
u_char ecc_code[ECCTOTAL];
u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
int eccsize = CONFIG_SYS_NAND_ECCSIZE;
int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
int eccsize = CFG_SYS_NAND_ECCSIZE;
int eccbytes = CFG_SYS_NAND_ECCBYTES;
int eccsteps = ECCSTEPS;
int i;
uint8_t *p = dst;
@ -1415,7 +1415,7 @@ int board_nand_init(struct nand_chip *nand)
nand->read_buf = nand_read_buf;
#endif
nand->cmd_ctrl = at91_nand_hwcontrol;
#ifdef CONFIG_SYS_NAND_READY_PIN
#ifdef CFG_SYS_NAND_READY_PIN
nand->dev_ready = at91_nand_ready;
#else
nand->dev_ready = at91_nand_wait_ready;
@ -1439,8 +1439,8 @@ void nand_init(void)
mtd = nand_to_mtd(&nand_chip);
mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE;
mtd->oobsize = CONFIG_SYS_NAND_OOBSIZE;
nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
nand_chip.IO_ADDR_R = (void __iomem *)CFG_SYS_NAND_BASE;
nand_chip.IO_ADDR_W = (void __iomem *)CFG_SYS_NAND_BASE;
board_nand_init(&nand_chip);
#ifdef CONFIG_SPL_NAND_ECC
@ -1464,11 +1464,11 @@ void nand_deselect(void)
#else
#ifndef CONFIG_SYS_NAND_BASE_LIST
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#ifndef CFG_SYS_NAND_BASE_LIST
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#endif
static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CFG_SYS_NAND_BASE_LIST;
int atmel_nand_chip_init(int devnum, ulong base_addr)
{
@ -1487,7 +1487,7 @@ int atmel_nand_chip_init(int devnum, ulong base_addr)
nand->options = NAND_BUSWIDTH_16;
#endif
nand->cmd_ctrl = at91_nand_hwcontrol;
#ifdef CONFIG_SYS_NAND_READY_PIN
#ifdef CFG_SYS_NAND_READY_PIN
nand->dev_ready = at91_nand_ready;
#endif
nand->chip_delay = 75;

14
drivers/mtd/nand/raw/davinci_nand.c
View file

@ -170,7 +170,7 @@ static u_int32_t nand_davinci_readecc(struct mtd_info *mtd)
u_int32_t ecc = 0;
ecc = __raw_readl(&(davinci_emif_regs->nandfecc[
CONFIG_SYS_NAND_CS - 2]));
CFG_SYS_NAND_CS - 2]));
return ecc;
}
@ -183,8 +183,8 @@ static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
nand_davinci_readecc(mtd);
val = __raw_readl(&davinci_emif_regs->nandfcr);
val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
val |= DAVINCI_NANDFCR_NAND_ENABLE(CFG_SYS_NAND_CS);
val |= DAVINCI_NANDFCR_1BIT_ECC_START(CFG_SYS_NAND_CS);
__raw_writel(val, &davinci_emif_regs->nandfcr);
}
@ -486,8 +486,8 @@ static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
*/
val = __raw_readl(&davinci_emif_regs->nandfcr);
val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
val |= DAVINCI_NANDFCR_NAND_ENABLE(CFG_SYS_NAND_CS);
val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CFG_SYS_NAND_CS);
val |= DAVINCI_NANDFCR_4BIT_ECC_START;
__raw_writel(val, &davinci_emif_regs->nandfcr);
break;
@ -794,8 +794,8 @@ static int davinci_nand_probe(struct udevice *dev)
struct mtd_info *mtd = nand_to_mtd(nand);
int ret;
nand->IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
nand->IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
nand->IO_ADDR_R = (void __iomem *)CFG_SYS_NAND_BASE;
nand->IO_ADDR_W = (void __iomem *)CFG_SYS_NAND_BASE;
davinci_nand_init(nand);

4
drivers/mtd/nand/raw/denali_spl.c
View file

@ -25,9 +25,9 @@
#define BANK(x) ((x) << 24)
static void __iomem *denali_flash_mem =
(void __iomem *)CONFIG_SYS_NAND_DATA_BASE;
(void __iomem *)CFG_SYS_NAND_DATA_BASE;
static void __iomem *denali_flash_reg =
(void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
(void __iomem *)CFG_SYS_NAND_REGS_BASE;
static const int flash_bank;
static int page_size, oob_size, pages_per_block;

6
drivers/mtd/nand/raw/fsl_elbc_nand.c
View file

@ -819,12 +819,12 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr, struct udevice *dev)
#ifndef CONFIG_NAND_FSL_ELBC_DT
#ifndef CONFIG_SYS_NAND_BASE_LIST
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#ifndef CFG_SYS_NAND_BASE_LIST
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#endif
static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] =
CONFIG_SYS_NAND_BASE_LIST;
CFG_SYS_NAND_BASE_LIST;
void board_nand_init(void)
{

12
drivers/mtd/nand/raw/fsl_elbc_spl.c
View file

@ -46,8 +46,8 @@ static int nand_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
#endif
{
fsl_lbc_t *regs = LBC_BASE_ADDR;
uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
const int large = CONFIG_SYS_NAND_OR_PRELIM & OR_FCM_PGS;
uchar *buf = (uchar *)CFG_SYS_NAND_BASE;
const int large = CFG_SYS_NAND_OR_PRELIM & OR_FCM_PGS;
const int block_shift = large ? 17 : 14;
const int block_size = 1 << block_shift;
const int page_size = large ? 2048 : 512;
@ -143,8 +143,8 @@ void nand_boot(void)
* Load U-Boot image from NAND into RAM
*/
nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
CONFIG_SYS_NAND_U_BOOT_SIZE,
(void *)CONFIG_SYS_NAND_U_BOOT_DST);
CFG_SYS_NAND_U_BOOT_SIZE,
(void *)CFG_SYS_NAND_U_BOOT_DST);
#ifdef CONFIG_NAND_ENV_DST
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
@ -161,13 +161,13 @@ void nand_boot(void)
* Clean d-cache and invalidate i-cache, to
* make sure that no stale data is executed.
*/
flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
flush_cache(CFG_SYS_NAND_U_BOOT_DST, CFG_SYS_NAND_U_BOOT_SIZE);
#endif
puts("transfering control\n");
/*
* Jump to U-Boot image
*/
uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
uboot = (void *)CFG_SYS_NAND_U_BOOT_START;
(*uboot)();
}

6
drivers/mtd/nand/raw/fsl_ifc_nand.c
View file

@ -1053,12 +1053,12 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
return 0;
}
#ifndef CONFIG_SYS_NAND_BASE_LIST
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#ifndef CFG_SYS_NAND_BASE_LIST
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#endif
static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] =
CONFIG_SYS_NAND_BASE_LIST;
CFG_SYS_NAND_BASE_LIST;
void board_nand_init(void)
{

20
drivers/mtd/nand/raw/fsl_ifc_spl.c
View file

@ -110,7 +110,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
{
struct fsl_ifc_fcm *gregs = (void *)CONFIG_SYS_IFC_ADDR;
struct fsl_ifc_runtime *ifc = NULL;
uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
uchar *buf = (uchar *)CFG_SYS_NAND_BASE;
int page_size;
int port_size;
int pages_per_blk;
@ -129,8 +129,8 @@ int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
ifc = runtime_regs_address();
/* Get NAND Flash configuration */
csor = CONFIG_SYS_NAND_CSOR;
cspr = CONFIG_SYS_NAND_CSPR;
csor = CFG_SYS_NAND_CSOR;
cspr = CFG_SYS_NAND_CSPR;
port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8;
@ -250,8 +250,8 @@ void nand_boot(void)
* Load U-Boot image from NAND into RAM
*/
nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
CONFIG_SYS_NAND_U_BOOT_SIZE,
(uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
CFG_SYS_NAND_U_BOOT_SIZE,
(uchar *)CFG_SYS_NAND_U_BOOT_DST);
#ifdef CONFIG_NAND_ENV_DST
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
@ -270,7 +270,7 @@ void nand_boot(void)
* Clean d-cache and invalidate i-cache, to
* make sure that no stale data is executed.
*/
flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
flush_cache(CFG_SYS_NAND_U_BOOT_DST, CFG_SYS_NAND_U_BOOT_SIZE);
#endif
#ifdef CONFIG_CHAIN_OF_TRUST
@ -279,11 +279,11 @@ void nand_boot(void)
* calculate U-boot header address using U-boot header size.
*/
#define CONFIG_U_BOOT_HDR_ADDR \
((CONFIG_SYS_NAND_U_BOOT_START + \
CONFIG_SYS_NAND_U_BOOT_SIZE) - \
((CFG_SYS_NAND_U_BOOT_START + \
CFG_SYS_NAND_U_BOOT_SIZE) - \
CONFIG_U_BOOT_HDR_SIZE)
spl_validate_uboot(CONFIG_U_BOOT_HDR_ADDR,
CONFIG_SYS_NAND_U_BOOT_START);
CFG_SYS_NAND_U_BOOT_START);
/*
* In case of failure in validation, spl_validate_uboot would
* not return back in case of Production environment with ITS=1.
@ -293,7 +293,7 @@ void nand_boot(void)
*/
#endif
uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
uboot = (void *)CFG_SYS_NAND_U_BOOT_START;
uboot();
}

2
drivers/mtd/nand/raw/fsmc_nand.c
View file

@ -427,7 +427,7 @@ int fsmc_nand_init(struct nand_chip *nand)
nand->ecc.hwctl = fsmc_enable_hwecc;
nand->cmd_ctrl = fsmc_nand_hwcontrol;
nand->IO_ADDR_R = nand->IO_ADDR_W =
(void __iomem *)CONFIG_SYS_NAND_BASE;
(void __iomem *)CFG_SYS_NAND_BASE;
nand->badblockbits = 7;
mtd = nand_to_mtd(nand);

4
drivers/mtd/nand/raw/kmeter1_nand.c
View file

@ -10,8 +10,8 @@
#include <linux/delay.h>
#include <linux/mtd/rawnand.h>
#define CONFIG_NAND_MODE_REG (void *)(CONFIG_SYS_NAND_BASE + 0x20000)
#define CONFIG_NAND_DATA_REG (void *)(CONFIG_SYS_NAND_BASE + 0x30000)
#define CONFIG_NAND_MODE_REG (void *)(CFG_SYS_NAND_BASE + 0x20000)
#define CONFIG_NAND_DATA_REG (void *)(CFG_SYS_NAND_BASE + 0x30000)
#define read_mode() in_8(CONFIG_NAND_MODE_REG)
#define write_mode(val) out_8(CONFIG_NAND_MODE_REG, val)

22
drivers/mtd/nand/raw/lpc32xx_nand_slc.c
View file

@ -84,7 +84,7 @@ static struct nand_ecclayout lpc32xx_nand_oob_16 = {
};
#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD)
#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CFG_SYS_NAND_ECCSIZE)
/*
* DMA Descriptors
@ -187,7 +187,7 @@ static void lpc32xx_nand_dma_configure(struct nand_chip *chip,
DMAC_CHAN_DEST_AHB1;
/* CTRL descriptor entry for reading/writing Data */
ctrl = (CONFIG_SYS_NAND_ECCSIZE / 4) |
ctrl = (CFG_SYS_NAND_ECCSIZE / 4) |
DMAC_CHAN_SRC_BURST_4 |
DMAC_CHAN_DEST_BURST_4 |
DMAC_CHAN_SRC_WIDTH_32 |
@ -241,7 +241,7 @@ static void lpc32xx_nand_dma_configure(struct nand_chip *chip,
* 2. X'fer 64 bytes of Spare area from Flash to Memory.
*/
for (i = 0; i < size/CONFIG_SYS_NAND_ECCSIZE; i++) {
for (i = 0; i < size/CFG_SYS_NAND_ECCSIZE; i++) {
dmalist_cur = &dmalist[i * 2];
dmalist_cur_ecc = &dmalist[(i * 2) + 1];
@ -337,9 +337,9 @@ static void lpc32xx_nand_xfer(struct mtd_info *mtd, const u8 *buf,
static u32 slc_ecc_copy_to_buffer(u8 *spare, const u32 *ecc, int count)
{
int i;
for (i = 0; i < (count * CONFIG_SYS_NAND_ECCBYTES);
i += CONFIG_SYS_NAND_ECCBYTES) {
u32 ce = ecc[i / CONFIG_SYS_NAND_ECCBYTES];
for (i = 0; i < (count * CFG_SYS_NAND_ECCBYTES);
i += CFG_SYS_NAND_ECCBYTES) {
u32 ce = ecc[i / CFG_SYS_NAND_ECCBYTES];
ce = ~(ce << 2) & 0xFFFFFF;
spare[i+2] = (u8)(ce & 0xFF); ce >>= 8;
spare[i+1] = (u8)(ce & 0xFF); ce >>= 8;
@ -386,9 +386,9 @@ int lpc32xx_correct_data(struct mtd_info *mtd, u_char *dat,
u16 data_offset = 0;
for (i = 0 ; i < ECCSTEPS ; i++) {
r += CONFIG_SYS_NAND_ECCBYTES;
c += CONFIG_SYS_NAND_ECCBYTES;
data_offset += CONFIG_SYS_NAND_ECCSIZE;
r += CFG_SYS_NAND_ECCBYTES;
c += CFG_SYS_NAND_ECCBYTES;
data_offset += CFG_SYS_NAND_ECCSIZE;
ret1 = nand_correct_data(mtd, dat + data_offset, r, c);
if (ret1 < 0)
@ -568,8 +568,8 @@ int board_nand_init(struct nand_chip *lpc32xx_chip)
* These values are predefined
* for both small and large page NAND flash devices.
*/
lpc32xx_chip->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
lpc32xx_chip->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
lpc32xx_chip->ecc.size = CFG_SYS_NAND_ECCSIZE;
lpc32xx_chip->ecc.bytes = CFG_SYS_NAND_ECCBYTES;
lpc32xx_chip->ecc.strength = 1;
if (CONFIG_SYS_NAND_PAGE_SIZE != NAND_LARGE_BLOCK_PAGE_SIZE)

6
drivers/mtd/nand/raw/mxc_nand.c
View file

@ -50,7 +50,7 @@ static struct mxc_nand_host *host = &mxc_host;
/* OOB placement block for use with hardware ecc generation */
#if defined(MXC_NFC_V1)
#ifndef CONFIG_SYS_NAND_LARGEPAGE
#ifndef CFG_SYS_NAND_LARGEPAGE
static struct nand_ecclayout nand_hw_eccoob = {
.eccbytes = 5,
.eccpos = {6, 7, 8, 9, 10},
@ -69,7 +69,7 @@ static struct nand_ecclayout nand_hw_eccoob2k = {
};
#endif
#elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
#ifndef CONFIG_SYS_NAND_LARGEPAGE
#ifndef CFG_SYS_NAND_LARGEPAGE
static struct nand_ecclayout nand_hw_eccoob = {
.eccbytes = 9,
.eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
@ -1219,7 +1219,7 @@ int board_nand_init(struct nand_chip *this)
if (is_16bit_nand())
this->options |= NAND_BUSWIDTH_16;
#ifdef CONFIG_SYS_NAND_LARGEPAGE
#ifdef CFG_SYS_NAND_LARGEPAGE
host->pagesize_2k = 1;
this->ecc.layout = &nand_hw_eccoob2k;
#else

8
drivers/mtd/nand/raw/mxc_nand_spl.c
View file

@ -332,14 +332,14 @@ __used void nand_boot(void)
__attribute__((noreturn)) void (*uboot)(void);
/*
* CONFIG_SYS_NAND_U_BOOT_OFFS and CONFIG_SYS_NAND_U_BOOT_SIZE must
* CONFIG_SYS_NAND_U_BOOT_OFFS and CFG_SYS_NAND_U_BOOT_SIZE must
* be aligned to full pages
*/
if (!nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
CONFIG_SYS_NAND_U_BOOT_SIZE,
(uchar *)CONFIG_SYS_NAND_U_BOOT_DST)) {
CFG_SYS_NAND_U_BOOT_SIZE,
(uchar *)CFG_SYS_NAND_U_BOOT_DST)) {
/* Copy from NAND successful, start U-Boot */
uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
uboot = (void *)CFG_SYS_NAND_U_BOOT_START;
uboot();
} else {
/* Unrecoverable error when copying from NAND */

6
drivers/mtd/nand/raw/nand.c
View file

@ -11,8 +11,8 @@
#include <linux/mtd/concat.h>
#include <linux/mtd/rawnand.h>
#ifndef CONFIG_SYS_NAND_BASE_LIST
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#ifndef CFG_SYS_NAND_BASE_LIST
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#endif
int nand_curr_device = -1;
@ -21,7 +21,7 @@ static struct mtd_info *nand_info[CONFIG_SYS_MAX_NAND_DEVICE];
#if !CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT)
static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
static ulong base_address[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
static ulong base_address[CONFIG_SYS_MAX_NAND_DEVICE] = CFG_SYS_NAND_BASE_LIST;
#endif
static char dev_name[CONFIG_SYS_MAX_NAND_DEVICE][8];

6
drivers/mtd/nand/raw/nand_spl_load.c
View file

@ -20,8 +20,8 @@ void nand_boot(void)
* Load U-Boot image from NAND into RAM
*/
nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
CONFIG_SYS_NAND_U_BOOT_SIZE,
(void *)CONFIG_SYS_NAND_U_BOOT_DST);
CFG_SYS_NAND_U_BOOT_SIZE,
(void *)CFG_SYS_NAND_U_BOOT_DST);
#ifdef CONFIG_NAND_ENV_DST
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
@ -36,6 +36,6 @@ void nand_boot(void)
/*
* Jump to U-Boot image
*/
uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
uboot = (void *)CFG_SYS_NAND_U_BOOT_START;
(*uboot)();
}

16
drivers/mtd/nand/raw/nand_spl_simple.c
View file

@ -10,13 +10,13 @@
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/rawnand.h>
static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
static int nand_ecc_pos[] = CFG_SYS_NAND_ECCPOS;
static struct mtd_info *mtd;
static struct nand_chip nand_chip;
#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
CONFIG_SYS_NAND_ECCSIZE)
#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
CFG_SYS_NAND_ECCSIZE)
#define ECCTOTAL (ECCSTEPS * CFG_SYS_NAND_ECCBYTES)
#if (CONFIG_SYS_NAND_PAGE_SIZE <= 512)
@ -139,8 +139,8 @@ static int nand_read_page(int block, int page, uchar *dst)
u_char ecc_code[ECCTOTAL];
u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
int i;
int eccsize = CONFIG_SYS_NAND_ECCSIZE;
int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
int eccsize = CFG_SYS_NAND_ECCSIZE;
int eccbytes = CFG_SYS_NAND_ECCBYTES;
int eccsteps = ECCSTEPS;
uint8_t *p = dst;
@ -170,8 +170,8 @@ static int nand_read_page(int block, int page, void *dst)
u_char ecc_code[ECCTOTAL];
u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
int i;
int eccsize = CONFIG_SYS_NAND_ECCSIZE;
int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
int eccsize = CFG_SYS_NAND_ECCSIZE;
int eccbytes = CFG_SYS_NAND_ECCBYTES;
int eccsteps = ECCSTEPS;
uint8_t *p = dst;
@ -212,7 +212,7 @@ void nand_init(void)
*/
mtd = nand_to_mtd(&nand_chip);
nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
(void __iomem *)CONFIG_SYS_NAND_BASE;
(void __iomem *)CFG_SYS_NAND_BASE;
board_nand_init(&nand_chip);
#ifdef CONFIG_SPL_NAND_SOFTECC

2
drivers/mtd/nand/raw/omap_gpmc.c
View file

@ -407,7 +407,7 @@ static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int le
cnt = PREFETCH_STATUS_FIFO_CNT(cnt);
for (i = 0; i < cnt / 4; i++) {
*buf++ = readl(CONFIG_SYS_NAND_BASE);
*buf++ = readl(CFG_SYS_NAND_BASE);
len -= 4;
}
} while (len);

2
drivers/mtd/nand/raw/vf610_nfc.c
View file

@ -812,7 +812,7 @@ void board_nand_init(void)
return;
}
nfc->regs = (void __iomem *)CONFIG_SYS_NAND_BASE;
nfc->regs = (void __iomem *)CFG_SYS_NAND_BASE;
err = vf610_nfc_nand_init(nfc, 0);
if (err)
printf("VF610 NAND init failed (err %d)\n", err);

4
include/configs/M5329EVB.h
View file

@ -93,8 +93,8 @@
#endif
#ifdef CONFIG_CMD_NAND
# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
# define CFG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
# define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
# define NAND_ALLOW_ERASE_ALL 1
#endif

4
include/configs/M5373EVB.h
View file

@ -94,8 +94,8 @@
# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
#endif
# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
# define CFG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
# define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
# define NAND_ALLOW_ERASE_ALL 1
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE

2
include/configs/MCR3000.h
View file

@ -82,6 +82,6 @@
/* Ethernet configuration part */
/* NAND configuration part */
#define CONFIG_SYS_NAND_BASE 0x0C000000
#define CFG_SYS_NAND_BASE 0x0C000000
#endif /* __CONFIG_H */

2
include/configs/MPC837XERDB.h
View file

@ -141,7 +141,7 @@
/*
* NAND Flash on the Local Bus
*/
#define CONFIG_SYS_NAND_BASE 0xE0600000
#define CFG_SYS_NAND_BASE 0xE0600000
/* Vitesse 7385 */

78
include/configs/P1010RDB.h
View file

@ -36,18 +36,18 @@
#ifdef CONFIG_MTD_RAW_NAND
#ifdef CONFIG_NXP_ESBC
#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
#define CFG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
#define CFG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
#define CFG_SYS_NAND_U_BOOT_START 0x00200000
#else
#ifdef CONFIG_TPL_BUILD
#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
#define CFG_SYS_NAND_U_BOOT_SIZE (576 << 10)
#define CFG_SYS_NAND_U_BOOT_DST (0x11000000)
#define CFG_SYS_NAND_U_BOOT_START (0x11000000)
#elif defined(CONFIG_SPL_BUILD)
#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
#define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
#define CFG_SYS_NAND_U_BOOT_SIZE (128 << 10)
#define CFG_SYS_NAND_U_BOOT_DST 0xD0000000
#define CFG_SYS_NAND_U_BOOT_START 0xD0000000
#endif
#endif
#endif
@ -167,23 +167,23 @@ extern unsigned long get_sdram_size(void);
/* CFI for NOR Flash */
/* NAND Flash on IFC */
#define CONFIG_SYS_NAND_BASE 0xff800000
#define CFG_SYS_NAND_BASE 0xff800000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
#define CFG_SYS_NAND_BASE_PHYS 0xfff800000ull
#else
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
#endif
#define CONFIG_MTD_PARTITION
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_NAND \
| CSPR_V)
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
#if defined(CONFIG_TARGET_P1010RDB_PA)
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
@ -192,7 +192,7 @@ extern unsigned long get_sdram_size(void);
| CSOR_NAND_PB(32)) /* 32 Pages Per Block */
#elif defined(CONFIG_TARGET_P1010RDB_PB)
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
@ -201,49 +201,49 @@ extern unsigned long get_sdram_size(void);
| CSOR_NAND_PB(128)) /*Pages Per Block = 128 */
#endif
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_TARGET_P1010RDB_PA)
/* NAND Flash Timing Params */
#define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
#define CFG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
FTIM0_NAND_TWP(0x0C) | \
FTIM0_NAND_TWCHT(0x04) | \
FTIM0_NAND_TWH(0x05)
#define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
#define CFG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
FTIM1_NAND_TWBE(0x1d) | \
FTIM1_NAND_TRR(0x07) | \
FTIM1_NAND_TRP(0x0c)
#define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
#define CFG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
FTIM2_NAND_TREH(0x05) | \
FTIM2_NAND_TWHRE(0x0f)
#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
#define CFG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
#elif defined(CONFIG_TARGET_P1010RDB_PB)
/* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x07) | \
FTIM0_NAND_TWH(0x0a))
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0x0e) | \
FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
FTIM2_NAND_TREH(0x0a) | \
FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3 0x0
#define CFG_SYS_NAND_FTIM3 0x0
#endif
/* Set up IFC registers for boot location NOR/NAND */
#if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
@ -259,13 +259,13 @@ extern unsigned long get_sdram_size(void);
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#endif
/* CPLD on IFC */

12
include/configs/P2041RDB.h
View file

@ -111,22 +111,22 @@
/* Nand Flash */
#ifdef CONFIG_NAND_FSL_ELBC
#define CONFIG_SYS_NAND_BASE 0xffa00000
#define CFG_SYS_NAND_BASE 0xffa00000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
#define CFG_SYS_NAND_BASE_PHYS 0xfffa00000ull
#else
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
#endif
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
#define CFG_SYS_NAND_BASE_LIST {CFG_SYS_NAND_BASE}
/* NAND flash config */
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
#define CFG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
#define CFG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
| OR_FCM_PGS /* Large Page*/ \
| OR_FCM_CSCT \
| OR_FCM_CST \

64
include/configs/T102xRDB.h
View file

@ -22,9 +22,9 @@
#define BOOT_PAGE_OFFSET 0x27000
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
#define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#define CFG_SYS_NAND_U_BOOT_DST 0x30000000
#define CFG_SYS_NAND_U_BOOT_START 0x30000000
#endif
#ifdef CONFIG_SPIFLASH
@ -189,21 +189,21 @@
#endif
/* NAND Flash on IFC */
#define CONFIG_SYS_NAND_BASE 0xff800000
#define CFG_SYS_NAND_BASE 0xff800000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE)
#else
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
#endif
#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
#define CFG_SYS_NAND_CSPR_EXT (0xf)
#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
| CSPR_MSEL_NAND /* MSEL = NAND */ \
| CSPR_V)
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
#if defined(CONFIG_TARGET_T1024RDB)
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
@ -211,7 +211,7 @@
| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
#elif defined(CONFIG_TARGET_T1023RDB)
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
@ -221,30 +221,30 @@
#endif
/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x07) | \
FTIM0_NAND_TWH(0x0a))
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0x0e) | \
FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
FTIM2_NAND_TREH(0x0a) | \
FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3 0x0
#define CFG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
@ -262,14 +262,14 @@
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#define CONFIG_HWCONFIG

62
include/configs/T104xRDB.h
View file

@ -25,13 +25,13 @@
* HDR would be appended at end of image and copied to DDR along
* with U-Boot image.
*/
#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \
#define CFG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \
CONFIG_U_BOOT_HDR_SIZE)
#else
#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#endif
#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
#define CFG_SYS_NAND_U_BOOT_DST 0x30000000
#define CFG_SYS_NAND_U_BOOT_START 0x30000000
#endif
#ifdef CONFIG_SPIFLASH
@ -178,17 +178,17 @@
#define CONFIG_SYS_CS2_FTIM3 0x0
/* NAND Flash on IFC */
#define CONFIG_SYS_NAND_BASE 0xff800000
#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
#define CFG_SYS_NAND_BASE 0xff800000
#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE)
#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
#define CFG_SYS_NAND_CSPR_EXT (0xf)
#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
| CSPR_MSEL_NAND /* MSEL = NAND */ \
| CSPR_V)
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
@ -197,30 +197,30 @@
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x07) | \
FTIM0_NAND_TWH(0x0a))
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0x0e) | \
FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
FTIM2_NAND_TREH(0x0a) | \
FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3 0x0
#define CFG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
@ -238,14 +238,14 @@
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#define CONFIG_HWCONFIG

60
include/configs/T208xQDS.h
View file

@ -29,9 +29,9 @@
#define BOOT_PAGE_OFFSET 0x27000
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
#define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#define CFG_SYS_NAND_U_BOOT_DST 0x00200000
#define CFG_SYS_NAND_U_BOOT_START 0x00200000
#endif
#ifdef CONFIG_SPIFLASH
@ -166,17 +166,17 @@
#define CONFIG_SYS_CS3_FTIM3 0x0
/* NAND Flash on IFC */
#define CONFIG_SYS_NAND_BASE 0xff800000
#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
#define CFG_SYS_NAND_BASE 0xff800000
#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE)
#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
#define CFG_SYS_NAND_CSPR_EXT (0xf)
#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
| CSPR_MSEL_NAND /* MSEL = NAND */ \
| CSPR_V)
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
@ -185,30 +185,30 @@
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x07) | \
FTIM0_NAND_TWH(0x0a))
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0x0e) | \
FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
FTIM2_NAND_TREH(0x0a) | \
FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3 0x0
#define CFG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
@ -242,14 +242,14 @@
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#define CONFIG_HWCONFIG

60
include/configs/T208xRDB.h
View file

@ -24,9 +24,9 @@
#define BOOT_PAGE_OFFSET 0x27000
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
#define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#define CFG_SYS_NAND_U_BOOT_DST 0x00200000
#define CFG_SYS_NAND_U_BOOT_START 0x00200000
#endif
#ifdef CONFIG_SPIFLASH
@ -142,17 +142,17 @@
#define CONFIG_SYS_CS2_FTIM3 0x0
/* NAND Flash on IFC */
#define CONFIG_SYS_NAND_BASE 0xff800000
#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
#define CFG_SYS_NAND_BASE 0xff800000
#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE)
#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
#define CFG_SYS_NAND_CSPR_EXT (0xf)
#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
| CSPR_MSEL_NAND /* MSEL = NAND */ \
| CSPR_V)
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
@ -161,30 +161,30 @@
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x07) | \
FTIM0_NAND_TWH(0x0a))
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0x0e) | \
FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
FTIM2_NAND_TREH(0x0a) | \
FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3 0x0
#define CFG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
@ -202,14 +202,14 @@
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#define CONFIG_HWCONFIG

54
include/configs/T4240RDB.h
View file

@ -197,17 +197,17 @@
+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
/* NAND Flash on IFC */
#define CONFIG_SYS_NAND_BASE 0xff800000
#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
#define CFG_SYS_NAND_BASE 0xff800000
#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE)
#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
#define CFG_SYS_NAND_CSPR_EXT (0xf)
#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
| CSPR_MSEL_NAND /* MSEL = NAND */ \
| CSPR_V)
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
@ -216,30 +216,30 @@
| CSOR_NAND_PB(128)) /*Page Per Block = 128*/
/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x07) | \
FTIM0_NAND_TWH(0x0a))
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0x0e) | \
FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
FTIM2_NAND_TREH(0x0a) | \
FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3 0x0
#define CFG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
@ -257,14 +257,14 @@
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR

6
include/configs/am335x_evm.h
View file

@ -171,7 +171,7 @@
#ifdef CONFIG_MTD_RAW_NAND
/* NAND: device related configs */
/* NAND: driver related configs */
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
26, 27, 28, 29, 30, 31, 32, 33, \
@ -179,8 +179,8 @@
42, 43, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56, 57, }
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
#define CFG_SYS_NAND_ECCSIZE 512
#define CFG_SYS_NAND_ECCBYTES 14
#endif /* !CONFIG_MTD_RAW_NAND */
/* USB Device Firmware Update support */

6
include/configs/am335x_guardian.h
View file

@ -91,7 +91,7 @@
#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \
@ -113,8 +113,8 @@
190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \
200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \
}
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 26
#define CFG_SYS_NAND_ECCSIZE 512
#define CFG_SYS_NAND_ECCBYTES 26
#define MTDIDS_DEFAULT "nand0=nand.0"
#endif /* CONFIG_MTD_RAW_NAND */

6
include/configs/am335x_igep003x.h
View file

@ -95,7 +95,7 @@
/* NAND support */
/* NAND config */
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
26, 27, 28, 29, 30, 31, 32, 33, \
@ -103,7 +103,7 @@
42, 43, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56, 57, }
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
#define CFG_SYS_NAND_ECCSIZE 512
#define CFG_SYS_NAND_ECCBYTES 14
#endif /* ! __CONFIG_IGEP003X_H */

8
include/configs/am3517_evm.h
View file

@ -16,16 +16,16 @@
/* Board NAND Info. */
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, 10, \
#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, 10, \
11, 12, 13, 14, 16, 17, 18, 19, 20, \
21, 22, 23, 24, 25, 26, 27, 28, 30, \
31, 32, 33, 34, 35, 36, 37, 38, 39, \
40, 41, 42, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56 }
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 13
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
#define CFG_SYS_NAND_ECCSIZE 512
#define CFG_SYS_NAND_ECCBYTES 13
#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
/* NAND block size is 128 KiB. Synchronize these values with
* corresponding Device Tree entries in Linux:
* MLO(SPL) 4 * NAND_BLOCK_SIZE = 512 KiB @ 0x000000

6
include/configs/am43xx_evm.h
View file

@ -120,7 +120,7 @@
#ifdef CONFIG_MTD_RAW_NAND
/* NAND: device related configs */
/* NAND: driver related configs */
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \
@ -142,8 +142,8 @@
190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \
200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \
}
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 26
#define CFG_SYS_NAND_ECCSIZE 512
#define CFG_SYS_NAND_ECCBYTES 26
#define NANDARGS \
"nandargs=setenv bootargs console=${console} " \
"${optargs} " \

10
include/configs/at91sam9260ek.h
View file

@ -43,11 +43,11 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CFG_SYS_NAND_MASK_ALE (1 << 21)
#define CFG_SYS_NAND_MASK_CLE (1 << 22)
#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CFG_SYS_NAND_READY_PIN AT91_PIN_PC13
#endif
/* USB */

10
include/configs/at91sam9261ek.h
View file

@ -24,13 +24,13 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CFG_SYS_NAND_BASE 0x40000000
/* our ALE is AD22 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
#define CFG_SYS_NAND_MASK_ALE (1 << 22)
/* our CLE is AD21 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 21)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC15
#define CFG_SYS_NAND_MASK_CLE (1 << 21)
#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CFG_SYS_NAND_READY_PIN AT91_PIN_PC15
#endif

10
include/configs/at91sam9263ek.h
View file

@ -150,13 +150,13 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
#define CFG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22
#define CFG_SYS_NAND_MASK_CLE (1 << 22)
#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
#define CFG_SYS_NAND_READY_PIN AT91_PIN_PA22
#endif
/* USB */

18
include/configs/at91sam9m10g45ek.h
View file

@ -20,23 +20,23 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
#define CFG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8
#define CFG_SYS_NAND_MASK_CLE (1 << 22)
#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CFG_SYS_NAND_READY_PIN AT91_PIN_PC8
#endif
#ifdef CONFIG_SD_BOOT
#elif CONFIG_NAND_BOOT
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
#define CFG_SYS_NAND_U_BOOT_SIZE 0x80000
#define CONFIG_SYS_NAND_ECCSIZE 256
#define CONFIG_SYS_NAND_ECCBYTES 3
#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
#define CFG_SYS_NAND_ECCSIZE 256
#define CFG_SYS_NAND_ECCBYTES 3
#define CFG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }
#endif

10
include/configs/at91sam9n12ek.h
View file

@ -21,11 +21,11 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(4)
#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PD(5)
#define CFG_SYS_NAND_BASE 0x40000000
#define CFG_SYS_NAND_MASK_ALE (1 << 21)
#define CFG_SYS_NAND_MASK_CLE (1 << 22)
#define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(4)
#define CFG_SYS_NAND_READY_PIN GPIO_PIN_PD(5)
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \

10
include/configs/at91sam9rlek.h
View file

@ -25,13 +25,13 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
#define CFG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PB6
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD17
#define CFG_SYS_NAND_MASK_CLE (1 << 22)
#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PB6
#define CFG_SYS_NAND_READY_PIN AT91_PIN_PD17
#endif

10
include/configs/at91sam9x5ek.h
View file

@ -27,13 +27,13 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CFG_SYS_NAND_BASE 0x40000000
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
#define CFG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
#define CFG_SYS_NAND_MASK_CLE (1 << 22)
#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
#define CFG_SYS_NAND_READY_PIN AT91_PIN_PD5
#endif
/* SPL */

8
include/configs/baltos.h
View file

@ -195,7 +195,7 @@
#ifndef CONFIG_NOR_BOOT
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
26, 27, 28, 29, 30, 31, 32, 33, \
@ -203,9 +203,9 @@
42, 43, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56, 57, }
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
#define CFG_SYS_NAND_ECCSIZE 512
#define CFG_SYS_NAND_ECCBYTES 14
#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
#endif
#endif

6
include/configs/chiliboard.h
View file

@ -108,7 +108,7 @@
/* NAND: device related configs */
/* NAND: driver related configs */
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
26, 27, 28, 29, 30, 31, 32, 33, \
@ -116,7 +116,7 @@
42, 43, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56, 57, }
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
#define CFG_SYS_NAND_ECCSIZE 512
#define CFG_SYS_NAND_ECCBYTES 14
#endif /* ! __CONFIG_CHILIBOARD_H */

2
include/configs/cm_fx6.h
View file

@ -128,7 +128,7 @@
#include <config_distro_bootcmd.h>
/* NAND */
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CFG_SYS_NAND_BASE 0x40000000
/* APBH DMA is required for NAND support */
/* Ethernet */

6
include/configs/cm_t43.h
View file

@ -22,9 +22,9 @@
#endif
/* NAND support */
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
#define CFG_SYS_NAND_ECCSIZE 512
#define CFG_SYS_NAND_ECCBYTES 14
#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
26, 27, 28, 29, 30, 31, 32, 33, \

4
include/configs/colibri-imx6ull.h
View file

@ -122,8 +122,8 @@
#ifdef CONFIG_TARGET_COLIBRI_IMX6ULL_NAND
/* NAND stuff */
/* used to initialize CONFIG_SYS_NAND_BASE_LIST which is unused */
#define CONFIG_SYS_NAND_BASE -1
/* used to initialize CFG_SYS_NAND_BASE_LIST which is unused */
#define CFG_SYS_NAND_BASE -1
#endif
/* USB Configs */

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