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ARM: dts: stm32: Fix and expand PLL configuration comments

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Fix the frequencies listed in PLL configuration comments to match
the actual frequencies programmed into hardware. Furthermore, add
a comment which explains how those frequencies are calculated, so
it won't be necessary to look it up all over the datasheet and
make more mistakes in the calculation in the future.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
This commit is contained in:
Marek Vasut 2022-10-11 22:42:44 +02:00 • committed by Patrice Chotard
parent 0de10e2fe1
commit 1587e689b3
2 changed files with 32 additions and 2 deletions
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17
arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
View file

@ -190,6 +190,21 @@
CLK_LPTIM45_LSE
>;
/*
* cfg = < DIVM1 DIVN P Q R PQR(p,q,r) >;
* frac = < f >;
*
* PRQ(p,q,r) ... for p,q,r: 0-output disabled / 1-output enabled
* DIVN ... actually multiplier, but RCC_PLL1CFGR1 calls the field DIVN
* m ... for PLL1,2: m=2 ; for PLL3,4: m=1
* XTAL = 24 MHz
*
* VCO = ( XTAL / (DIVM1 + 1) ) * m * ( DIVN + 1 + ( f / 8192 ) )
* P = VCO / (P + 1)
* Q = VCO / (Q + 1)
* R = VCO / (R + 1)
*/
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
compatible = "st,stm32mp1-pll";
@ -208,7 +223,7 @@
u-boot,dm-pre-reloc;
};
/* VCO = 600.0 MHz => P = 50, Q = 50, R = 50 */
/* VCO = 600.0 MHz => P = 100, Q = 50, R = 50 */
pll4: st,pll@3 {
compatible = "st,stm32mp1-pll";
reg = <3>;

17
arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
View file

@ -144,6 +144,21 @@
CLK_LPTIM45_LSE
>;
/*
* cfg = < DIVM1 DIVN P Q R PQR(p,q,r) >;
* frac = < f >;
*
* PRQ(p,q,r) ... for p,q,r: 0-output disabled / 1-output enabled
* DIVN ... actually multiplier, but RCC_PLL1CFGR1 calls the field DIVN
* m ... for PLL1,2: m=2 ; for PLL3,4: m=1
* XTAL = 24 MHz
*
* VCO = ( XTAL / (DIVM1 + 1) ) * m * ( DIVN + 1 + ( f / 8192 ) )
* P = VCO / (P + 1)
* Q = VCO / (Q + 1)
* R = VCO / (R + 1)
*/
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
compatible = "st,stm32mp1-pll";
@ -162,7 +177,7 @@
u-boot,dm-pre-reloc;
};
/* VCO = 600.0 MHz => P = 99, Q = 74, R = 99 */
/* VCO = 594.0 MHz => P = 99, Q = 74, R = 99 */
pll4: st,pll@3 {
compatible = "st,stm32mp1-pll";
reg = <3>;