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arm: dts: Add i.MX93 SoC DTSi file
Add the DTSi file and DT header files for i.MX93 SoC Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Alice Guo <alice.guo@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Peng Fan
Stefano Babic
parent
5f77e669df
commit
0da3d96e10
3 changed files with 903 additions and 0 deletions
688
arch/arm/dts/imx93.dtsi
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688
arch/arm/dts/imx93.dtsi
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2021 NXP
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*/
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#include <dt-bindings/clock/imx93-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/thermal/thermal.h>
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#include <dt-bindings/power/imx93-power.h>
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#include <dt-bindings/usb/pd.h>
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#include "imx93-pinfunc.h"
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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gpio0 = &gpio1;
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gpio1 = &gpio2;
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gpio2 = &gpio3;
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gpio3 = &gpio4;
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mmc0 = &usdhc1;
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mmc1 = &usdhc2;
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mmc2 = &usdhc3;
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ethernet0 = &fec;
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ethernet1 = &eqos;
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serial0 = &lpuart1;
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serial1 = &lpuart2;
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serial2 = &lpuart3;
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serial3 = &lpuart4;
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serial4 = &lpuart5;
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serial5 = &lpuart6;
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serial6 = &lpuart7;
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serial7 = &lpuart8;
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i2c0 = &lpi2c1;
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i2c1 = &lpi2c2;
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i2c2 = &lpi2c3;
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i2c3 = &lpi2c4;
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i2c4 = &lpi2c5;
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i2c5 = &lpi2c6;
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usb0 = &usbotg1;
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usb1 = &usbotg2;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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A55_0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0>;
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enable-method = "psci";
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#cooling-cells = <2>;
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};
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A55_1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x100>;
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enable-method = "psci";
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#cooling-cells = <2>;
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};
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};
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osc_32k: clock-osc-32k {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "osc_32k";
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};
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osc_24m: clock-osc-24m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "osc_24m";
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};
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clk_ext1: clock-ext1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <133000000>;
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clock-output-names = "clk_ext1";
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <24000000>;
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arm,no-tick-in-suspend;
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interrupt-parent = <&gic>;
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};
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gic: interrupt-controller@48000000 {
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compatible = "arm,gic-v3";
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reg = <0 0x48000000 0 0x10000>,
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<0 0x48040000 0 0xc0000>;
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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};
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soc@0 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x0 0x80000000>,
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<0x28000000 0x0 0x28000000 0x10000000>;
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aips1: bus@44000000 {
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compatible = "fsl,aips-bus", "simple-bus";
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reg = <0x44000000 0x800000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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mu1: mailbox@44230000 {
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compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
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reg = <0x44230000 0x10000>;
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interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <2>;
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status = "disabled";
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};
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anomix_ns_gpr: blk-ctrl-anomix@42420000 {
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compatible = "syscon";
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reg = <0x44210000 0x1000>;
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};
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system_counter: timer@44290000 {
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compatible = "nxp,sysctr-timer";
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reg = <0x44290000 0x30000>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&osc_24m>;
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clock-names = "per";
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};
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i3c1: i3c-master@44330000 {
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#address-cells = <3>;
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#size-cells = <0>;
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compatible = "fsl,imx93-i3c-master", "silvaco,i3c-master";
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reg = <0x44330000 0x10000>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_I3C1_GATE>,
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<&clk IMX93_CLK_I3C1_GATE>,
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<&clk IMX93_CLK_DUMMY>;
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clock-names = "pclk", "fast_clk", "slow_clk";
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status = "disabled";
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};
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lpi2c1: i2c@44340000 {
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compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
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reg = <0x44340000 0x10000>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_LPI2C1_GATE>,
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<&clk IMX93_CLK_LPI2C1_GATE>;
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clock-names = "per", "ipg";
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status = "disabled";
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};
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lpi2c2: i2c@44350000 {
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compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
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reg = <0x44350000 0x10000>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_LPI2C2_GATE>,
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<&clk IMX93_CLK_LPI2C2_GATE>;
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clock-names = "per", "ipg";
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status = "disabled";
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};
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lpspi1: spi@44360000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
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reg = <0x44360000 0x10000>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_LPSPI1_GATE>,
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<&clk IMX93_CLK_LPSPI1_GATE>;
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clock-names = "per", "ipg";
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status = "disabled";
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};
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lpspi2: spi@44370000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
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reg = <0x44370000 0x10000>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_LPSPI2_GATE>,
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<&clk IMX93_CLK_LPSPI2_GATE>;
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clock-names = "per", "ipg";
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status = "disabled";
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};
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lpuart1: serial@44380000 {
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compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart",
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"fsl,imx7ulp-lpuart";
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reg = <0x44380000 0x1000>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_LPUART1_GATE>;
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clock-names = "ipg";
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status = "disabled";
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};
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lpuart2: serial@44390000 {
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compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart",
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"fsl,imx7ulp-lpuart";
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reg = <0x44390000 0x1000>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_LPUART2_GATE>;
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clock-names = "ipg";
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status = "disabled";
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};
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iomuxc: pinctrl@443c0000 {
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compatible = "fsl,imx93-iomuxc";
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reg = <0x443c0000 0x10000>;
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};
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clk: clock-controller@44450000 {
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compatible = "fsl,imx93-ccm";
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reg = <0x44450000 0x10000>;
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#clock-cells = <1>;
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clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>;
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clock-names = "osc_32k", "osc_24m", "clk_ext1";
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assigned-clocks = <&clk IMX93_CLK_AUDIO_PLL>;
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assigned-clock-rates = <393216000>;
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status = "okay";
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};
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anatop: anatop@44480000 {
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compatible = "fsl,imx93-anatop", "syscon";
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reg = <0x44480000 0x10000>;
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};
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adc1: adc@44530000 {
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compatible = "nxp,imx93-adc";
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reg = <0x44530000 0x10000>;
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interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_ADC1_GATE>;
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clock-names = "ipg";
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status = "disabled";
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};
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};
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aips2: bus@42000000 {
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compatible = "fsl,aips-bus", "simple-bus";
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reg = <0x42000000 0x800000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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wakeupmix_gpr: blk-ctrl-wakeupmix@42420000 {
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compatible = "syscon";
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reg = <0x42420000 0x1000>;
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};
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mu2: mailbox@42440000 {
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compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
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reg = <0x42440000 0x10000>;
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interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <2>;
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status = "disabled";
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};
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wdog3: wdog@42490000 {
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compatible = "fsl,imx93-wdt";
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reg = <0x42490000 0x10000>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_WDOG3_GATE>;
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timeout-sec = <40>;
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status = "disabled";
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};
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tpm4: pwm@424f0000 {
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compatible = "fsl,imx7ulp-pwm";
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reg = <0x424f0000 0x1000>;
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clocks = <&clk IMX93_CLK_TPM4_GATE>;
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assigned-clocks = <&clk IMX93_CLK_TPM4>;
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assigned-clock-parents = <&clk IMX93_CLK_24M>;
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assigned-clock-rates = <24000000>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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i3c2: i3c-master@42520000 {
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#address-cells = <3>;
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#size-cells = <0>;
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compatible = "fsl,imx93-i3c-master", "silvaco,i3c-master";
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reg = <0x42520000 0x10000>;
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interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_I3C2_GATE>,
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<&clk IMX93_CLK_I3C2_GATE>,
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<&clk IMX93_CLK_DUMMY>;
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clock-names = "pclk", "fast_clk", "slow_clk";
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status = "disabled";
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};
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lpi2c3: i2c@42530000 {
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compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
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reg = <0x42530000 0x10000>;
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_LPI2C3_GATE>,
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<&clk IMX93_CLK_LPI2C3_GATE>;
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clock-names = "per", "ipg";
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status = "disabled";
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};
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lpi2c4: i2c@42540000 {
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compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
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reg = <0x42540000 0x10000>;
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interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_LPI2C4_GATE>,
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<&clk IMX93_CLK_LPI2C4_GATE>;
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clock-names = "per", "ipg";
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status = "disabled";
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};
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lpspi3: spi@42550000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
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reg = <0x42550000 0x10000>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_LPSPI3_GATE>,
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<&clk IMX93_CLK_LPSPI3_GATE>;
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clock-names = "per", "ipg";
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status = "disabled";
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};
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lpspi4: spi@42560000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
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reg = <0x42560000 0x10000>;
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_LPSPI4_GATE>,
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<&clk IMX93_CLK_LPSPI4_GATE>;
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clock-names = "per", "ipg";
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status = "disabled";
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};
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lpuart3: serial@42570000 {
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compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart",
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"fsl,imx7ulp-lpuart";
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reg = <0x42570000 0x1000>;
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_LPUART3_GATE>;
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clock-names = "ipg";
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status = "disabled";
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};
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lpuart4: serial@42580000 {
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compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart",
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"fsl,imx7ulp-lpuart";
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reg = <0x42580000 0x1000>;
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interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_LPUART4_GATE>;
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clock-names = "ipg";
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status = "disabled";
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};
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lpuart5: serial@42590000 {
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compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart",
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"fsl,imx7ulp-lpuart";
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reg = <0x42590000 0x1000>;
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_LPUART5_GATE>;
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clock-names = "ipg";
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status = "disabled";
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};
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lpuart6: serial@425a0000 {
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compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart",
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"fsl,imx7ulp-lpuart";
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reg = <0x425a0000 0x1000>;
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interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_LPUART6_GATE>;
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clock-names = "ipg";
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status = "disabled";
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};
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flexspi: spi@425e0000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nxp,imx8mm-fspi";
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reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>;
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reg-names = "fspi_base", "fspi_mmap";
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_DUMMY>,
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<&clk IMX93_CLK_DUMMY>;
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clock-names = "fspi", "fspi_en";
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status = "disabled";
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};
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lpuart7: serial@42690000 {
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compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart",
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||||
"fsl,imx7ulp-lpuart";
|
||||
reg = <0x42690000 0x1000>;
|
||||
interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_LPUART7_GATE>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart8: serial@426a0000 {
|
||||
compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart",
|
||||
"fsl,imx7ulp-lpuart";
|
||||
reg = <0x426a0000 0x1000>;
|
||||
interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_LPUART8_GATE>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpi2c5: i2c@426b0000 {
|
||||
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
|
||||
reg = <0x426b0000 0x10000>;
|
||||
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_LPI2C5_GATE>,
|
||||
<&clk IMX93_CLK_LPI2C5_GATE>;
|
||||
clock-names = "per", "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpi2c6: i2c@426c0000 {
|
||||
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
|
||||
reg = <0x426c0000 0x10000>;
|
||||
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_LPI2C6_GATE>,
|
||||
<&clk IMX93_CLK_LPI2C6_GATE>;
|
||||
clock-names = "per", "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
aips3: bus@42800000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x42800000 0x800000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
usdhc1: mmc@42850000 {
|
||||
compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
|
||||
reg = <0x42850000 0x10000>;
|
||||
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_DUMMY>,
|
||||
<&clk IMX93_CLK_DUMMY>,
|
||||
<&clk IMX93_CLK_USDHC1_GATE>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <8>;
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step= <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc2: mmc@42860000 {
|
||||
compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
|
||||
reg = <0x42860000 0x10000>;
|
||||
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_DUMMY>,
|
||||
<&clk IMX93_CLK_DUMMY>,
|
||||
<&clk IMX93_CLK_USDHC2_GATE>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step= <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fec: ethernet@42890000 {
|
||||
compatible = "fsl,imx93-fec", "fsl,imx8mp-fec", "fsl,imx8mq-fec";
|
||||
reg = <0x42890000 0x10000>;
|
||||
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_WAKEUP_AXI>,
|
||||
<&clk IMX93_CLK_WAKEUP_AXI>,
|
||||
<&clk IMX93_CLK_ENET_TIMER1>,
|
||||
<&clk IMX93_CLK_ENET_REF>,
|
||||
<&clk IMX93_CLK_ENET_REF_PHY>;
|
||||
clock-names = "ipg", "ahb", "ptp",
|
||||
"enet_clk_ref", "enet_out";
|
||||
assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>,
|
||||
<&clk IMX93_CLK_ENET_REF>,
|
||||
<&clk IMX93_CLK_ENET_REF_PHY>;
|
||||
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
|
||||
<&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>,
|
||||
<&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
|
||||
assigned-clock-rates = <100000000>, <250000000>, <50000000>;
|
||||
fsl,num-tx-queues = <3>;
|
||||
fsl,num-rx-queues = <3>;
|
||||
fsl,wakeup_irq = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
eqos: ethernet@428a0000 {
|
||||
compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a";
|
||||
reg = <0x428a0000 0x10000>;
|
||||
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "eth_wake_irq", "macirq";
|
||||
clocks = <&clk IMX93_CLK_WAKEUP_AXI>,
|
||||
<&clk IMX93_CLK_WAKEUP_AXI>,
|
||||
<&clk IMX93_CLK_ENET_TIMER2>,
|
||||
<&clk IMX93_CLK_ENET>,
|
||||
<&clk IMX93_CLK_WAKEUP_AXI>;
|
||||
clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
|
||||
assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>,
|
||||
<&clk IMX93_CLK_ENET>;
|
||||
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
|
||||
<&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
|
||||
assigned-clock-rates = <100000000>, <250000000>;
|
||||
intf_mode = <&wakeupmix_gpr 0x28>;
|
||||
clk_csr = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc3: mmc@428b0000 {
|
||||
compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
|
||||
reg = <0x428b0000 0x10000>;
|
||||
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_DUMMY>,
|
||||
<&clk IMX93_CLK_DUMMY>,
|
||||
<&clk IMX93_CLK_USDHC3_GATE>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step= <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
gpio2: gpio@43810000 {
|
||||
compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
|
||||
reg = <0x43810080 0x1000>, <0x43810040 0x40>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 32 32>;
|
||||
};
|
||||
|
||||
gpio3: gpio@43820000 {
|
||||
compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
|
||||
reg = <0x43820080 0x1000>, <0x43820040 0x40>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 64 32>;
|
||||
};
|
||||
|
||||
gpio4: gpio@43830000 {
|
||||
compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
|
||||
reg = <0x43830080 0x1000>, <0x43830040 0x40>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 96 32>;
|
||||
};
|
||||
|
||||
gpio1: gpio@47400000 {
|
||||
compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
|
||||
reg = <0x47400080 0x1000>, <0x47400040 0x40>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 0 32>;
|
||||
};
|
||||
|
||||
ocotp: efuse@47510000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,imx93-ocotp", "syscon";
|
||||
reg = <0x47510000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
s4muap: s4muap@47520000 {
|
||||
compatible = "fsl,imx93-mu-s4";
|
||||
reg = <0x47520000 0x10000>;
|
||||
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "txirq", "rxirq";
|
||||
#mbox-cells = <2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sentnl_mu: sentnl-mu {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,imx-sentnl";
|
||||
mboxes = <&s4muap 0 0 &s4muap 1 0>;
|
||||
mbox-names = "tx", "rx";
|
||||
fsl,sentnl_mu_id = <2>;
|
||||
fsl,sentnl_mu_max_users = <4>;
|
||||
status = "okay";
|
||||
dma-ranges = <0x80000000 0x80000000 0x20000000>;
|
||||
};
|
||||
|
||||
ddr-pmu@4e300e00 {
|
||||
compatible = "fsl,imx93-ddr-pmu";
|
||||
reg = <0x4e300dc0 0x200>; /* _dc0 ~ _eb8 */
|
||||
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
usbphynop1: usbphynop1 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>;
|
||||
clock-names = "main_clk";
|
||||
};
|
||||
|
||||
usbotg1: usb@4c100000 {
|
||||
compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
|
||||
reg = <0x4c100000 0x200>;
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>;
|
||||
clock-names = "usb1_ctrl_root_clk";
|
||||
assigned-clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>;
|
||||
assigned-clock-parents = <&clk IMX93_CLK_HSIO>;
|
||||
fsl,usbphy = <&usbphynop1>;
|
||||
fsl,usbmisc = <&usbmisc1 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbmisc1: usbmisc@4c100200 {
|
||||
compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
|
||||
#index-cells = <1>;
|
||||
reg = <0x4c100200 0x200>;
|
||||
};
|
||||
|
||||
usbphynop2: usbphynop2 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>;
|
||||
clock-names = "main_clk";
|
||||
};
|
||||
|
||||
usbotg2: usb@4c200000 {
|
||||
compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
|
||||
reg = <0x4c200000 0x200>;
|
||||
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>;
|
||||
clock-names = "usb2_ctrl_root_clk";
|
||||
assigned-clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>;
|
||||
assigned-clock-parents = <&clk IMX93_CLK_HSIO>;
|
||||
fsl,usbphy = <&usbphynop2>;
|
||||
fsl,usbmisc = <&usbmisc2 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbmisc2: usbmisc@4c200200 {
|
||||
compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
|
||||
#index-cells = <1>;
|
||||
reg = <0x4c200200 0x200>;
|
||||
};
|
||||
};
|
||||
};
|
||||
203
include/dt-bindings/clock/imx93-clock.h
Normal file
203
include/dt-bindings/clock/imx93-clock.h
Normal file
|
|
@ -0,0 +1,203 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ OR MIT */
|
||||
/*
|
||||
* Copyright 2021 NXP
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_IMX93_CLK_H
|
||||
#define __DT_BINDINGS_CLOCK_IMX93_CLK_H
|
||||
|
||||
#define IMX93_CLK_DUMMY 0
|
||||
#define IMX93_CLK_24M 1
|
||||
#define IMX93_CLK_EXT1 2
|
||||
#define IMX93_CLK_SYS_PLL_PFD0 3
|
||||
#define IMX93_CLK_SYS_PLL_PFD0_DIV2 4
|
||||
#define IMX93_CLK_SYS_PLL_PFD1 5
|
||||
#define IMX93_CLK_SYS_PLL_PFD1_DIV2 6
|
||||
#define IMX93_CLK_SYS_PLL_PFD2 7
|
||||
#define IMX93_CLK_SYS_PLL_PFD2_DIV2 8
|
||||
#define IMX93_CLK_AUDIO_PLL 9
|
||||
#define IMX93_CLK_VIDEO_PLL 10
|
||||
#define IMX93_CLK_A55_PERIPH 11
|
||||
#define IMX93_CLK_A55_MTR_BUS 12
|
||||
#define IMX93_CLK_A55 13
|
||||
#define IMX93_CLK_M33 14
|
||||
#define IMX93_CLK_BUS_WAKEUP 15
|
||||
#define IMX93_CLK_BUS_AON 16
|
||||
#define IMX93_CLK_WAKEUP_AXI 17
|
||||
#define IMX93_CLK_SWO_TRACE 18
|
||||
#define IMX93_CLK_M33_SYSTICK 19
|
||||
#define IMX93_CLK_FLEXIO1 20
|
||||
#define IMX93_CLK_FLEXIO2 21
|
||||
#define IMX93_CLK_LPIT1 22
|
||||
#define IMX93_CLK_LPIT2 23
|
||||
#define IMX93_CLK_LPTMR1 24
|
||||
#define IMX93_CLK_LPTMR2 25
|
||||
#define IMX93_CLK_TPM1 26
|
||||
#define IMX93_CLK_TPM2 27
|
||||
#define IMX93_CLK_TPM3 28
|
||||
#define IMX93_CLK_TPM4 29
|
||||
#define IMX93_CLK_TPM5 30
|
||||
#define IMX93_CLK_TPM6 31
|
||||
#define IMX93_CLK_FLEXSPI1 32
|
||||
#define IMX93_CLK_CAN1 33
|
||||
#define IMX93_CLK_CAN2 34
|
||||
#define IMX93_CLK_LPUART1 35
|
||||
#define IMX93_CLK_LPUART2 36
|
||||
#define IMX93_CLK_LPUART3 37
|
||||
#define IMX93_CLK_LPUART4 38
|
||||
#define IMX93_CLK_LPUART5 39
|
||||
#define IMX93_CLK_LPUART6 40
|
||||
#define IMX93_CLK_LPUART7 41
|
||||
#define IMX93_CLK_LPUART8 42
|
||||
#define IMX93_CLK_LPI2C1 43
|
||||
#define IMX93_CLK_LPI2C2 44
|
||||
#define IMX93_CLK_LPI2C3 45
|
||||
#define IMX93_CLK_LPI2C4 46
|
||||
#define IMX93_CLK_LPI2C5 47
|
||||
#define IMX93_CLK_LPI2C6 48
|
||||
#define IMX93_CLK_LPI2C7 49
|
||||
#define IMX93_CLK_LPI2C8 50
|
||||
#define IMX93_CLK_LPSPI1 51
|
||||
#define IMX93_CLK_LPSPI2 52
|
||||
#define IMX93_CLK_LPSPI3 53
|
||||
#define IMX93_CLK_LPSPI4 54
|
||||
#define IMX93_CLK_LPSPI5 55
|
||||
#define IMX93_CLK_LPSPI6 56
|
||||
#define IMX93_CLK_LPSPI7 57
|
||||
#define IMX93_CLK_LPSPI8 58
|
||||
#define IMX93_CLK_I3C1 59
|
||||
#define IMX93_CLK_I3C2 60
|
||||
#define IMX93_CLK_USDHC1 61
|
||||
#define IMX93_CLK_USDHC2 62
|
||||
#define IMX93_CLK_USDHC3 63
|
||||
#define IMX93_CLK_SAI1 64
|
||||
#define IMX93_CLK_SAI2 65
|
||||
#define IMX93_CLK_SAI3 66
|
||||
#define IMX93_CLK_CCM_CKO1 67
|
||||
#define IMX93_CLK_CCM_CKO2 68
|
||||
#define IMX93_CLK_CCM_CKO3 69
|
||||
#define IMX93_CLK_CCM_CKO4 70
|
||||
#define IMX93_CLK_HSIO 71
|
||||
#define IMX93_CLK_HSIO_USB_TEST_60M 72
|
||||
#define IMX93_CLK_HSIO_ACSCAN_80M 73
|
||||
#define IMX93_CLK_HSIO_ACSCAN_480M 74
|
||||
#define IMX93_CLK_ML_APB 75
|
||||
#define IMX93_CLK_ML 76
|
||||
#define IMX93_CLK_MEDIA_AXI 77
|
||||
#define IMX93_CLK_MEDIA_APB 78
|
||||
#define IMX93_CLK_MEDIA_LDB 79
|
||||
#define IMX93_CLK_MEDIA_DISP_PIX 80
|
||||
#define IMX93_CLK_CAM_PIX 81
|
||||
#define IMX93_CLK_MIPI_TEST_BYTE 82
|
||||
#define IMX93_CLK_MIPI_PHY_CFG 83
|
||||
#define IMX93_CLK_ADC 84
|
||||
#define IMX93_CLK_PDM 85
|
||||
#define IMX93_CLK_TSTMR1 86
|
||||
#define IMX93_CLK_TSTMR2 87
|
||||
#define IMX93_CLK_MQS1 88
|
||||
#define IMX93_CLK_MQS2 89
|
||||
#define IMX93_CLK_AUDIO_XCVR 90
|
||||
#define IMX93_CLK_SPDIF 91
|
||||
#define IMX93_CLK_ENET 92
|
||||
#define IMX93_CLK_ENET_TIMER1 93
|
||||
#define IMX93_CLK_ENET_TIMER2 94
|
||||
#define IMX93_CLK_ENET_REF 95
|
||||
#define IMX93_CLK_ENET_REF_PHY 96
|
||||
#define IMX93_CLK_I3C1_SLOW 97
|
||||
#define IMX93_CLK_I3C2_SLOW 98
|
||||
#define IMX93_CLK_USB_PHY_BURUNIN 99
|
||||
#define IMX93_CLK_PAL_CAME_SCAN 100
|
||||
#define IMX93_CLK_A55_GATE 101
|
||||
#define IMX93_CLK_CM33_GATE 102
|
||||
#define IMX93_CLK_ADC1_GATE 103
|
||||
#define IMX93_CLK_WDOG1_GATE 104
|
||||
#define IMX93_CLK_WDOG2_GATE 105
|
||||
#define IMX93_CLK_WDOG3_GATE 106
|
||||
#define IMX93_CLK_WDOG4_GATE 107
|
||||
#define IMX93_CLK_WDOG5_GATE 108
|
||||
#define IMX93_CLK_SEMA1_GATE 109
|
||||
#define IMX93_CLK_SEMA2_GATE 110
|
||||
#define IMX93_CLK_MU_A_GATE 111
|
||||
#define IMX93_CLK_MU_B_GATE 112
|
||||
#define IMX93_CLK_EDMA1_GATE 113
|
||||
#define IMX93_CLK_EDMA2_GATE 114
|
||||
#define IMX93_CLK_FLEXSPI1_GATE 115
|
||||
#define IMX93_CLK_GPIO1_GATE 116
|
||||
#define IMX93_CLK_GPIO2_GATE 117
|
||||
#define IMX93_CLK_GPIO3_GATE 118
|
||||
#define IMX93_CLK_GPIO4_GATE 119
|
||||
#define IMX93_CLK_FLEXIO1_GATE 120
|
||||
#define IMX93_CLK_FLEXIO2_GATE 121
|
||||
#define IMX93_CLK_LPIT1_GATE 122
|
||||
#define IMX93_CLK_LPIT2_GATE 123
|
||||
#define IMX93_CLK_LPTMR1_GATE 124
|
||||
#define IMX93_CLK_LPTMR2_GATE 125
|
||||
#define IMX93_CLK_TPM1_GATE 126
|
||||
#define IMX93_CLK_TPM2_GATE 127
|
||||
#define IMX93_CLK_TPM3_GATE 128
|
||||
#define IMX93_CLK_TPM4_GATE 129
|
||||
#define IMX93_CLK_TPM5_GATE 130
|
||||
#define IMX93_CLK_TPM6_GATE 131
|
||||
#define IMX93_CLK_CAN1_GATE 132
|
||||
#define IMX93_CLK_CAN2_GATE 133
|
||||
#define IMX93_CLK_LPUART1_GATE 134
|
||||
#define IMX93_CLK_LPUART2_GATE 135
|
||||
#define IMX93_CLK_LPUART3_GATE 136
|
||||
#define IMX93_CLK_LPUART4_GATE 137
|
||||
#define IMX93_CLK_LPUART5_GATE 138
|
||||
#define IMX93_CLK_LPUART6_GATE 139
|
||||
#define IMX93_CLK_LPUART7_GATE 140
|
||||
#define IMX93_CLK_LPUART8_GATE 141
|
||||
#define IMX93_CLK_LPI2C1_GATE 142
|
||||
#define IMX93_CLK_LPI2C2_GATE 143
|
||||
#define IMX93_CLK_LPI2C3_GATE 144
|
||||
#define IMX93_CLK_LPI2C4_GATE 145
|
||||
#define IMX93_CLK_LPI2C5_GATE 146
|
||||
#define IMX93_CLK_LPI2C6_GATE 147
|
||||
#define IMX93_CLK_LPI2C7_GATE 148
|
||||
#define IMX93_CLK_LPI2C8_GATE 149
|
||||
#define IMX93_CLK_LPSPI1_GATE 150
|
||||
#define IMX93_CLK_LPSPI2_GATE 151
|
||||
#define IMX93_CLK_LPSPI3_GATE 152
|
||||
#define IMX93_CLK_LPSPI4_GATE 153
|
||||
#define IMX93_CLK_LPSPI5_GATE 154
|
||||
#define IMX93_CLK_LPSPI6_GATE 155
|
||||
#define IMX93_CLK_LPSPI7_GATE 156
|
||||
#define IMX93_CLK_LPSPI8_GATE 157
|
||||
#define IMX93_CLK_I3C1_GATE 158
|
||||
#define IMX93_CLK_I3C2_GATE 159
|
||||
#define IMX93_CLK_USDHC1_GATE 160
|
||||
#define IMX93_CLK_USDHC2_GATE 161
|
||||
#define IMX93_CLK_USDHC3_GATE 162
|
||||
#define IMX93_CLK_SAI1_GATE 163
|
||||
#define IMX93_CLK_SAI2_GATE 164
|
||||
#define IMX93_CLK_SAI3_GATE 165
|
||||
#define IMX93_CLK_MIPI_CSI_GATE 166
|
||||
#define IMX93_CLK_MIPI_DSI_GATE 167
|
||||
#define IMX93_CLK_LVDS_GATE 168
|
||||
#define IMX93_CLK_LCDIF_GATE 169
|
||||
#define IMX93_CLK_PXP_GATE 170
|
||||
#define IMX93_CLK_ISI_GATE 171
|
||||
#define IMX93_CLK_NIC_MEDIA_GATE 172
|
||||
#define IMX93_CLK_USB_CONTROLLER_GATE 173
|
||||
#define IMX93_CLK_USB_TEST_60M_GATE 174
|
||||
#define IMX93_CLK_HSIO_TROUT_24M_GATE 175
|
||||
#define IMX93_CLK_PDM_GATE 176
|
||||
#define IMX93_CLK_MQS1_GATE 177
|
||||
#define IMX93_CLK_MQS2_GATE 178
|
||||
#define IMX93_CLK_AUD_XCVR_GATE 179
|
||||
#define IMX93_CLK_SPDIF_GATE 180
|
||||
#define IMX93_CLK_HSIO_32K_GATE 181
|
||||
#define IMX93_CLK_ENET1_GATE 182
|
||||
#define IMX93_CLK_ENET_QOS_GATE 183
|
||||
#define IMX93_CLK_SYS_CNT_GATE 184
|
||||
#define IMX93_CLK_TSTMR1_GATE 185
|
||||
#define IMX93_CLK_TSTMR2_GATE 186
|
||||
#define IMX93_CLK_TMC_GATE 187
|
||||
#define IMX93_CLK_PMRO_GATE 188
|
||||
#define IMX93_CLK_32K 189
|
||||
#define IMX93_CLK_SAI1_IPG 190
|
||||
#define IMX93_CLK_SAI2_IPG 191
|
||||
#define IMX93_CLK_SAI3_IPG 192
|
||||
#define IMX93_CLK_END 193
|
||||
#endif
|
||||
12
include/dt-bindings/power/imx93-power.h
Normal file
12
include/dt-bindings/power/imx93-power.h
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright 2021 NXP
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_IMX93_POWER_H__
|
||||
#define __DT_BINDINGS_IMX93_POWER_H__
|
||||
|
||||
#define IMX93_POWER_DOMAIN_MLMIX 0
|
||||
#define IMX93_POWER_DOMAIN_MEDIAMIX 1
|
||||
|
||||
#endif
|
||||
Loading…
Reference in a new issue