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arm: mvebu: Avoid reading MVEBU_REG_PCIE_DEVID register too many times

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Change detection of platform/cpu from runtime to compile time via config
define. This completely eliminates compiling code which is not going to run
on selected platform. Code which parses and prints device / revision id
still reads device id from MVEBU_REG_PCIE_DEVID register, but only once.

Signed-off-by: Pali Rohár <pali@kernel.org>
Acked-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Pali Rohár 2022-07-15 10:13:12 +02:00 • committed by Stefan Roese
parent 569b8b8dd8
commit 3308933d2f
3 changed files with 32 additions and 62 deletions
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67
arch/arm/mach-mvebu/cpu.c
View file

@ -54,33 +54,6 @@ void reset_cpu(void)
;
}
int mvebu_soc_family(void)
{
u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
switch (devid) {
case SOC_MV78230_ID:
case SOC_MV78260_ID:
case SOC_MV78460_ID:
return MVEBU_SOC_AXP;
case SOC_88F6720_ID:
return MVEBU_SOC_A375;
case SOC_88F6810_ID:
case SOC_88F6820_ID:
case SOC_88F6828_ID:
return MVEBU_SOC_A38X;
case SOC_98DX3236_ID:
case SOC_98DX3336_ID:
case SOC_98DX4251_ID:
return MVEBU_SOC_MSYS;
}
return MVEBU_SOC_UNKNOWN;
}
u32 get_boot_device(void)
{
u32 val;
@ -305,7 +278,10 @@ int print_cpuinfo(void)
break;
}
if (mvebu_soc_family() == MVEBU_SOC_AXP) {
switch (devid) {
case SOC_MV78230_ID:
case SOC_MV78260_ID:
case SOC_MV78460_ID:
switch (revid) {
case 1:
puts("A0");
@ -317,9 +293,9 @@ int print_cpuinfo(void)
printf("?? (%x)", revid);
break;
}
}
break;
if (mvebu_soc_family() == MVEBU_SOC_A375) {
case SOC_88F6720_ID:
switch (revid) {
case MV_88F67XX_A0_ID:
puts("A0");
@ -328,9 +304,11 @@ int print_cpuinfo(void)
printf("?? (%x)", revid);
break;
}
}
break;
if (mvebu_soc_family() == MVEBU_SOC_A38X) {
case SOC_88F6810_ID:
case SOC_88F6820_ID:
case SOC_88F6828_ID:
switch (revid) {
case MV_88F68XX_Z1_ID:
puts("Z1");
@ -345,9 +323,11 @@ int print_cpuinfo(void)
printf("?? (%x)", revid);
break;
}
}
break;
if (mvebu_soc_family() == MVEBU_SOC_MSYS) {
case SOC_98DX3236_ID:
case SOC_98DX3336_ID:
case SOC_98DX4251_ID:
switch (revid) {
case 3:
puts("A0");
@ -359,6 +339,11 @@ int print_cpuinfo(void)
printf("?? (%x)", revid);
break;
}
break;
default:
printf("?? (%x)", revid);
break;
}
get_sar_freq(&sar_freq);
@ -463,7 +448,7 @@ int arch_cpu_init(void)
struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
if (mvebu_soc_family() == MVEBU_SOC_A38X) {
if (IS_ENABLED(CONFIG_ARMADA_38X)) {
/*
* To fully release / unlock this area from cache, we need
* to flush all caches and disable the L2 cache.
@ -492,7 +477,7 @@ int arch_cpu_init(void)
*/
mvebu_mbus_probe(NULL, 0);
if (mvebu_soc_family() == MVEBU_SOC_AXP) {
if (IS_ENABLED(CONFIG_ARMADA_XP)) {
/*
* Now the SDRAM access windows can be reconfigured using
* the information in the SDRAM scratch pad registers
@ -506,7 +491,7 @@ int arch_cpu_init(void)
*/
mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
if (mvebu_soc_family() == MVEBU_SOC_AXP) {
if (IS_ENABLED(CONFIG_ARMADA_XP)) {
/* Enable GBE0, GBE1, LCD and NFC PUP */
clrsetbits_le32(ARMADA_XP_PUP_ENABLE, 0,
GE0_PUP_EN | GE1_PUP_EN | LCD_PUP_EN |
@ -530,9 +515,9 @@ u32 mvebu_get_nand_clock(void)
{
u32 reg;
if (mvebu_soc_family() == MVEBU_SOC_A38X)
if (IS_ENABLED(CONFIG_ARMADA_38X))
reg = MVEBU_DFX_DIV_CLK_CTRL(1);
else if (mvebu_soc_family() == MVEBU_SOC_MSYS)
else if (IS_ENABLED(CONFIG_ARMADA_MSYS))
reg = MVEBU_DFX_DIV_CLK_CTRL(8);
else
reg = MVEBU_CORE_DIV_CLK_CTRL(1);
@ -678,7 +663,7 @@ void enable_caches(void)
* ethernet driver (mvpp2). So lets keep the d-cache disabled
* until this is solved.
*/
if (mvebu_soc_family() != MVEBU_SOC_A375) {
if (IS_ENABLED(CONFIG_ARMADA_375)) {
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}
@ -686,7 +671,7 @@ void enable_caches(void)
void v7_outer_cache_enable(void)
{
if (mvebu_soc_family() == MVEBU_SOC_AXP) {
if (IS_ENABLED(CONFIG_ARMADA_XP)) {
struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
u32 u;

18
arch/arm/mach-mvebu/dram.c
View file

@ -220,7 +220,7 @@ static int ecc_enabled(void)
return 0;
}
/* Return the width of the DRAM bus, or 0 for unknown. */
/* Return the width of the DRAM bus. */
static int bus_width(void)
{
int full_width = 0;
@ -228,17 +228,11 @@ static int bus_width(void)
if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_WIDTH_OFFS))
full_width = 1;
switch (mvebu_soc_family()) {
case MVEBU_SOC_AXP:
return full_width ? 64 : 32;
break;
case MVEBU_SOC_A375:
case MVEBU_SOC_A38X:
case MVEBU_SOC_MSYS:
return full_width ? 32 : 16;
default:
return 0;
}
#ifdef CONFIG_ARMADA_XP
return full_width ? 64 : 32;
#else
return full_width ? 32 : 16;
#endif
}
static int cycle_mode(void)

9
arch/arm/mach-mvebu/include/mach/cpu.h
View file

@ -61,14 +61,6 @@ enum cpu_attrib {
CPU_ATTR_DEV_CS3 = 0x37,
};
enum {
MVEBU_SOC_AXP,
MVEBU_SOC_A375,
MVEBU_SOC_A38X,
MVEBU_SOC_MSYS,
MVEBU_SOC_UNKNOWN,
};
#define MVEBU_SDRAM_SIZE_MAX 0xc0000000
/*
@ -140,7 +132,6 @@ unsigned int mvebu_sdram_bar(enum memory_bank bank);
unsigned int mvebu_sdram_bs(enum memory_bank bank);
void mvebu_sdram_size_adjust(enum memory_bank bank);
int mvebu_mbus_probe(struct mbus_win windows[], int count);
int mvebu_soc_family(void);
u32 mvebu_get_nand_clock(void);
void __noreturn return_to_bootrom(void);