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board: mediatek: add MT7981 reference boards
This patch adds general board files based on MT7981 SoCs. MT7981 uses one mmc controller for booting from both SD and eMMC, and the pins of mmc controller are also shared with spi controller. So three configs are need for these boot types: 1. mt7981_rfb_defconfig - SPI-NOR and SPI-NAND 2. mt7981_emmc_rfb_defconfig - eMMC only 3. mt7981_sd_rfb_defconfig - SD only Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This commit is contained in:
Weijie Gao
Tom Rini
parent
389ba6986b
commit
e053ccf6ef
11 changed files with 699 additions and 0 deletions
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@ -1235,6 +1235,9 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
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mt7622-bananapi-bpi-r64.dtb \
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mt7623n-bananapi-bpi-r2.dtb \
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mt7629-rfb.dtb \
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mt7981-rfb.dtb \
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mt7981-emmc-rfb.dtb \
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mt7981-sd-rfb.dtb \
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mt7986a-rfb.dtb \
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mt7986b-rfb.dtb \
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mt7986a-sd-rfb.dtb \
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139
arch/arm/dts/mt7981-emmc-rfb.dts
Normal file
139
arch/arm/dts/mt7981-emmc-rfb.dts
Normal file
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@ -0,0 +1,139 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Sam Shih <sam.shih@mediatek.com>
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*/
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/dts-v1/;
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#include "mt7981.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "mt7981-rfb";
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compatible = "mediatek,mt7981", "mediatek,mt7981-rfb";
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chosen {
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stdout-path = &uart0;
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tick-timer = &timer0;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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&uart0 {
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_pins>;
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status = "disabled";
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};
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ð {
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status = "okay";
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mediatek,gmac-id = <0>;
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phy-mode = "sgmii";
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mediatek,switch = "mt7531";
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reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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&pinctrl {
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spic_pins: spi1-pins-func-1 {
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mux {
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function = "spi";
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groups = "spi1_1";
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};
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};
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uart1_pins: spi1-pins-func-3 {
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mux {
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function = "uart";
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groups = "uart1_2";
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};
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};
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/* pin15 as pwm0 */
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one_pwm_pins: one-pwm-pins {
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mux {
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function = "pwm";
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groups = "pwm0_1";
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};
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};
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/* pin15 as pwm0 and pin14 as pwm1 */
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two_pwm_pins: two-pwm-pins {
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mux {
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function = "pwm";
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groups = "pwm0_1", "pwm1_0";
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};
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};
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/* pin15 as pwm0, pin14 as pwm1, pin7 as pwm2 */
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three_pwm_pins: three-pwm-pins {
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mux {
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function = "pwm";
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groups = "pwm0_1", "pwm1_0", "pwm2";
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};
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};
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mmc0_pins_default: mmc0default {
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mux {
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function = "flash";
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groups = "emmc_45";
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};
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conf-cmd-dat {
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pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
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"SPI0_CS", "SPI0_HOLD", "SPI0_WP",
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"SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
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input-enable;
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drive-strength = <MTK_DRIVE_4mA>;
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bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
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};
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conf-clk {
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pins = "SPI1_CS";
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drive-strength = <MTK_DRIVE_6mA>;
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bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
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};
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conf-rst {
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pins = "PWM0";
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drive-strength = <MTK_DRIVE_4mA>;
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bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
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};
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};
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};
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&pwm {
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pinctrl-names = "default";
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pinctrl-0 = <&two_pwm_pins>;
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status = "okay";
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};
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&watchdog {
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status = "disabled";
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};
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&mmc0 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins_default>;
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bus-width = <8>;
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max-frequency = <52000000>;
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cap-mmc-highspeed;
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cap-mmc-hw-reset;
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vmmc-supply = <®_3p3v>;
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non-removable;
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status = "okay";
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};
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173
arch/arm/dts/mt7981-rfb.dts
Normal file
173
arch/arm/dts/mt7981-rfb.dts
Normal file
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@ -0,0 +1,173 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Sam Shih <sam.shih@mediatek.com>
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*/
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/dts-v1/;
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#include "mt7981.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "mt7981-rfb";
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compatible = "mediatek,mt7981", "mediatek,mt7981-rfb";
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chosen {
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stdout-path = &uart0;
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tick-timer = &timer0;
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};
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};
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&uart0 {
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_pins>;
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status = "disabled";
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};
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ð {
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status = "okay";
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mediatek,gmac-id = <0>;
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phy-mode = "sgmii";
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mediatek,switch = "mt7531";
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reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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&pinctrl {
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spi_flash_pins: spi0-pins-func-1 {
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mux {
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function = "flash";
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groups = "spi0", "spi0_wp_hold";
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};
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conf-pu {
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pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
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drive-strength = <MTK_DRIVE_8mA>;
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bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
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};
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conf-pd {
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pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
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drive-strength = <MTK_DRIVE_8mA>;
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bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
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};
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};
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spi2_flash_pins: spi2-spi2-pins {
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mux {
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function = "spi";
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groups = "spi2", "spi2_wp_hold";
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};
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conf-pu {
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pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
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drive-strength = <MTK_DRIVE_8mA>;
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bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
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};
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conf-pd {
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pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
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drive-strength = <MTK_DRIVE_8mA>;
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bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
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};
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};
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spic_pins: spi1-pins-func-1 {
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mux {
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function = "spi";
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groups = "spi1_1";
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};
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};
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uart1_pins: spi1-pins-func-3 {
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mux {
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function = "uart";
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groups = "uart1_2";
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};
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};
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/* pin15 as pwm0 */
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one_pwm_pins: one-pwm-pins {
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mux {
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function = "pwm";
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groups = "pwm0_1";
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};
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};
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/* pin15 as pwm0 and pin14 as pwm1 */
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two_pwm_pins: two-pwm-pins {
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mux {
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function = "pwm";
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groups = "pwm0_1", "pwm1_0";
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};
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};
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/* pin15 as pwm0, pin14 as pwm1, pin7 as pwm2 */
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three_pwm_pins: three-pwm-pins {
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mux {
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function = "pwm";
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groups = "pwm0_1", "pwm1_0", "pwm2";
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};
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};
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};
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&spi0 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi_flash_pins>;
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status = "okay";
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must_tx;
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enhance_timing;
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dma_ext;
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ipm_design;
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support_quad;
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tick_dly = <2>;
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sample_sel = <0>;
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spi_nand@0 {
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compatible = "spi-nand";
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reg = <0>;
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spi-max-frequency = <52000000>;
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};
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};
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&spi2 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi2_flash_pins>;
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status = "okay";
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must_tx;
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enhance_timing;
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dma_ext;
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ipm_design;
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support_quad;
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tick_dly = <2>;
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sample_sel = <0>;
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spi_nor@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <52000000>;
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};
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};
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&pwm {
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pinctrl-names = "default";
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pinctrl-0 = <&two_pwm_pins>;
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status = "okay";
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};
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&watchdog {
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status = "disabled";
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};
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139
arch/arm/dts/mt7981-sd-rfb.dts
Normal file
139
arch/arm/dts/mt7981-sd-rfb.dts
Normal file
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@ -0,0 +1,139 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Sam Shih <sam.shih@mediatek.com>
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*/
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/dts-v1/;
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#include "mt7981.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "mt7981-rfb";
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compatible = "mediatek,mt7981", "mediatek,mt7981-sd-rfb";
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chosen {
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stdout-path = &uart0;
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tick-timer = &timer0;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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&uart0 {
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_pins>;
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status = "disabled";
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};
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ð {
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status = "okay";
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mediatek,gmac-id = <0>;
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phy-mode = "sgmii";
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mediatek,switch = "mt7531";
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reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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&pinctrl {
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spic_pins: spi1-pins-func-1 {
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mux {
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function = "spi";
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groups = "spi1_1";
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};
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};
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uart1_pins: spi1-pins-func-3 {
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mux {
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function = "uart";
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groups = "uart1_2";
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};
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};
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/* pin15 as pwm0 */
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one_pwm_pins: one-pwm-pins {
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mux {
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function = "pwm";
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groups = "pwm0_1";
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};
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};
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/* pin15 as pwm0 and pin14 as pwm1 */
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two_pwm_pins: two-pwm-pins {
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mux {
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function = "pwm";
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groups = "pwm0_1", "pwm1_0";
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};
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};
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/* pin15 as pwm0, pin14 as pwm1, pin7 as pwm2 */
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three_pwm_pins: three-pwm-pins {
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mux {
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function = "pwm";
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groups = "pwm0_1", "pwm1_0", "pwm2";
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};
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};
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mmc0_pins_default: mmc0default {
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mux {
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function = "flash";
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groups = "emmc_45";
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};
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conf-cmd-dat {
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pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
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"SPI0_CS", "SPI0_HOLD", "SPI0_WP",
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"SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
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input-enable;
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drive-strength = <MTK_DRIVE_4mA>;
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bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
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};
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conf-clk {
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pins = "SPI1_CS";
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drive-strength = <MTK_DRIVE_6mA>;
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bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
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};
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conf-rst {
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pins = "PWM0";
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drive-strength = <MTK_DRIVE_4mA>;
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bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
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};
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};
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};
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&pwm {
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pinctrl-names = "default";
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pinctrl-0 = <&two_pwm_pins>;
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status = "okay";
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};
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&watchdog {
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status = "disabled";
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};
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&mmc0 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins_default>;
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bus-width = <4>;
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max-frequency = <52000000>;
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cap-sd-highspeed;
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r_smpl = <0>;
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <®_3p3v>;
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status = "okay";
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};
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10
board/mediatek/mt7981/MAINTAINERS
Normal file
10
board/mediatek/mt7981/MAINTAINERS
Normal file
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MT7981
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M: Sam Shih <sam.shih@mediatek.com>
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S: Maintained
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F: board/mediatek/mt7981
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F: include/configs/mt7981.h
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F: configs/mt7981_emmc_rfb_defconfig
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F: configs/mt7981_rfb_defconfig
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F: configs/mt7981_sd_rfb_defconfig
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F: configs/mt7981_spim_nand_rfb_defconfig
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F: configs/mt7981_spim_nor_rfb_defconfig
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3
board/mediatek/mt7981/Makefile
Normal file
3
board/mediatek/mt7981/Makefile
Normal file
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# SPDX-License-Identifier: GPL-2.0
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obj-y += mt7981_rfb.o
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10
board/mediatek/mt7981/mt7981_rfb.c
Normal file
10
board/mediatek/mt7981/mt7981_rfb.c
Normal file
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@ -0,0 +1,10 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2022 MediaTek Inc.
|
||||
* Author: Sam Shih <sam.shih@mediatek.com>
|
||||
*/
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
64
configs/mt7981_emmc_rfb_defconfig
Normal file
64
configs/mt7981_emmc_rfb_defconfig
Normal file
|
|
@ -0,0 +1,64 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_POSITION_INDEPENDENT=y
|
||||
CONFIG_ARCH_MEDIATEK=y
|
||||
CONFIG_SYS_TEXT_BASE=0x41e00000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x4000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_ENV_SIZE=0x80000
|
||||
CONFIG_ENV_OFFSET=0x300000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="mt7981-emmc-rfb"
|
||||
CONFIG_TARGET_MT7981=y
|
||||
CONFIG_DEBUG_UART_BASE=0x11002000
|
||||
CONFIG_DEBUG_UART_CLOCK=40000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x46000000
|
||||
CONFIG_DEBUG_UART=y
|
||||
# CONFIG_AUTOBOOT is not set
|
||||
CONFIG_DEFAULT_FDT_FILE="mt7981-emmc-rfb"
|
||||
CONFIG_LOGLEVEL=7
|
||||
CONFIG_LOG=y
|
||||
CONFIG_SYS_PROMPT="MT7981> "
|
||||
CONFIG_SYS_CBSIZE=512
|
||||
CONFIG_SYS_PBSIZE=1049
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
# CONFIG_BOOTM_PLAN9 is not set
|
||||
# CONFIG_BOOTM_RTEMS is not set
|
||||
# CONFIG_BOOTM_VXWORKS is not set
|
||||
# CONFIG_CMD_ELF is not set
|
||||
# CONFIG_CMD_UNLZ4 is not set
|
||||
# CONFIG_CMD_UNZIP is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_GPT_RENAME=y
|
||||
CONFIG_CMD_LSBLK=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PART=y
|
||||
CONFIG_CMD_READ=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_SMC=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_PARTITION_TYPE_GUID=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_MMC_HS200_SUPPORT=y
|
||||
CONFIG_MMC_MTK=y
|
||||
CONFIG_PHY_FIXED=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_MEDIATEK_ETH=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCONF=y
|
||||
CONFIG_PINCTRL_MT7981=y
|
||||
CONFIG_POWER_DOMAIN=y
|
||||
CONFIG_MTK_POWER_DOMAIN=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_MTK_SERIAL=y
|
||||
CONFIG_FAT_WRITE=y
|
||||
CONFIG_HEXDUMP=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
69
configs/mt7981_rfb_defconfig
Normal file
69
configs/mt7981_rfb_defconfig
Normal file
|
|
@ -0,0 +1,69 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_POSITION_INDEPENDENT=y
|
||||
CONFIG_ARCH_MEDIATEK=y
|
||||
CONFIG_SYS_TEXT_BASE=0x41e00000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x4000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_DEFAULT_DEVICE_TREE="mt7981-rfb"
|
||||
CONFIG_TARGET_MT7981=y
|
||||
CONFIG_DEBUG_UART_BASE=0x11002000
|
||||
CONFIG_DEBUG_UART_CLOCK=40000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x46000000
|
||||
CONFIG_DEBUG_UART=y
|
||||
# CONFIG_AUTOBOOT is not set
|
||||
CONFIG_DEFAULT_FDT_FILE="mt7981-rfb"
|
||||
CONFIG_LOGLEVEL=7
|
||||
CONFIG_LOG=y
|
||||
CONFIG_SYS_PROMPT="MT7981> "
|
||||
CONFIG_SYS_CBSIZE=512
|
||||
CONFIG_SYS_PBSIZE=1049
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
# CONFIG_BOOTM_PLAN9 is not set
|
||||
# CONFIG_BOOTM_RTEMS is not set
|
||||
# CONFIG_BOOTM_VXWORKS is not set
|
||||
# CONFIG_CMD_ELF is not set
|
||||
# CONFIG_CMD_UNLZ4 is not set
|
||||
# CONFIG_CMD_UNZIP is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_MTD=y
|
||||
CONFIG_CMD_SF_TEST=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_SMC=y
|
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_BLK=y
|
||||
CONFIG_HAVE_BLOCK_DEVICE=y
|
||||
CONFIG_CLK=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_DM_MTD=y
|
||||
CONFIG_MTD_SPI_NAND=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_SPI_FLASH_XMC=y
|
||||
CONFIG_SPI_FLASH_XTX=y
|
||||
CONFIG_SPI_FLASH_MTD=y
|
||||
CONFIG_PHY_FIXED=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_MEDIATEK_ETH=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCONF=y
|
||||
CONFIG_PINCTRL_MT7981=y
|
||||
CONFIG_POWER_DOMAIN=y
|
||||
CONFIG_MTK_POWER_DOMAIN=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_MTK_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_MTK_SPIM=y
|
||||
CONFIG_HEXDUMP=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
64
configs/mt7981_sd_rfb_defconfig
Normal file
64
configs/mt7981_sd_rfb_defconfig
Normal file
|
|
@ -0,0 +1,64 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_POSITION_INDEPENDENT=y
|
||||
CONFIG_ARCH_MEDIATEK=y
|
||||
CONFIG_SYS_TEXT_BASE=0x41e00000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x4000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_ENV_SIZE=0x80000
|
||||
CONFIG_ENV_OFFSET=0x300000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="mt7981-sd-rfb"
|
||||
CONFIG_TARGET_MT7981=y
|
||||
CONFIG_DEBUG_UART_BASE=0x11002000
|
||||
CONFIG_DEBUG_UART_CLOCK=40000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x46000000
|
||||
CONFIG_DEBUG_UART=y
|
||||
# CONFIG_AUTOBOOT is not set
|
||||
CONFIG_DEFAULT_FDT_FILE="mt7981-sd-rfb"
|
||||
CONFIG_LOGLEVEL=7
|
||||
CONFIG_LOG=y
|
||||
CONFIG_SYS_PROMPT="MT7981> "
|
||||
CONFIG_SYS_CBSIZE=512
|
||||
CONFIG_SYS_PBSIZE=1049
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
# CONFIG_BOOTM_PLAN9 is not set
|
||||
# CONFIG_BOOTM_RTEMS is not set
|
||||
# CONFIG_BOOTM_VXWORKS is not set
|
||||
# CONFIG_CMD_ELF is not set
|
||||
# CONFIG_CMD_UNLZ4 is not set
|
||||
# CONFIG_CMD_UNZIP is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_GPT_RENAME=y
|
||||
CONFIG_CMD_LSBLK=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PART=y
|
||||
CONFIG_CMD_READ=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_SMC=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_PARTITION_TYPE_GUID=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_MMC_HS200_SUPPORT=y
|
||||
CONFIG_MMC_MTK=y
|
||||
CONFIG_PHY_FIXED=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_MEDIATEK_ETH=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCONF=y
|
||||
CONFIG_PINCTRL_MT7981=y
|
||||
CONFIG_POWER_DOMAIN=y
|
||||
CONFIG_MTK_POWER_DOMAIN=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_MTK_SERIAL=y
|
||||
CONFIG_FAT_WRITE=y
|
||||
CONFIG_HEXDUMP=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
25
include/configs/mt7981.h
Normal file
25
include/configs/mt7981.h
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Configuration for MediaTek MT7981 SoC
|
||||
*
|
||||
* Copyright (C) 2022 MediaTek Inc.
|
||||
* Author: Sam Shih <sam.shih@mediatek.com>
|
||||
*/
|
||||
|
||||
#ifndef __MT7981_H
|
||||
#define __MT7981_H
|
||||
|
||||
#include <linux/sizes.h>
|
||||
|
||||
#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M
|
||||
|
||||
/* Uboot definition */
|
||||
#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
|
||||
|
||||
/* SPL -> Uboot */
|
||||
#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
|
||||
|
||||
/* DRAM */
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x40000000
|
||||
|
||||
#endif
|
||||
Loading…
Reference in a new issue