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arm: mach-k3: Introduce the basic files to support AM62
The AM62 SoC family is the follow on AM335x built on K3 Multicore SoC architecture platform, providing ultra-low-power modes, dual display, multi-sensor edge compute, security and other BOM-saving integration. The AM62 SoC targets broad market to enable applications such as Industrial HMI, PLC/CNC/Robot control, Medical Equipment, Building Automation, Appliances and more. Some highlights of this SoC are: * Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. Pin-to-pin compatible options for single and quad core are available. * Cortex-M4F for general-purpose or safety usage. * Dual display support, providing 24-bit RBG parallel interface and OLDI/LVDS-4 Lane x2, up to 200MHz pixel clock support for 2K display resolution. * Selectable GPUsupport, up to 8GFLOPS, providing better user experience in 3D graphic display case and Android. * PRU(Programmable Realtime Unit) support for customized programmable interfaces/IOs. * Integrated Giga-bit Ethernet switch supporting up to a total of two external ports (TSN capable). * 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio, 1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. * Dedicated Centralized System Controller for Security, Power, and Resource Management. * Multiple low power modes support, ex: Deep sleep,Standby, MCU-only, enabling battery powered system design. AM625 is the first device of the family. Add DT bindings for the same. More details can be found in the Technical Reference Manual: https://www.ti.com/lit/pdf/spruiv7 Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Gowtham Tammana <g-tammana@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Suman Anna
Tom Rini
parent
4298ee7e40
commit
d98e860051
9 changed files with 415 additions and 3 deletions
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@ -16,6 +16,9 @@ config SOC_K3_J721S2
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config SOC_K3_AM642
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bool "TI's K3 based AM642 SoC Family Support"
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config SOC_K3_AM625
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bool "TI's K3 based AM625 SoC Family Support"
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endchoice
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config SYS_SOC
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@ -26,6 +29,7 @@ config SYS_K3_NON_SECURE_MSRAM_SIZE
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default 0x80000 if SOC_K3_AM6
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default 0x100000 if SOC_K3_J721E || SOC_K3_J721S2
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default 0x1c0000 if SOC_K3_AM642
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default 0x3c000 if SOC_K3_AM625
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help
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Describes the total size of the MCU or OCMC MSRAM present on
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the SoC in use. This doesn't specify the total size of SPL as
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@ -37,6 +41,7 @@ config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
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default 0x58000 if SOC_K3_AM6
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default 0xc0000 if SOC_K3_J721E || SOC_K3_J721S2
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default 0x180000 if SOC_K3_AM642
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default 0x38000 if SOC_K3_AM625
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help
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Describes the maximum size of the image that ROM can download
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from any boot media.
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@ -61,6 +66,7 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX
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default 0x41cffbfc if SOC_K3_J721E
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default 0x41cfdbfc if SOC_K3_J721S2
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default 0x701bebfc if SOC_K3_AM642
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default 0x43c3f290 if SOC_K3_AM625
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help
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Address at which ROM stores the value which determines if SPL
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is booted up by primary boot media or secondary boot media.
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@ -129,6 +135,7 @@ config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_PART
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config K3_SYSFW_IMAGE_SIZE_MAX
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int "Amount of memory dynamically allocated for loading SYSFW blob"
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depends on K3_LOAD_SYSFW
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default 163840 if SOC_K3_AM625
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default 278000
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help
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Amount of memory (in bytes) reserved through dynamic allocation at
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@ -160,7 +167,7 @@ config K3_ATF_LOAD_ADDR
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config K3_DM_FW
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bool "Separate DM firmware image"
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depends on SPL && CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN
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depends on SPL && CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_AM625) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN
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default y
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help
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Enabling this will indicate that the system has separate DM
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@ -7,6 +7,7 @@ obj-$(CONFIG_SOC_K3_AM6) += am6_init.o
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obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o j721e/ j7200/
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obj-$(CONFIG_SOC_K3_J721S2) += j721s2_init.o j721s2/
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obj-$(CONFIG_SOC_K3_AM642) += am642_init.o
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obj-$(CONFIG_SOC_K3_AM625) += am625_init.o am62x/
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obj-$(CONFIG_ARM64) += arm64-mmu.o
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obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
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obj-$(CONFIG_TI_SECURE_DEVICE) += security.o
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271
arch/arm/mach-k3/am625_init.c
Normal file
271
arch/arm/mach-k3/am625_init.c
Normal file
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@ -0,0 +1,271 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* AM625: SoC specific initialization
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*
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* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
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* Suman Anna <s-anna@ti.com>
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*/
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sysfw-loader.h>
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#include "common.h"
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#include <dm.h>
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#include <dm/uclass-internal.h>
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#include <dm/pinctrl.h>
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#if defined(CONFIG_SPL_BUILD)
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/*
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* This uninitialized global variable would normal end up in the .bss section,
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* but the .bss is cleared between writing and reading this variable, so move
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* it to the .data section.
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*/
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u32 bootindex __section(".data");
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static struct rom_extended_boot_data bootdata __section(".data");
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static void store_boot_info_from_rom(void)
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{
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bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
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memcpy(&bootdata, (uintptr_t *)ROM_ENTENDED_BOOT_DATA_INFO,
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sizeof(struct rom_extended_boot_data));
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}
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static void ctrl_mmr_unlock(void)
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{
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/* Unlock all WKUP_CTRL_MMR0 module registers */
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 5);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
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/* Unlock all CTRL_MMR0 module registers */
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mmr_unlock(CTRL_MMR0_BASE, 0);
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mmr_unlock(CTRL_MMR0_BASE, 1);
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mmr_unlock(CTRL_MMR0_BASE, 2);
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mmr_unlock(CTRL_MMR0_BASE, 4);
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mmr_unlock(CTRL_MMR0_BASE, 6);
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/* Unlock all MCU_CTRL_MMR0 module registers */
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mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
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mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
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mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
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mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
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mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
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mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
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/* Unlock PADCFG_CTRL_MMR padconf registers */
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mmr_unlock(PADCFG_MMR0_BASE, 1);
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mmr_unlock(PADCFG_MMR1_BASE, 1);
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}
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void board_init_f(ulong dummy)
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{
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struct udevice *dev;
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int ret;
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#if defined(CONFIG_CPU_V7R)
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setup_k3_mpu_regions();
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#endif
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/*
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* Cannot delay this further as there is a chance that
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* K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
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*/
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store_boot_info_from_rom();
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ctrl_mmr_unlock();
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/* Init DM early */
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spl_early_init();
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/*
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* Process pinctrl for the serial0 and serial3, aka WKUP_UART0 and
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* MAIN_UART1 modules and continue regardless of the result of pinctrl.
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* Do this without probing the device, but instead by searching the
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* device that would request the given sequence number if probed. The
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* UARTs will be used by the DM firmware and TIFS firmware images
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* respectively and the firmware depend on SPL to initialize the pin
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* settings.
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*/
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ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev);
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if (!ret)
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pinctrl_select_state(dev, "default");
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ret = uclass_find_device_by_seq(UCLASS_SERIAL, 3, &dev);
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if (!ret)
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pinctrl_select_state(dev, "default");
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preloader_console_init();
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#ifdef CONFIG_K3_EARLY_CONS
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/*
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* Allow establishing an early console as required for example when
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* doing a UART-based boot. Note that this console may not "survive"
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* through a SYSFW PM-init step and will need a re-init in some way
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* due to changing module clock frequencies.
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*/
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early_console_init();
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#endif
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#if defined(CONFIG_K3_LOAD_SYSFW)
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/*
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* Configure and start up system controller firmware. Provide
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* the U-Boot console init function to the SYSFW post-PM configuration
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* callback hook, effectively switching on (or over) the console
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* output.
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*/
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ret = is_rom_loaded_sysfw(&bootdata);
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if (!ret)
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panic("ROM has not loaded TIFS firmware\n");
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k3_sysfw_loader(true, NULL, NULL);
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#endif
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/*
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* Force probe of clk_k3 driver here to ensure basic default clock
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* configuration is always done.
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*/
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if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
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ret = uclass_get_device_by_driver(UCLASS_CLK,
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DM_DRIVER_GET(ti_clk),
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&dev);
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if (ret)
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printf("Failed to initialize clk-k3!\n");
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}
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/* Output System Firmware version info */
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k3_sysfw_print_ver();
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#if defined(CONFIG_K3_AM64_DDRSS)
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ret = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (ret)
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panic("DRAM init failed: %d\n", ret);
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#endif
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}
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u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
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{
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u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
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u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
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MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
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switch (boot_device) {
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case BOOT_DEVICE_MMC1:
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if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK) >>
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MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_SHIFT)
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return MMCSD_MODE_EMMCBOOT;
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return MMCSD_MODE_FS;
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case BOOT_DEVICE_MMC2:
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return MMCSD_MODE_FS;
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default:
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return MMCSD_MODE_RAW;
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}
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}
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static u32 __get_backup_bootmedia(u32 devstat)
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{
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u32 bkup_bootmode = (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >>
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MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT;
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u32 bkup_bootmode_cfg =
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(devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >>
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MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT;
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switch (bkup_bootmode) {
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case BACKUP_BOOT_DEVICE_UART:
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return BOOT_DEVICE_UART;
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case BACKUP_BOOT_DEVICE_USB:
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return BOOT_DEVICE_USB;
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case BACKUP_BOOT_DEVICE_ETHERNET:
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return BOOT_DEVICE_ETHERNET;
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case BACKUP_BOOT_DEVICE_MMC:
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if (bkup_bootmode_cfg)
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return BOOT_DEVICE_MMC2;
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return BOOT_DEVICE_MMC1;
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case BACKUP_BOOT_DEVICE_SPI:
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return BOOT_DEVICE_SPI;
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case BACKUP_BOOT_DEVICE_I2C:
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return BOOT_DEVICE_I2C;
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case BACKUP_BOOT_DEVICE_DFU:
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if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK)
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return BOOT_DEVICE_USB;
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return BOOT_DEVICE_DFU;
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};
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return BOOT_DEVICE_RAM;
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}
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static u32 __get_primary_bootmedia(u32 devstat)
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{
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u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
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MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
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u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
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MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
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switch (bootmode) {
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case BOOT_DEVICE_OSPI:
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fallthrough;
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case BOOT_DEVICE_QSPI:
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fallthrough;
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case BOOT_DEVICE_XSPI:
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fallthrough;
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case BOOT_DEVICE_SPI:
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return BOOT_DEVICE_SPI;
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case BOOT_DEVICE_ETHERNET_RGMII:
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fallthrough;
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case BOOT_DEVICE_ETHERNET_RMII:
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return BOOT_DEVICE_ETHERNET;
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case BOOT_DEVICE_EMMC:
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return BOOT_DEVICE_MMC1;
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case BOOT_DEVICE_MMC:
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if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >>
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MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT)
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return BOOT_DEVICE_MMC2;
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return BOOT_DEVICE_MMC1;
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case BOOT_DEVICE_DFU:
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if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >>
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MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT)
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return BOOT_DEVICE_USB;
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return BOOT_DEVICE_DFU;
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case BOOT_DEVICE_NOBOOT:
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return BOOT_DEVICE_RAM;
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}
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return bootmode;
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}
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u32 spl_boot_device(void)
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{
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u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
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u32 bootmedia;
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if (bootindex == K3_PRIMARY_BOOTMODE)
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bootmedia = __get_primary_bootmedia(devstat);
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else
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bootmedia = __get_backup_bootmedia(devstat);
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debug("am625_init: %s: devstat = 0x%x bootmedia = 0x%x bootindex = %d\n",
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__func__, devstat, bootmedia, bootindex);
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return bootmedia;
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}
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#endif /* CONFIG_SPL_BUILD */
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@ -222,7 +222,7 @@ struct mm_region *mem_map = j721s2_mem_map;
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#endif /* CONFIG_SOC_K3_J721S2 */
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#ifdef CONFIG_SOC_K3_AM642
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#if (CONFIG_IS_ENABLED(SOC_K3_AM642) || CONFIG_IS_ENABLED(SOC_K3_AM625))
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/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
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#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3)
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@ -261,4 +261,4 @@ struct mm_region am64_mem_map[NR_MMU_REGIONS] = {
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};
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struct mm_region *mem_map = am64_mem_map;
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#endif /* CONFIG_SOC_K3_AM642 */
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#endif /* CONFIG_SOC_K3_AM642 || CONFIG_SOC_K3_AM625 */
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75
arch/arm/mach-k3/include/mach/am62_hardware.h
Normal file
75
arch/arm/mach-k3/include/mach/am62_hardware.h
Normal file
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@ -0,0 +1,75 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* K3: AM62 SoC definitions, structures etc.
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*
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* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
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* Suman Anna <s-anna@ti.com>
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*/
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#ifndef __ASM_ARCH_AM62_HARDWARE_H
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#define __ASM_ARCH_AM62_HARDWARE_H
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#include <config.h>
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#ifndef __ASSEMBLY__
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#include <linux/bitops.h>
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#endif
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#define PADCFG_MMR0_BASE 0x04080000
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#define PADCFG_MMR1_BASE 0x000f0000
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#define CTRL_MMR0_BASE 0x00100000
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#define MCU_CTRL_MMR0_BASE 0x04500000
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#define WKUP_CTRL_MMR0_BASE 0x43000000
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#define CTRLMMR_MAIN_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30)
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#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(6, 3)
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#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3
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#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK GENMASK(9, 7)
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#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT 7
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#define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK GENMASK(12, 10)
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#define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT 10
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#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK BIT(13)
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#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT 13
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/* Primary Bootmode MMC Config macros */
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#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK 0x4
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#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT 2
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#define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK 0x1
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#define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_SHIFT 0
|
||||
|
||||
/* Primary Bootmode USB Config macros */
|
||||
#define MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT 1
|
||||
#define MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK 0x02
|
||||
|
||||
/* Backup Bootmode USB Config macros */
|
||||
#define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK 0x01
|
||||
|
||||
/*
|
||||
* The CTRL_MMR0 memory space is divided into several equally-spaced
|
||||
* partitions, so defining the partition size allows us to determine
|
||||
* register addresses common to those partitions.
|
||||
*/
|
||||
#define CTRL_MMR0_PARTITION_SIZE 0x4000
|
||||
|
||||
/*
|
||||
* CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTRL_MMR0 lock/kick-mechanism
|
||||
* shared register definitions. The same registers are also used for
|
||||
* PADCFG_MMR lock/kick-mechanism.
|
||||
*/
|
||||
#define CTRLMMR_LOCK_KICK0 0x1008
|
||||
#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490
|
||||
#define CTRLMMR_LOCK_KICK1 0x100c
|
||||
#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
|
||||
|
||||
#define MCU_CTRL_LFXOSC_CTRL (MCU_CTRL_MMR0_BASE + 0x8038)
|
||||
#define MCU_CTRL_LFXOSC_TRIM (MCU_CTRL_MMR0_BASE + 0x803c)
|
||||
#define MCU_CTRL_LFXOSC_32K_DISABLE_VAL BIT(7)
|
||||
|
||||
#define MCU_CTRL_DEVICE_CLKOUT_32K_CTRL (MCU_CTRL_MMR0_BASE + 0x8058)
|
||||
#define MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL (0x3)
|
||||
|
||||
#define ROM_ENTENDED_BOOT_DATA_INFO 0x43c3f1e0
|
||||
|
||||
/* Use Last 2K as Scratch pad */
|
||||
#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x70000000
|
||||
|
||||
#endif /* __ASM_ARCH_AM62_HARDWARE_H */
|
||||
48
arch/arm/mach-k3/include/mach/am62_spl.h
Normal file
48
arch/arm/mach-k3/include/mach/am62_spl.h
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Suman Anna <s-anna@ti.com>
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARCH_AM62_SPL_H_
|
||||
#define _ASM_ARCH_AM62_SPL_H_
|
||||
|
||||
/* Primary BootMode devices */
|
||||
#define BOOT_DEVICE_RAM 0x00
|
||||
#define BOOT_DEVICE_OSPI 0x01
|
||||
#define BOOT_DEVICE_QSPI 0x02
|
||||
#define BOOT_DEVICE_SPI 0x03
|
||||
#define BOOT_DEVICE_CPGMAC 0x04
|
||||
#define BOOT_DEVICE_ETHERNET_RGMII 0x04
|
||||
#define BOOT_DEVICE_ETHERNET_RMII 0x05
|
||||
#define BOOT_DEVICE_I2C 0x06
|
||||
#define BOOT_DEVICE_UART 0x07
|
||||
#define BOOT_DEVICE_MMC 0x08
|
||||
#define BOOT_DEVICE_EMMC 0x09
|
||||
|
||||
#define BOOT_DEVICE_USB 0x2A
|
||||
#define BOOT_DEVICE_DFU 0x0A
|
||||
#define BOOT_DEVICE_GPMC_NAND 0x0B
|
||||
#define BOOT_DEVICE_GPMC_NOR 0x0C
|
||||
#define BOOT_DEVICE_XSPI 0x0E
|
||||
#define BOOT_DEVICE_NOBOOT 0x0F
|
||||
|
||||
/* U-Boot used aliases */
|
||||
#define BOOT_DEVICE_ETHERNET 0x04
|
||||
#define BOOT_DEVICE_MMC2 0x08
|
||||
#define BOOT_DEVICE_MMC1 0x09
|
||||
/* Invalid */
|
||||
#define BOOT_DEVICE_MMC2_2 0x1F
|
||||
|
||||
/* Backup BootMode devices */
|
||||
#define BACKUP_BOOT_DEVICE_DFU 0x01
|
||||
#define BACKUP_BOOT_DEVICE_UART 0x03
|
||||
#define BACKUP_BOOT_DEVICE_ETHERNET 0x04
|
||||
#define BACKUP_BOOT_DEVICE_MMC 0x05
|
||||
#define BACKUP_BOOT_DEVICE_SPI 0x06
|
||||
#define BACKUP_BOOT_DEVICE_I2C 0x07
|
||||
#define BACKUP_BOOT_DEVICE_USB 0x09
|
||||
|
||||
#define K3_PRIMARY_BOOTMODE 0x0
|
||||
|
||||
#endif /* _ASM_ARCH_AM62_SPL_H_ */
|
||||
|
|
@ -22,6 +22,10 @@
|
|||
#include "am64_hardware.h"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_K3_AM625
|
||||
#include "am62_hardware.h"
|
||||
#endif
|
||||
|
||||
/* Assuming these addresses and definitions stay common across K3 devices */
|
||||
#define CTRLMMR_WKUP_JTAG_ID 0x43000014
|
||||
#define JTAG_ID_VARIANT_SHIFT 28
|
||||
|
|
|
|||
|
|
@ -21,4 +21,9 @@
|
|||
#ifdef CONFIG_SOC_K3_AM642
|
||||
#include "am64_spl.h"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_K3_AM625
|
||||
#include "am62_spl.h"
|
||||
#endif
|
||||
|
||||
#endif /* _ASM_ARCH_SPL_H_ */
|
||||
|
|
|
|||
|
|
@ -64,6 +64,7 @@ choice
|
|||
|
||||
default K3_J721E_DDRSS if SOC_K3_J721E || SOC_K3_J721S2
|
||||
default K3_AM64_DDRSS if SOC_K3_AM642
|
||||
default K3_AM64_DDRSS if SOC_K3_AM625
|
||||
|
||||
config K3_J721E_DDRSS
|
||||
bool "Enable J721E DDRSS support"
|
||||
|
|
|
|||
Loading…
Reference in a new issue