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imx8mn: synchronise device tree with linux

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Synchronise device tree with linux v6.1-rc3.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-By: Tim Harvey <tharvey@gateworks.com> #imx8m{m,n,p}-venice-*
This commit is contained in:
Marcel Ziswiler 2022-11-07 22:22:40 +01:00 committed by Stefano Babic
parent 0b42fdca2d
commit f067b59743
6 changed files with 101 additions and 18 deletions
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4
arch/arm/dts/imx8mn-beacon-baseboard.dtsi
View file

@ -146,7 +146,7 @@
};
&easrc {
fsl,asrc-rate = <48000>;
fsl,asrc-rate = <48000>;
status = "okay";
};
@ -182,7 +182,7 @@
&usbotg1 {
vbus-supply = <&reg_usb_otg_vbus>;
disable-over-current;
dr_mode="otg";
dr_mode = "otg";
status = "okay";
};

45
arch/arm/dts/imx8mn-evk.dtsi
View file

@ -47,6 +47,11 @@
linux,autosuspend-period = <125>;
};
audio_codec_bt_sco: audio-codec-bt-sco {
compatible = "linux,bt-sco";
#sound-dai-cells = <1>;
};
wm8524: audio-codec {
#sound-dai-cells = <0>;
compatible = "wlf,wm8524";
@ -57,6 +62,25 @@
clock-names = "mclk";
};
sound-bt-sco {
compatible = "simple-audio-card";
simple-audio-card,name = "bt-sco-audio";
simple-audio-card,format = "dsp_a";
simple-audio-card,bitclock-inversion;
simple-audio-card,frame-master = <&btcpu>;
simple-audio-card,bitclock-master = <&btcpu>;
btcpu: simple-audio-card,cpu {
sound-dai = <&sai2>;
dai-tdm-slot-num = <2>;
dai-tdm-slot-width = <16>;
};
simple-audio-card,codec {
sound-dai = <&audio_codec_bt_sco 1>;
};
};
sound-wm8524 {
compatible = "fsl,imx-audio-wm8524";
model = "wm8524-audio";
@ -78,7 +102,7 @@
};
&easrc {
fsl,asrc-rate = <48000>;
fsl,asrc-rate = <48000>;
status = "okay";
};
@ -183,6 +207,16 @@
};
};
&sai2 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
assigned-clocks = <&clk IMX8MN_CLK_SAI2>;
assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
status = "okay";
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
@ -354,6 +388,15 @@
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6

6
arch/arm/dts/imx8mn-var-som-symphony.dts
View file

@ -26,19 +26,19 @@
gpio-keys {
compatible = "gpio-keys";
back {
key-back {
label = "Back";
gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_BACK>;
};
home {
key-home {
label = "Home";
gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
};
menu {
key-menu {
label = "Menu";
gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_MENU>;

9
arch/arm/dts/imx8mn-venice-gw7902.dts
View file

@ -39,13 +39,13 @@
gpio-keys {
compatible = "gpio-keys";
user-pb {
key-user-pb {
label = "user_pb";
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
user-pb1x {
key-user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
@ -59,14 +59,14 @@
interrupts = <1>;
};
eeprom-wp {
key-eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
tamper {
key-tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
@ -213,7 +213,6 @@
compatible = "microchip,mcp2515";
reg = <0>;
clocks = <&can20m>;
oscillator-frequency = <20000000>;
interrupt-parent = <&gpio2>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
spi-max-frequency = <10000000>;

14
arch/arm/dts/imx8mn.dtsi
View file

@ -212,7 +212,7 @@
clk_ext4: clock-ext4 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency= <133000000>;
clock-frequency = <133000000>;
clock-output-names = "clk_ext4";
};
@ -269,7 +269,7 @@
arm,no-tick-in-suspend;
};
soc@0 {
soc: soc@0 {
compatible = "fsl,imx8mn-soc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@ -422,7 +422,7 @@
"ctx2_rx", "ctx2_tx",
"ctx3_rx", "ctx3_tx";
firmware-name = "imx/easrc/easrc-imx8mn.bin";
fsl,asrc-rate = <8000>;
fsl,asrc-rate = <8000>;
fsl,asrc-format = <2>;
status = "disabled";
};
@ -672,7 +672,6 @@
<&clk IMX8MN_CLK_GPU_SHADER>,
<&clk IMX8MN_CLK_GPU_BUS_ROOT>,
<&clk IMX8MN_CLK_GPU_AHB>;
resets = <&src IMX8MQ_RESET_GPU_RESET>;
};
pgc_dispmix: power-domain@3 {
@ -857,6 +856,7 @@
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sec_jr1: jr@2000 {
@ -941,7 +941,7 @@
<&clk IMX8MN_CLK_USDHC1_ROOT>;
clock-names = "ipg", "ahb", "per";
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};
@ -955,7 +955,7 @@
<&clk IMX8MN_CLK_USDHC2_ROOT>;
clock-names = "ipg", "ahb", "per";
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};
@ -969,7 +969,7 @@
<&clk IMX8MN_CLK_USDHC3_ROOT>;
clock-names = "ipg", "ahb", "per";
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};

41
include/dt-bindings/interconnect/imx8mn.h Normal file
View file

@ -0,0 +1,41 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Interconnect framework driver for i.MX SoC
*
* Copyright (c) 2019-2020, NXP
*/
#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MN_H
#define __DT_BINDINGS_INTERCONNECT_IMX8MN_H
#define IMX8MN_ICN_NOC 1
#define IMX8MN_ICS_DRAM 2
#define IMX8MN_ICS_OCRAM 3
#define IMX8MN_ICM_A53 4
#define IMX8MN_ICM_GPU 5
#define IMX8MN_ICN_GPU 6
#define IMX8MN_ICM_CSI1 7
#define IMX8MN_ICM_CSI2 8
#define IMX8MN_ICM_ISI 9
#define IMX8MN_ICM_LCDIF 10
#define IMX8MN_ICN_MIPI 11
#define IMX8MN_ICM_USB 12
#define IMX8MN_ICM_SDMA2 13
#define IMX8MN_ICM_SDMA3 14
#define IMX8MN_ICN_AUDIO 15
#define IMX8MN_ICN_ENET 16
#define IMX8MN_ICM_ENET 17
#define IMX8MN_ICM_NAND 18
#define IMX8MN_ICM_SDMA1 19
#define IMX8MN_ICM_USDHC1 20
#define IMX8MN_ICM_USDHC2 21
#define IMX8MN_ICM_USDHC3 22
#define IMX8MN_ICN_MAIN 23
#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MN_H */