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colibri_imx6: synchronise device tree with linux

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Synchronise device tree with linux-next next-20220708.

Please note that this also means that instead of the previous "generic"
U-Boot specific carrier board agnostic device tree we are now using the
regular one for the Colibri Evaluation (carrier) board V3 (e.g.
imx6dl-colibri-eval-v3.dtb rather than the previous imx6-colibri.dtb).

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
This commit is contained in:
Marcel Ziswiler 2022-07-21 15:27:28 +02:00 committed by Stefano Babic
parent 50ba171e2d
commit bd483b7a9f
7 changed files with 1478 additions and 434 deletions
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2
arch/arm/dts/Makefile
View file

@ -895,7 +895,7 @@ dtb-$(CONFIG_MX6ULL) += \
dtb-$(CONFIG_ARCH_MX6) += \
imx6q-apalis-eval.dtb \
imx6-colibri.dtb
imx6dl-colibri-eval-v3.dtb
dtb-$(CONFIG_O4_IMX_NANO) += \
o4-imx-nano.dtb

431
arch/arm/dts/imx6-colibri.dts
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@ -1,431 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* Copyright 2019 Toradex AG
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "imx6dl.dtsi"
/ {
model = "Toradex Colibri iMX6DL/S";
compatible = "toradex,colibri_imx6dl", "fsl,imx6dl";
/* Will be filled by the bootloader */
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0>;
};
aliases {
mmc0 = &usdhc3;
mmc1 = &usdhc1;
usb0 = &usbotg; /* required for ums */
ethernet0 = &fec;
};
chosen {
stdout-path = &uart1;
};
reg_module_3v3: regulator-module-3v3 {
compatible = "regulator-fixed";
regulator-name = "+V3.3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usb_host_vbus: regulator-usb-host-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
regulator-name = "usb_host_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 31 GPIO_ACTIVE_LOW>; /* USBH_PEN */
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rmii";
phy-handle = <&ethphy>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy: ethernet-phy@0 {
reg = <0>;
micrel,led-mode = <0>;
status = "okay";
};
};
};
/*
* PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
* touch screen controller
*/
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
pmic: pfuze100@8 {
compatible = "fsl,pfuze100";
reg = <0x08>;
regulators {
sw1a_reg: sw1ab {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw1c_reg: sw1c {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw3a_reg: sw3a {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-boot-on;
regulator-always-on;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
regulator-boot-on;
regulator-always-on;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-boot-on;
regulator-always-on;
};
/* vgen1: unused */
vgen2_reg: vgen2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
regulator-boot-on;
regulator-always-on;
};
/* vgen3: unused */
vgen4_reg: vgen4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
vgen5_reg: vgen5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
vgen6_reg: vgen6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
/*
* I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
*/
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_recovery>;
scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
/* Colibri UART_A */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
fsl,dte-mode;
uart-has-rtscts;
status = "okay";
};
/* Colibri UART_B */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_dte>;
fsl,dte-mode;
uart-has-rtscts;
status = "okay";
};
/* Colibri UART_C */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_dte>;
fsl,dte-mode;
status = "okay";
};
/* Colibri USBH */
&usbh1 {
dr_mode = "host";
vbus-supply = <&reg_usb_host_vbus>;
status = "okay";
};
/* Colibri USBC */
&usbotg {
dr_mode = "host";
status = "okay";
};
/* Colibri MMC */
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>;
cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */
disable-wp;
vqmmc-supply = <&reg_module_3v3>;
bus-width = <4>;
no-1-8-v;
status = "okay";
};
/* eMMC */
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
vqmmc-supply = <&reg_module_3v3>;
bus-width = <8>;
no-1-8-v;
non-removable;
status = "okay";
};
&iomuxc {
pinctrl_ecspi4: ecspi4grp {
fsl,pins = <
MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
/* SPI CS */
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0)
>;
};
pinctrl_gpio_bl_on: gpioblon {
fsl,pins = <
MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0
>;
};
pinctrl_hdmi_ddc: hdmiddcgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_i2c3_recovery: i2c3recoverygrp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1
MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
>;
};
pinctrl_ipu1_lcdif: ipu1lcdifgrp {
fsl,pins = <
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xa1
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xa1
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0xa1
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0xa1
MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xa1
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xa1
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xa1
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xa1
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xa1
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xa1
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xa1
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xa1
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xa1
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xa1
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xa1
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xa1
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xa1
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xa1
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xa1
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xa1
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xa1
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xa1
>;
};
pinctrl_mmc_cd: gpiommccd {
fsl,pins = <
MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b1
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x00040
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x00040
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
>;
};
pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
fsl,pins = <
/* SODIMM 129 USBH_PEN */
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0f058
>;
};
pinctrl_uart1_dce: uart1dcegrp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
>;
};
/* DTE mode */
pinctrl_uart1_dte: uart1dtegrp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
>;
};
/* Additional DTR, DSR, DCD */
pinctrl_uart1_ctrl: uart1ctrlgrp {
fsl,pins = <
MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
>;
};
pinctrl_uart2_dte: uart2dtegrp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1
MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1
>;
};
pinctrl_uart3_dte: uart3dtegrp {
fsl,pins = <
MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
/* eMMC reset */
MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059
>;
};
};

20
arch/arm/dts/imx6dl-colibri-eval-v3-u-boot.dtsi Normal file
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@ -0,0 +1,20 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2022 Toradex
*/
#include "imx6qdl-u-boot.dtsi"
&{/aliases} {
/* U-Boot won't find PMIC otherwise */
i2c0 = &i2c3;
i2c1 = &i2c2;
/* SDHCI instance order: eMMC, 4-bit SD/MMC (U-Boot won't find ConfigBlock otherwise) */
mmc0 = &usdhc3;
mmc1 = &usdhc1;
};
&wdog1 {
status = "okay";
u-boot,dm-spl;
};

157
arch/arm/dts/imx6dl-colibri-eval-v3.dts Normal file
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@ -0,0 +1,157 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2014-2022 Toradex
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx6dl.dtsi"
#include "imx6qdl-colibri.dtsi"
/ {
model = "Toradex Colibri iMX6DL/S on Colibri Evaluation Board V3";
compatible = "toradex,colibri_imx6dl-eval-v3", "toradex,colibri_imx6dl",
"fsl,imx6dl";
aliases {
i2c0 = &i2c2;
i2c1 = &i2c3;
};
aliases {
rtc0 = &rtc_i2c;
rtc1 = &snvs_rtc;
};
chosen {
stdout-path = "serial0:115200n8";
};
/* Fixed crystal dedicated to mcp251x */
clk16m: clock-16m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <16000000>;
clock-output-names = "clk16m";
};
};
/* Colibri SSP */
&ecspi4 {
status = "okay";
mcp251x0: mcp251x@0 {
compatible = "microchip,mcp2515";
clocks = <&clk16m>;
interrupt-parent = <&gpio3>;
interrupts = <27 0x2>;
reg = <0>;
spi-max-frequency = <10000000>;
status = "okay";
};
};
/*
* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
*/
&i2c3 {
status = "okay";
/* M41T0M6 real time clock on carrier board */
rtc_i2c: rtc@68 {
compatible = "st,m41t0";
reg = <0x68>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <
&pinctrl_weim_gpio_1 &pinctrl_weim_gpio_2
&pinctrl_weim_gpio_3 &pinctrl_weim_gpio_4
&pinctrl_weim_gpio_5 &pinctrl_weim_gpio_6
&pinctrl_usbh_oc_1 &pinctrl_usbc_id_1
>;
};
&pwm1 {
status = "okay";
};
&pwm2 {
status = "okay";
};
&pwm3 {
status = "okay";
};
&pwm4 {
status = "okay";
};
&reg_usb_host_vbus {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&uart3 {
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_host_vbus>;
status = "okay";
};
&usbotg {
status = "okay";
};
/* Colibri MMC */
&usdhc1 {
status = "okay";
};
&weim {
status = "okay";
/* weim memory map: 32MB on CS0, CS1, CS2 and CS3 */
ranges = <0 0 0x08000000 0x02000000
1 0 0x0a000000 0x02000000
2 0 0x0c000000 0x02000000
3 0 0x0e000000 0x02000000>;
/* SRAM on Colibri nEXT_CS0 */
sram@0,0 {
compatible = "cypress,cy7c1019dv33-10zsxi", "mtd-ram";
reg = <0 0 0x00010000>;
#address-cells = <1>;
#size-cells = <1>;
bank-width = <2>;
fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000
0x00000000 0x04000040 0x00000000>;
};
/* SRAM on Colibri nEXT_CS1 */
sram@1,0 {
compatible = "cypress,cy7c1019dv33-10zsxi", "mtd-ram";
reg = <1 0 0x00010000>;
#address-cells = <1>;
#size-cells = <1>;
bank-width = <2>;
fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000
0x00000000 0x04000040 0x00000000>;
};
};

1296
arch/arm/dts/imx6qdl-colibri.dtsi Normal file
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File diff suppressed because it is too large Load diff

4
board/toradex/colibri_imx6/MAINTAINERS
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@ -6,4 +6,6 @@ S: Maintained
F: board/toradex/colibri_imx6/
F: include/configs/colibri_imx6.h
F: configs/colibri_imx6_defconfig
F: arch/arm/dts/imx6-colibri.dts
F: arch/arm/dts/imx6dl-colibri-eval-v3.dts
F: arch/arm/dts/imx6dl-colibri-eval-v3-u-boot.dtsi
F: arch/arm/dts/imx6qdl-colibri.dtsi

2
configs/colibri_imx6_defconfig
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@ -15,7 +15,7 @@ CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6-colibri"
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-colibri-eval-v3"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y