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arm: kirkwood: nsa310s: Use Marvell uclass mvgbe and PHY driver for DM Ethernet
The Zyxel NSA310s board has the network chip Marvell Alaska 88E1318S. Use uclass mvgbe and the compatible driver M88E1310 driver to bring up Ethernet. - Use uclass mvgbe to bring up the network. And remove ad-hoc code. - Remove CONFIG_RESET_PHY_R. - Enable CONFIG_PHY_MARVELL to properly configure the network. - Add phy mode RGMII to kirkwood-nsa310s.dts - Miscellaneous changes: Move constants to .c file and remove header file board/zyxel/nsa310s/nsa310s.h, add support for large USB and SATA HDDs, use BIT macro, add/cleanup comments, and cosmetic changes. Note that this patch is depended on the following patch: https://patchwork.ozlabs.org/project/uboot/patch/20220412201820.10291-1-mibodhi@gmail.com/ Signed-off-by: Tony Dinh <mibodhi@gmail.com>
This commit is contained in:
Tony Dinh
Stefan Roese
parent
f0f98758ed
commit
dbd2a382c1
5 changed files with 41 additions and 142 deletions
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@ -306,6 +306,7 @@
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status = "okay";
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ethernet0-port@0 {
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phy-handle = <ðphy0>;
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phy-mode = "rgmii";
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};
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};
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@ -1,22 +1,49 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015, 2021 Tony Dinh <mibodhi@gmail.com>
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* Copyright (C) 2015, 2021-2022 Tony Dinh <mibodhi@gmail.com>
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* Copyright (C) 2015 Gerald Kerma <dreagle@doukki.net>
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*/
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#include <common.h>
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#include <init.h>
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#include <miiphy.h>
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#include <net.h>
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#include <netdev.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <asm/arch/mpp.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include "nsa310s.h"
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#include <linux/bitops.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* low GPIO's
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*/
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#define HDD1_GREEN_LED BIT(16)
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#define HDD1_RED_LED BIT(13)
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#define USB_GREEN_LED BIT(15)
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#define USB_POWER BIT(21)
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#define SYS_GREEN_LED BIT(28)
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#define SYS_ORANGE_LED BIT(29)
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#define COPY_GREEN_LED BIT(22)
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#define COPY_RED_LED BIT(23)
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#define PIN_USB_GREEN_LED 15
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#define PIN_USB_POWER 21
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#define NSA310S_OE_LOW (~(0))
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#define NSA310S_VAL_LOW (SYS_GREEN_LED | USB_POWER)
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/*
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* high GPIO's
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*/
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#define HDD2_GREEN_LED BIT(2)
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#define HDD2_POWER BIT(1)
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#define NSA310S_OE_HIGH (~(0))
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#define NSA310S_VAL_HIGH (HDD2_POWER)
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int board_early_init_f(void)
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{
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/*
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@ -80,87 +107,7 @@ int board_init(void)
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return 0;
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}
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static int fdt_get_phy_addr(const char *path)
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int board_eth_init(struct bd_info *bis)
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{
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const void *fdt = gd->fdt_blob;
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const u32 *reg;
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const u32 *val;
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int node, phandle, addr;
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/* Find the node by its full path */
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node = fdt_path_offset(fdt, path);
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if (node >= 0) {
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/* Look up phy-handle */
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val = fdt_getprop(fdt, node, "phy-handle", NULL);
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if (val) {
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phandle = fdt32_to_cpu(*val);
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if (!phandle)
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return -1;
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/* Follow it to its node */
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node = fdt_node_offset_by_phandle(fdt, phandle);
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if (node) {
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/* Look up reg */
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reg = fdt_getprop(fdt, node, "reg", NULL);
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if (reg) {
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addr = fdt32_to_cpu(*reg);
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return addr;
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}
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}
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}
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}
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return -1;
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return cpu_eth_init(bis);
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}
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#ifdef CONFIG_RESET_PHY_R
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void reset_phy(void)
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{
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u16 reg;
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u16 phyaddr;
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char *name = "ethernet-controller@72000";
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char *eth0_path = "/ocp@f1000000/ethernet-controller@72000/ethernet0-port@0";
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if (miiphy_set_current_dev(name))
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return;
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phyaddr = fdt_get_phy_addr(eth0_path);
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if (phyaddr < 0)
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return;
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/* set RGMII delay */
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miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_MAC_CTRL_PG);
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miiphy_read(name, phyaddr, MV88E1318_MAC_CTRL_REG, ®);
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reg |= (MV88E1318_RGMII_RX_CTRL | MV88E1318_RGMII_TX_CTRL);
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miiphy_write(name, phyaddr, MV88E1318_MAC_CTRL_REG, reg);
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miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0);
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/* reset PHY */
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if (miiphy_reset(name, phyaddr))
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return;
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/*
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* ZyXEL NSA310S uses the 88E1310S Alaska (interface identical to 88E1318)
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* and has an MCU attached to the LED[2] via tristate interrupt
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*/
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/* switch to LED register page */
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miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_LED_PG);
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/* read out LED polarity register */
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miiphy_read(name, phyaddr, MV88E1318_LED_POL_REG, ®);
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/* clear 4, set 5 - LED2 low, tri-state */
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reg &= ~(MV88E1318_LED2_4);
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reg |= (MV88E1318_LED2_5);
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/* write back LED polarity register */
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miiphy_write(name, phyaddr, MV88E1318_LED_POL_REG, reg);
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/* jump back to page 0, per the PHY chip documenation. */
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miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0);
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/* set PHY back to auto-negotiation mode */
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miiphy_write(name, phyaddr, 0x4, 0x1e1);
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miiphy_write(name, phyaddr, 0x9, 0x300);
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/* downshift */
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miiphy_write(name, phyaddr, 0x10, 0x3860);
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miiphy_write(name, phyaddr, 0x0, 0x9140);
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printf("MV88E1318 PHY initialized on %s\n", name);
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}
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#endif /* CONFIG_RESET_PHY_R */
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@ -1,46 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2015
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* Gerald Kerma <dreagle@doukki.net>
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* Tony Dinh <mibodhi@gmail.com>
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*/
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#ifndef __NSA310S_H
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#define __NSA310S_H
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/* low GPIO's */
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#define HDD1_GREEN_LED (1 << 16)
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#define HDD1_RED_LED (1 << 13)
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#define USB_GREEN_LED (1 << 15)
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#define USB_POWER (1 << 21)
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#define SYS_GREEN_LED (1 << 28)
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#define SYS_ORANGE_LED (1 << 29)
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#define COPY_GREEN_LED (1 << 22)
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#define COPY_RED_LED (1 << 23)
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#define PIN_USB_GREEN_LED 15
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#define PIN_USB_POWER 21
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#define NSA310S_OE_LOW (~(0))
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#define NSA310S_VAL_LOW (SYS_GREEN_LED | USB_POWER)
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/* high GPIO's */
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#define HDD2_GREEN_LED (1 << 2)
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#define HDD2_POWER (1 << 1)
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#define NSA310S_OE_HIGH (~(0))
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#define NSA310S_VAL_HIGH (HDD2_POWER)
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/* PHY related */
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#define MV88E1318_PGADR_REG 22
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#define MV88E1318_MAC_CTRL_PG 2
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#define MV88E1318_MAC_CTRL_REG 21
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#define MV88E1318_RGMII_TX_CTRL (1 << 4)
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#define MV88E1318_RGMII_RX_CTRL (1 << 5)
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#define MV88E1318_LED_PG 3
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#define MV88E1318_LED_POL_REG 17
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#define MV88E1318_LED2_4 (1 << 4)
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#define MV88E1318_LED2_5 (1 << 5)
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#endif /* __NSA310S_H */
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@ -2,6 +2,7 @@ CONFIG_ARM=y
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CONFIG_SKIP_LOWLEVEL_INIT=y
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CONFIG_SYS_DCACHE_OFF=y
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CONFIG_ARCH_CPU_INIT=y
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CONFIG_SYS_THUMB_BUILD=y
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CONFIG_ARCH_KIRKWOOD=y
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CONFIG_SYS_KWD_CONFIG="board/zyxel/nsa310s/kwbimage.cfg"
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CONFIG_SYS_TEXT_BASE=0x600000
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@ -18,9 +19,8 @@ CONFIG_USE_BOOTCOMMAND=y
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CONFIG_BOOTCOMMAND="setenv bootargs ${console} ${mtdparts} ${bootargs_root}; ubi part root; ubifsmount ubi:rootfs; ubifsload 0x800000 ${kernel}; ubifsload 0x700000 ${fdt}; ubifsumount; fdt addr 0x700000; fdt resize; fdt chosen; bootz 0x800000 - 0x700000"
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CONFIG_USE_PREBOOT=y
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# CONFIG_DISPLAY_BOARDINFO is not set
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CONFIG_RESET_PHY_R=y
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CONFIG_HUSH_PARSER=y
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CONFIG_SYS_PROMPT="nsa310s => "
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CONFIG_SYS_PROMPT="NSA310s> "
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CONFIG_CMD_BOOTZ=y
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# CONFIG_CMD_FLASH is not set
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CONFIG_CMD_NAND=y
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@ -32,6 +32,7 @@ CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_EXT2=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FS_GENERIC=y
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CONFIG_CMD_JFFS2=y
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CONFIG_CMD_MTDPARTS=y
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CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0xe0000@0x0(uboot),0x20000@0xe0000(uboot_env),0x100000@0x100000(second_stage_uboot),-@0x200000(root)"
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@ -50,6 +51,7 @@ CONFIG_SYS_SATA_MAX_DEVICE=1
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# CONFIG_MMC is not set
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_PHY_MARVELL=y
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CONFIG_DM_ETH=y
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CONFIG_MVGBE=y
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CONFIG_MII=y
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2015, 2021 Tony Dinh <mibodhi@gmail.com>
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* Copyright (C) 2015, 2021-2022 Tony Dinh <mibodhi@gmail.com>
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* Copyright (C) 2015
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* Gerald Kerma <dreagle@doukki.net>
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* Luka Perkov <luka.perkov@sartura.hr>
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@ -11,8 +11,6 @@
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#include "mv-common.h"
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/* environment variables configuration */
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/* default environment variables */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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@ -24,14 +22,11 @@
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"bootargs_root=ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs rw\0"
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/* Ethernet driver configuration */
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#ifdef CONFIG_CMD_NET
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#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
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#define CONFIG_PHY_BASE_ADR 1
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#endif /* CONFIG_CMD_NET */
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/* SATA driver configuration */
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#ifdef CONFIG_SATA
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/* Support large HDDs for USB and SATA */
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#define CONFIG_LBA48
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#endif /* CONFIG_SATA */
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#define CONFIG_SYS_64BIT_LBA
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#endif /* _CONFIG_NSA310S_H */
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