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- Increase SYS_MALLOC_F_LEN for STM32 MCU's board

Browse source 
- SPL fixes for STM32F7 MCUs
 - Device tree alignement with kernelv6.0-rc4 for MCU's board
 - Device tree alignement with kernelv6.0-rc3 for MPU's board
 - Update DDR node for STM32MP15
 - Cleanup config file for STM32MP1
 - Update for cmd_stm32key command
 - Fix compatible string to add partitions for STM32MP1
 - Update for stm32programmer tool
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Merge tag 'u-boot-stm32-20220927' of https://source.denx.de/u-boot/custodians/u-boot-stm into next

- Increase SYS_MALLOC_F_LEN for STM32 MCU's board
- SPL fixes for STM32F7 MCUs
- Device tree alignement with kernelv6.0-rc4 for MCU's board
- Device tree alignement with kernelv6.0-rc3 for MPU's board
- Update DDR node for STM32MP15
- Cleanup config file for STM32MP1
- Update for cmd_stm32key command
- Fix compatible string to add partitions for STM32MP1
- Update for stm32programmer tool
This commit is contained in:
Tom Rini 2022-09-27 08:53:51 -04:00
commit 01c88e3dcd
52 changed files with 631 additions and 466 deletions
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2
arch/arm/dts/stm32429i-eval-u-boot.dtsi
View file

@ -218,6 +218,6 @@
};
};
&timer5 {
&timers5 {
u-boot,dm-pre-reloc;
};

18
arch/arm/dts/stm32746g-eval.dts
View file

@ -45,12 +45,10 @@
};
};
gpio_keys {
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
button@0 {
button-0 {
label = "Wake up";
linux,code = <KEY_WAKEUP>;
gpios = <&gpioc 13 0>;
@ -160,6 +158,18 @@
bus-width = <4>;
};
&timers5 {
/* Override timer5 to act as clockevent */
compatible = "st,stm32-timer";
interrupts = <50>;
status = "okay";
/delete-property/#address-cells;
/delete-property/#size-cells;
/delete-property/clock-names;
/delete-node/pwm;
/delete-node/timer@4;
};
&usart1 {
pinctrl-0 = <&usart1_pins_a>;
pinctrl-names = "default";

2
arch/arm/dts/stm32f4-pinctrl.dtsi
View file

@ -9,7 +9,7 @@
/ {
soc {
pinctrl: pin-controller {
pinctrl: pinctrl@40020000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x40020000 0x3000>;

8
arch/arm/dts/stm32f429-disco-u-boot.dtsi
View file

@ -27,10 +27,6 @@
soc {
u-boot,dm-pre-reloc;
pin-controller {
u-boot,dm-pre-reloc;
};
fmc: fmc@A0000000 {
compatible = "st,stm32-fmc";
reg = <0xa0000000 0x1000>;
@ -123,6 +119,8 @@
};
&pinctrl {
u-boot,dm-pre-reloc;
usart1_pins_a: usart1-0 {
u-boot,dm-pre-reloc;
pins1 {
@ -193,6 +191,6 @@
u-boot,dm-pre-reloc;
};
&timer5 {
&timers5 {
u-boot,dm-pre-reloc;
};

20
arch/arm/dts/stm32f429-disco.dts
View file

@ -39,12 +39,10 @@
};
};
gpio_keys {
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
button@0 {
button-0 {
label = "User";
linux,code = <KEY_HOME>;
gpios = <&gpioa 0 0>;
@ -152,7 +150,7 @@
display: display@1{
/* Connect panel-ilitek-9341 to ltdc */
compatible = "st,sf-tc240t-9370-t";
compatible = "st,sf-tc240t-9370-t", "ilitek,ili9341";
reg = <1>;
spi-3wire;
spi-max-frequency = <10000000>;
@ -165,6 +163,18 @@
};
};
&timers5 {
/* Override timer5 to act as clockevent */
compatible = "st,stm32-timer";
interrupts = <50>;
status = "okay";
/delete-property/#address-cells;
/delete-property/#size-cells;
/delete-property/clock-names;
/delete-node/pwm;
/delete-node/timer@4;
};
&usart1 {
pinctrl-0 = <&usart1_pins_a>;
pinctrl-names = "default";

72
arch/arm/dts/stm32f429-pinctrl.dtsi
View file

@ -6,54 +6,50 @@
#include "stm32f4-pinctrl.dtsi"
/ {
soc {
pinctrl: pin-controller {
compatible = "st,stm32f429-pinctrl";
&pinctrl {
compatible = "st,stm32f429-pinctrl";
gpioa: gpio@40020000 {
gpio-ranges = <&pinctrl 0 0 16>;
};
gpioa: gpio@40020000 {
gpio-ranges = <&pinctrl 0 0 16>;
};
gpiob: gpio@40020400 {
gpio-ranges = <&pinctrl 0 16 16>;
};
gpiob: gpio@40020400 {
gpio-ranges = <&pinctrl 0 16 16>;
};
gpioc: gpio@40020800 {
gpio-ranges = <&pinctrl 0 32 16>;
};
gpioc: gpio@40020800 {
gpio-ranges = <&pinctrl 0 32 16>;
};
gpiod: gpio@40020c00 {
gpio-ranges = <&pinctrl 0 48 16>;
};
gpiod: gpio@40020c00 {
gpio-ranges = <&pinctrl 0 48 16>;
};
gpioe: gpio@40021000 {
gpio-ranges = <&pinctrl 0 64 16>;
};
gpioe: gpio@40021000 {
gpio-ranges = <&pinctrl 0 64 16>;
};
gpiof: gpio@40021400 {
gpio-ranges = <&pinctrl 0 80 16>;
};
gpiof: gpio@40021400 {
gpio-ranges = <&pinctrl 0 80 16>;
};
gpiog: gpio@40021800 {
gpio-ranges = <&pinctrl 0 96 16>;
};
gpiog: gpio@40021800 {
gpio-ranges = <&pinctrl 0 96 16>;
};
gpioh: gpio@40021c00 {
gpio-ranges = <&pinctrl 0 112 16>;
};
gpioh: gpio@40021c00 {
gpio-ranges = <&pinctrl 0 112 16>;
};
gpioi: gpio@40022000 {
gpio-ranges = <&pinctrl 0 128 16>;
};
gpioi: gpio@40022000 {
gpio-ranges = <&pinctrl 0 128 16>;
};
gpioj: gpio@40022400 {
gpio-ranges = <&pinctrl 0 144 16>;
};
gpioj: gpio@40022400 {
gpio-ranges = <&pinctrl 0 144 16>;
};
gpiok: gpio@40022800 {
gpio-ranges = <&pinctrl 0 160 8>;
};
};
gpiok: gpio@40022800 {
gpio-ranges = <&pinctrl 0 160 8>;
};
};

69
arch/arm/dts/stm32f429.dtsi
View file

@ -52,14 +52,6 @@
};
};
timer2: timer@40000000 {
compatible = "st,stm32-timer";
reg = <0x40000000 0x400>;
interrupts = <28>;
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
status = "disabled";
};
timers2: timers@40000000 {
#address-cells = <1>;
#size-cells = <0>;
@ -82,14 +74,6 @@
};
};
timer3: timer@40000400 {
compatible = "st,stm32-timer";
reg = <0x40000400 0x400>;
interrupts = <29>;
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
status = "disabled";
};
timers3: timers@40000400 {
#address-cells = <1>;
#size-cells = <0>;
@ -112,14 +96,6 @@
};
};
timer4: timer@40000800 {
compatible = "st,stm32-timer";
reg = <0x40000800 0x400>;
interrupts = <30>;
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
status = "disabled";
};
timers4: timers@40000800 {
#address-cells = <1>;
#size-cells = <0>;
@ -142,13 +118,6 @@
};
};
timer5: timer@40000c00 {
compatible = "st,stm32-timer";
reg = <0x40000c00 0x400>;
interrupts = <50>;
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
};
timers5: timers@40000c00 {
#address-cells = <1>;
#size-cells = <0>;
@ -171,14 +140,6 @@
};
};
timer6: timer@40001000 {
compatible = "st,stm32-timer";
reg = <0x40001000 0x400>;
interrupts = <54>;
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
status = "disabled";
};
timers6: timers@40001000 {
#address-cells = <1>;
#size-cells = <0>;
@ -195,14 +156,6 @@
};
};
timer7: timer@40001400 {
compatible = "st,stm32-timer";
reg = <0x40001400 0x400>;
interrupts = <55>;
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
status = "disabled";
};
timers7: timers@40001400 {
#address-cells = <1>;
#size-cells = <0>;
@ -242,8 +195,6 @@
};
timers13: timers@40001c00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40001C00 0x400>;
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
@ -258,8 +209,6 @@
};
timers14: timers@40002000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40002000 0x400>;
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
@ -525,7 +474,7 @@
};
};
sdio: sdio@40012c00 {
sdio: mmc@40012c00 {
compatible = "arm,pl180", "arm,primecell";
arm,primecell-periphid = <0x00880180>;
reg = <0x40012c00 0x400>;
@ -592,8 +541,6 @@
};
timers10: timers@40014400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40014400 0x400>;
clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
@ -608,8 +555,6 @@
};
timers11: timers@40014800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40014800 0x400>;
clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
@ -668,7 +613,7 @@
status = "disabled";
};
rcc: rcc@40023810 {
rcc: rcc@40023800 {
#reset-cells = <1>;
#clock-cells = <2>;
compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
@ -726,6 +671,16 @@
status = "disabled";
};
dma2d: dma2d@4002b000 {
compatible = "st,stm32-dma2d";
reg = <0x4002b000 0xc00>;
interrupts = <90>;
resets = <&rcc STM32F4_AHB1_RESET(DMA2D)>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2D)>;
clock-names = "dma2d";
status = "disabled";
};
usbotg_hs: usb@40040000 {
compatible = "snps,dwc2";
reg = <0x40040000 0x40000>;

7
arch/arm/dts/stm32f469-disco-u-boot.dtsi
View file

@ -28,9 +28,6 @@
soc {
u-boot,dm-pre-reloc;
pin-controller {
u-boot,dm-pre-reloc;
};
fmc: fmc@A0000000 {
compatible = "st,stm32-fmc";
@ -138,6 +135,8 @@
};
&pinctrl {
u-boot,dm-pre-reloc;
fmc_pins_d32: fmc_d32@0 {
u-boot,dm-pre-reloc;
pins
@ -256,6 +255,6 @@
u-boot,dm-pre-reloc;
};
&timer5 {
&timers5 {
u-boot,dm-pre-reloc;
};

24
arch/arm/dts/stm32f469-disco.dts
View file

@ -19,7 +19,7 @@
stdout-path = "serial0:115200n8";
};
memory@00000000 {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x1000000>;
};
@ -63,12 +63,10 @@
};
};
gpio_keys {
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
button@0 {
button-0 {
label = "User";
linux,code = <KEY_WAKEUP>;
gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
@ -93,6 +91,10 @@
clock-frequency = <8000000>;
};
&dma2d {
status = "okay";
};
&dsi {
#address-cells = <1>;
#size-cells = <0>;
@ -185,6 +187,18 @@
bus-width = <4>;
};
&timers5 {
/* Override timer5 to act as clockevent */
compatible = "st,stm32-timer";
interrupts = <50>;
status = "okay";
/delete-property/#address-cells;
/delete-property/#size-cells;
/delete-property/clock-names;
/delete-node/pwm;
/delete-node/timer@4;
};
&usart3 {
pinctrl-0 = <&usart3_pins_a>;
pinctrl-names = "default";

74
arch/arm/dts/stm32f469-pinctrl.dtsi
View file

@ -5,55 +5,51 @@
#include "stm32f4-pinctrl.dtsi"
/ {
soc {
pinctrl: pin-controller {
compatible = "st,stm32f469-pinctrl";
&pinctrl {
compatible = "st,stm32f469-pinctrl";
gpioa: gpio@40020000 {
gpio-ranges = <&pinctrl 0 0 16>;
};
gpioa: gpio@40020000 {
gpio-ranges = <&pinctrl 0 0 16>;
};
gpiob: gpio@40020400 {
gpio-ranges = <&pinctrl 0 16 16>;
};
gpiob: gpio@40020400 {
gpio-ranges = <&pinctrl 0 16 16>;
};
gpioc: gpio@40020800 {
gpio-ranges = <&pinctrl 0 32 16>;
};
gpioc: gpio@40020800 {
gpio-ranges = <&pinctrl 0 32 16>;
};
gpiod: gpio@40020c00 {
gpio-ranges = <&pinctrl 0 48 16>;
};
gpiod: gpio@40020c00 {
gpio-ranges = <&pinctrl 0 48 16>;
};
gpioe: gpio@40021000 {
gpio-ranges = <&pinctrl 0 64 16>;
};
gpioe: gpio@40021000 {
gpio-ranges = <&pinctrl 0 64 16>;
};
gpiof: gpio@40021400 {
gpio-ranges = <&pinctrl 0 80 16>;
};
gpiof: gpio@40021400 {
gpio-ranges = <&pinctrl 0 80 16>;
};
gpiog: gpio@40021800 {
gpio-ranges = <&pinctrl 0 96 16>;
};
gpiog: gpio@40021800 {
gpio-ranges = <&pinctrl 0 96 16>;
};
gpioh: gpio@40021c00 {
gpio-ranges = <&pinctrl 0 112 16>;
};
gpioh: gpio@40021c00 {
gpio-ranges = <&pinctrl 0 112 16>;
};
gpioi: gpio@40022000 {
gpio-ranges = <&pinctrl 0 128 16>;
};
gpioi: gpio@40022000 {
gpio-ranges = <&pinctrl 0 128 16>;
};
gpioj: gpio@40022400 {
gpio-ranges = <&pinctrl 0 144 6>,
<&pinctrl 12 156 4>;
};
gpioj: gpio@40022400 {
gpio-ranges = <&pinctrl 0 144 6>,
<&pinctrl 12 156 4>;
};
gpiok: gpio@40022800 {
gpio-ranges = <&pinctrl 3 163 5>;
};
};
gpiok: gpio@40022800 {
gpio-ranges = <&pinctrl 3 163 5>;
};
};

2
arch/arm/dts/stm32f7-pinctrl.dtsi
View file

@ -9,7 +9,7 @@
/ {
soc {
pinctrl: pin-controller {
pinctrl: pinctrl@40020000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x40020000 0x3000>;

2
arch/arm/dts/stm32f7-u-boot.dtsi
View file

@ -119,7 +119,7 @@
u-boot,dm-pre-reloc;
};
&timer5 {
&timers5 {
u-boot,dm-pre-reloc;
};

12
arch/arm/dts/stm32f746-disco.dts
View file

@ -73,6 +73,18 @@
bus-width = <4>;
};
&timers5 {
/* Override timer5 to act as clockevent */
compatible = "st,stm32-timer";
interrupts = <50>;
status = "okay";
/delete-property/#address-cells;
/delete-property/#size-cells;
/delete-property/clock-names;
/delete-node/pwm;
/delete-node/timer@4;
};
&usart1 {
pinctrl-0 = <&usart1_pins_b>;
pinctrl-names = "default";

67
arch/arm/dts/stm32f746.dtsi
View file

@ -39,14 +39,6 @@
};
soc {
timer2: timer@40000000 {
compatible = "st,stm32-timer";
reg = <0x40000000 0x400>;
interrupts = <28>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
status = "disabled";
};
timers2: timers@40000000 {
#address-cells = <1>;
#size-cells = <0>;
@ -69,14 +61,6 @@
};
};
timer3: timer@40000400 {
compatible = "st,stm32-timer";
reg = <0x40000400 0x400>;
interrupts = <29>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
status = "disabled";
};
timers3: timers@40000400 {
#address-cells = <1>;
#size-cells = <0>;
@ -99,14 +83,6 @@
};
};
timer4: timer@40000800 {
compatible = "st,stm32-timer";
reg = <0x40000800 0x400>;
interrupts = <30>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
status = "disabled";
};
timers4: timers@40000800 {
#address-cells = <1>;
#size-cells = <0>;
@ -129,13 +105,6 @@
};
};
timer5: timer@40000c00 {
compatible = "st,stm32-timer";
reg = <0x40000c00 0x400>;
interrupts = <50>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
};
timers5: timers@40000c00 {
#address-cells = <1>;
#size-cells = <0>;
@ -158,14 +127,6 @@
};
};
timer6: timer@40001000 {
compatible = "st,stm32-timer";
reg = <0x40001000 0x400>;
interrupts = <54>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
status = "disabled";
};
timers6: timers@40001000 {
#address-cells = <1>;
#size-cells = <0>;
@ -182,14 +143,6 @@
};
};
timer7: timer@40001400 {
compatible = "st,stm32-timer";
reg = <0x40001400 0x400>;
interrupts = <55>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
status = "disabled";
};
timers7: timers@40001400 {
#address-cells = <1>;
#size-cells = <0>;
@ -229,8 +182,6 @@
};
timers13: timers@40001c00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40001C00 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
@ -245,8 +196,6 @@
};
timers14: timers@40002000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40002000 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
@ -313,7 +262,6 @@
clocks = <&rcc 1 CLK_I2C1>;
#address-cells = <1>;
#size-cells = <0>;
i2c-analog-filter;
status = "disabled";
};
@ -326,20 +274,18 @@
clocks = <&rcc 1 CLK_I2C2>;
#address-cells = <1>;
#size-cells = <0>;
i2c-analog-filter;
status = "disabled";
};
i2c3: i2c@40005C00 {
i2c3: i2c@40005c00 {
compatible = "st,stm32f7-i2c";
reg = <0x40005C00 0x400>;
reg = <0x40005c00 0x400>;
interrupts = <72>,
<73>;
resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
clocks = <&rcc 1 CLK_I2C3>;
#address-cells = <1>;
#size-cells = <0>;
i2c-analog-filter;
status = "disabled";
};
@ -352,7 +298,6 @@
clocks = <&rcc 1 CLK_I2C4>;
#address-cells = <1>;
#size-cells = <0>;
i2c-analog-filter;
status = "disabled";
};
@ -441,7 +386,7 @@
status = "disabled";
};
sdio2: sdio2@40011c00 {
sdio2: mmc@40011c00 {
compatible = "arm,pl180", "arm,primecell";
arm,primecell-periphid = <0x00880180>;
reg = <0x40011c00 0x400>;
@ -452,7 +397,7 @@
status = "disabled";
};
sdio1: sdio1@40012c00 {
sdio1: mmc@40012c00 {
compatible = "arm,pl180", "arm,primecell";
arm,primecell-periphid = <0x00880180>;
reg = <0x40012c00 0x400>;
@ -499,8 +444,6 @@
};
timers10: timers@40014400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40014400 0x400>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
@ -515,8 +458,6 @@
};
timers11: timers@40014800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40014800 0x400>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;

18
arch/arm/dts/stm32f769-disco.dts
View file

@ -39,12 +39,10 @@
};
};
gpio_keys {
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
button@0 {
button-0 {
label = "User";
linux,code = <KEY_HOME>;
gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
@ -103,6 +101,18 @@
bus-width = <4>;
};
&timers5 {
/* Override timer5 to act as clockevent */
compatible = "st,stm32-timer";
interrupts = <50>;
status = "okay";
/delete-property/#address-cells;
/delete-property/#size-cells;
/delete-property/clock-names;
/delete-node/pwm;
/delete-node/timer@4;
};
&usart1 {
pinctrl-0 = <&usart1_pins_a>;
pinctrl-names = "default";

19
arch/arm/dts/stm32h743.dtsi
View file

@ -124,7 +124,6 @@
<32>;
resets = <&rcc STM32H7_APB1L_RESET(I2C1)>;
clocks = <&rcc I2C1_CK>;
i2c-analog-filter;
status = "disabled";
};
@ -137,7 +136,6 @@
<34>;
resets = <&rcc STM32H7_APB1L_RESET(I2C2)>;
clocks = <&rcc I2C2_CK>;
i2c-analog-filter;
status = "disabled";
};
@ -150,7 +148,6 @@
<73>;
resets = <&rcc STM32H7_APB1L_RESET(I2C3)>;
clocks = <&rcc I2C3_CK>;
i2c-analog-filter;
status = "disabled";
};
@ -337,12 +334,12 @@
dma-requests = <32>;
};
sdmmc1: sdmmc@52007000 {
sdmmc1: mmc@52007000 {
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x10153180>;
reg = <0x52007000 0x1000>;
interrupts = <49>;
interrupt-names = "cmd_irq";
interrupt-names = "cmd_irq";
clocks = <&rcc SDMMC1_CK>;
clock-names = "apb_pclk";
resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
@ -351,18 +348,19 @@
max-frequency = <120000000>;
};
sdmmc2: sdmmc@48022400 {
sdmmc2: mmc@48022400 {
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x10153180>;
reg = <0x48022400 0x400>;
interrupts = <124>;
interrupt-names = "cmd_irq";
interrupt-names = "cmd_irq";
clocks = <&rcc SDMMC2_CK>;
clock-names = "apb_pclk";
resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <120000000>;
status = "disabled";
};
exti: interrupt-controller@58000000 {
@ -398,7 +396,6 @@
<96>;
resets = <&rcc STM32H7_APB4_RESET(I2C4)>;
clocks = <&rcc I2C4_CK>;
i2c-analog-filter;
status = "disabled";
};
@ -452,8 +449,6 @@
};
lptimer4: timer@58002c00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x58002c00 0x400>;
clocks = <&rcc LPTIM4_CK>;
@ -468,8 +463,6 @@
};
lptimer5: timer@58003000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x58003000 0x400>;
clocks = <&rcc LPTIM5_CK>;
@ -554,7 +547,7 @@
status = "disabled";
};
pinctrl: pin-controller@58020000 {
pinctrl: pinctrl@58020000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32h743-pinctrl";

8
arch/arm/dts/stm32h743i-disco.dts
View file

@ -41,10 +41,10 @@
&mac {
status = "disabled";
pinctrl-0 = <&ethernet_rmii>;
pinctrl-names = "default";
phy-mode = "rmii";
phy-handle = <&phy0>;
pinctrl-0 = <&ethernet_rmii>;
pinctrl-names = "default";
phy-mode = "rmii";
phy-handle = <&phy0>;
mdio0 {
#address-cells = <1>;

8
arch/arm/dts/stm32h743i-eval.dts
View file

@ -115,10 +115,10 @@
&mac {
status = "disabled";
pinctrl-0 = <&ethernet_rmii>;
pinctrl-names = "default";
phy-mode = "rmii";
phy-handle = <&phy0>;
pinctrl-0 = <&ethernet_rmii>;
pinctrl-names = "default";
phy-mode = "rmii";
phy-handle = <&phy0>;
mdio0 {
#address-cells = <1>;

8
arch/arm/dts/stm32h750i-art-pi.dts
View file

@ -87,10 +87,10 @@
&mac {
status = "disabled";
pinctrl-0 = <&ethernet_rmii>;
pinctrl-names = "default";
phy-mode = "rmii";
phy-handle = <&phy0>;
pinctrl-0 = <&ethernet_rmii>;
pinctrl-names = "default";
phy-mode = "rmii";
phy-handle = <&phy0>;
mdio0 {
#address-cells = <1>;

10
arch/arm/dts/stm32mp13-u-boot.dtsi
View file

@ -17,6 +17,12 @@
pinctrl0 = &pinctrl;
};
firmware {
optee {
u-boot,dm-pre-reloc;
};
};
/* need PSCI for sysreset during board_f */
psci {
u-boot,dm-pre-proper;
@ -82,10 +88,6 @@
u-boot,dm-pre-reloc;
};
&optee {
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};

28
arch/arm/dts/stm32mp131.dtsi
View file

@ -27,21 +27,8 @@
interrupt-parent = <&intc>;
};
scmi_sram: sram@2ffff000 {
compatible = "mmio-sram";
reg = <0x2ffff000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2ffff000 0x1000>;
scmi_shm: scmi_shm@0 {
compatible = "arm,scmi-shmem";
reg = <0 0x80>;
};
};
firmware {
optee: optee {
optee {
method = "smc";
compatible = "linaro,optee-tz";
};
@ -151,6 +138,19 @@
interrupt-parent = <&intc>;
ranges;
scmi_sram: sram@2ffff000 {
compatible = "mmio-sram";
reg = <0x2ffff000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2ffff000 0x1000>;
scmi_shm: scmi-sram@0 {
compatible = "arm,scmi-shmem";
reg = <0 0x80>;
};
};
uart4: serial@40010000 {
compatible = "st,stm32h7-uart";
reg = <0x40010000 0x400>;

4
arch/arm/dts/stm32mp135f-dk.dts
View file

@ -31,8 +31,8 @@
#size-cells = <1>;
ranges;
optee@de000000 {
reg = <0xde000000 0x2000000>;
optee@dd000000 {
reg = <0xdd000000 0x3000000>;
no-map;
};
};

16
arch/arm/dts/stm32mp15-ddr.dtsi
View file

@ -4,7 +4,22 @@
*/
#include <linux/stringify.h>
#ifdef CONFIG_SPL
&ddr {
clocks = <&rcc AXIDCG>,
<&rcc DDRC1>,
<&rcc DDRC2>,
<&rcc DDRPHYC>,
<&rcc DDRCAPB>,
<&rcc DDRPHYCAPB>;
clock-names = "axidcg",
"ddrc1",
"ddrc2",
"ddrphyc",
"ddrcapb",
"ddrphycapb";
config-DDR_MEM_COMPATIBLE {
u-boot,dm-pre-reloc;
@ -119,6 +134,7 @@
status = "okay";
};
};
#endif
#undef DDR_MEM_COMPATIBLE
#undef DDR_MEM_NAME

64
arch/arm/dts/stm32mp15-pinctrl.dtsi
View file

@ -151,6 +151,43 @@
};
};
dcmi_pins_c: dcmi-2 {
pins {
pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */
<STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
<STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
<STM32_PINMUX('A', 9, AF13)>,/* DCMI_D0 */
<STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
<STM32_PINMUX('E', 0, AF13)>,/* DCMI_D2 */
<STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */
<STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */
<STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */
<STM32_PINMUX('I', 6, AF13)>,/* DCMI_D6 */
<STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */
<STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
<STM32_PINMUX('H', 7, AF13)>;/* DCMI_D9 */
bias-pull-up;
};
};
dcmi_sleep_pins_c: dcmi-sleep-2 {
pins {
pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */
<STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
<STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
<STM32_PINMUX('A', 9, ANALOG)>,/* DCMI_D0 */
<STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
<STM32_PINMUX('E', 0, ANALOG)>,/* DCMI_D2 */
<STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */
<STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */
<STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */
<STM32_PINMUX('I', 6, ANALOG)>,/* DCMI_D6 */
<STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */
<STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */
<STM32_PINMUX('H', 7, ANALOG)>;/* DCMI_D9 */
};
};
ethernet0_rgmii_pins_a: rgmii-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
@ -923,6 +960,21 @@
};
};
mco1_pins_a: mco1-0 {
pins {
pinmux = <STM32_PINMUX('A', 13, AF2)>; /* MCO1 */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
};
mco1_sleep_pins_a: mco1-sleep-0 {
pins {
pinmux = <STM32_PINMUX('A', 13, ANALOG)>; /* MCO1 */
};
};
mco2_pins_a: mco2-0 {
pins {
pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */
@ -1814,30 +1866,30 @@
spi2_pins_a: spi2-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI1_SCK */
<STM32_PINMUX('I', 3, AF5)>; /* SPI1_MOSI */
pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */
<STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI1_MISO */
pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */
bias-disable;
};
};
spi2_pins_b: spi2-1 {
pins1 {
pinmux = <STM32_PINMUX('I', 1, AF5)>, /* SPI1_SCK */
<STM32_PINMUX('I', 3, AF5)>; /* SPI1_MOSI */
pinmux = <STM32_PINMUX('I', 1, AF5)>, /* SPI2_SCK */
<STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI1_MISO */
pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */
bias-disable;
};
};

14
arch/arm/dts/stm32mp15-u-boot.dtsi
View file

@ -53,20 +53,6 @@
reg = <0x5a003000 0x550
0x5a004000 0x234>;
clocks = <&rcc AXIDCG>,
<&rcc DDRC1>,
<&rcc DDRC2>,
<&rcc DDRPHYC>,
<&rcc DDRCAPB>,
<&rcc DDRPHYCAPB>;
clock-names = "axidcg",
"ddrc1",
"ddrc2",
"ddrphyc",
"ddrcapb",
"ddrphycapb";
status = "okay";
};
};

7
arch/arm/dts/stm32mp151.dtsi
View file

@ -1143,10 +1143,9 @@
reg = <0x4c001000 0x400>;
st,proc-id = <0>;
interrupts-extended =
<&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<&exti 61 1>;
interrupt-names = "rx", "tx", "wakeup";
<&exti 61 1>,
<&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "rx", "tx";
clocks = <&rcc IPCC>;
wakeup-source;
status = "disabled";

1
arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
View file

@ -5,7 +5,6 @@
#include <dt-bindings/clock/stm32mp1-clksrc.h>
#include "stm32mp15-scmi-u-boot.dtsi"
#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
/ {
aliases {

1
arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi
View file

@ -5,7 +5,6 @@
#include <dt-bindings/clock/stm32mp1-clksrc.h>
#include "stm32mp15-scmi-u-boot.dtsi"
#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
/ {
aliases {

8
arch/arm/dts/stm32mp15xx-dkx.dtsi
View file

@ -685,6 +685,14 @@
&usbh_ehci {
phys = <&usbphyc_port0>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
/* onboard HUB */
hub@1 {
compatible = "usb424,2514";
reg = <1>;
vdd-supply = <&v3v3>;
};
};
&usbotg_hs {

6
arch/arm/include/asm/arch-stm32f7/stm32.h
View file

@ -10,9 +10,9 @@
#include <asm/arch-stm32/stm32f.h>
static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
[0 ... 3] = 32 * 1024,
[4] = 128 * 1024,
[5 ... 7] = 256 * 1024
[0 ... 3] = 32 * 1024,
[4] = 128 * 1024,
[5 ... CONFIG_SYS_MAX_FLASH_SECT - 1] = 256 * 1024
};
#endif /* _ASM_ARCH_HARDWARE_H */

333
arch/arm/mach-stm32mp/cmd_stm32key.c
View file

@ -11,13 +11,81 @@
#include <dm/device.h>
#include <dm/uclass.h>
/* Closed device : bit 6 of OPT0*/
/*
* Closed device: OTP0
* STM32MP15x: bit 6 of OPT0
* STM32MP13x: 0b111111 = 0x3F for OTP_SECURED closed device
*/
#define STM32_OTP_CLOSE_ID 0
#define STM32_OTP_CLOSE_MASK BIT(6)
#define STM32_OTP_STM32MP13x_CLOSE_MASK 0x3F
#define STM32_OTP_STM32MP15x_CLOSE_MASK BIT(6)
/* HASH of key: 8 OTPs, starting with OTP24) */
#define STM32_OTP_HASH_KEY_START 24
#define STM32_OTP_HASH_KEY_SIZE 8
/* PKH is the first element of the key list */
#define STM32KEY_PKH 0
struct stm32key {
char *name;
char *desc;
u8 start;
u8 size;
};
const struct stm32key stm32mp13_list[] = {
[STM32KEY_PKH] = {
.name = "PKHTH",
.desc = "Hash of the 8 ECC Public Keys Hashes Table (ECDSA is the authentication algorithm)",
.start = 24,
.size = 8,
},
{
.name = "EDMK",
.desc = "Encryption/Decryption Master Key",
.start = 92,
.size = 4,
}
};
const struct stm32key stm32mp15_list[] = {
[STM32KEY_PKH] = {
.name = "PKH",
.desc = "Hash of the ECC Public Key (ECDSA is the authentication algorithm)",
.start = 24,
.size = 8,
}
};
/* index of current selected key in stm32key list, 0 = PKH by default */
static u8 stm32key_index;
static u8 get_key_nb(void)
{
if (IS_ENABLED(CONFIG_STM32MP13x))
return ARRAY_SIZE(stm32mp13_list);
if (IS_ENABLED(CONFIG_STM32MP15x))
return ARRAY_SIZE(stm32mp15_list);
}
static const struct stm32key *get_key(u8 index)
{
if (IS_ENABLED(CONFIG_STM32MP13x))
return &stm32mp13_list[index];
if (IS_ENABLED(CONFIG_STM32MP15x))
return &stm32mp15_list[index];
}
static u32 get_otp_close_mask(void)
{
if (IS_ENABLED(CONFIG_STM32MP13x))
return STM32_OTP_STM32MP13x_CLOSE_MASK;
if (IS_ENABLED(CONFIG_STM32MP15x))
return STM32_OTP_STM32MP15x_CLOSE_MASK;
}
#define BSEC_LOCK_ERROR (-1)
#define BSEC_LOCK_PERM BIT(0)
static int get_misc_dev(struct udevice **dev)
{
@ -30,108 +98,115 @@ static int get_misc_dev(struct udevice **dev)
return ret;
}
static void read_hash_value(u32 addr)
static void read_key_value(const struct stm32key *key, u32 addr)
{
int i;
printf("Read KEY at 0x%x\n", addr);
for (i = 0; i < STM32_OTP_HASH_KEY_SIZE; i++) {
printf("OTP value %i: %x\n", STM32_OTP_HASH_KEY_START + i,
__be32_to_cpu(*(u32 *)addr));
for (i = 0; i < key->size; i++) {
printf("%s OTP %i: [%08x] %08x\n", key->name, key->start + i,
addr, __be32_to_cpu(*(u32 *)addr));
addr += 4;
}
}
static int read_hash_otp(bool print, bool *locked, bool *closed)
static int read_key_otp(struct udevice *dev, const struct stm32key *key, bool print, bool *locked)
{
struct udevice *dev;
int i, word, ret;
int nb_invalid = 0, nb_zero = 0, nb_lock = 0;
int nb_invalid = 0, nb_zero = 0, nb_lock = 0, nb_lock_err = 0;
u32 val, lock;
bool status;
ret = get_misc_dev(&dev);
if (ret)
return ret;
for (i = 0, word = STM32_OTP_HASH_KEY_START; i < STM32_OTP_HASH_KEY_SIZE; i++, word++) {
for (i = 0, word = key->start; i < key->size; i++, word++) {
ret = misc_read(dev, STM32_BSEC_OTP(word), &val, 4);
if (ret != 4)
val = ~0x0;
ret = misc_read(dev, STM32_BSEC_LOCK(word), &lock, 4);
if (ret != 4)
lock = -1;
lock = BSEC_LOCK_ERROR;
if (print)
printf("OTP HASH %i: %x lock : %d\n", word, val, lock);
printf("%s OTP %i: %08x lock : %08x\n", key->name, word, val, lock);
if (val == ~0x0)
nb_invalid++;
else if (val == 0x0)
nb_zero++;
if (lock == 1)
if (lock & BSEC_LOCK_PERM)
nb_lock++;
if (lock & BSEC_LOCK_ERROR)
nb_lock_err++;
}
word = STM32_OTP_CLOSE_ID;
ret = misc_read(dev, STM32_BSEC_OTP(word), &val, 4);
if (ret != 4)
val = 0x0;
ret = misc_read(dev, STM32_BSEC_LOCK(word), &lock, 4);
if (ret != 4)
lock = -1;
status = (val & STM32_OTP_CLOSE_MASK) == STM32_OTP_CLOSE_MASK;
if (closed)
*closed = status;
if (print)
printf("OTP %d: closed status: %d lock : %d\n", word, status, lock);
status = (nb_lock == STM32_OTP_HASH_KEY_SIZE);
status = nb_lock_err || (nb_lock == key->size);
if (locked)
*locked = status;
if (!status && print)
printf("Hash of key is not locked!\n");
if (nb_lock_err && print)
printf("%s lock is invalid!\n", key->name);
else if (!status && print)
printf("%s is not locked!\n", key->name);
if (nb_invalid == STM32_OTP_HASH_KEY_SIZE) {
if (nb_invalid == key->size) {
if (print)
printf("Hash of key is invalid!\n");
printf("%s is invalid!\n", key->name);
return -EINVAL;
}
if (nb_zero == STM32_OTP_HASH_KEY_SIZE) {
if (nb_zero == key->size) {
if (print)
printf("Hash of key is free!\n");
printf("%s is free!\n", key->name);
return -ENOENT;
}
return 0;
}
static int fuse_hash_value(u32 addr, bool print)
static int read_close_status(struct udevice *dev, bool print, bool *closed)
{
int word, ret, result;
u32 val, lock, mask;
bool status;
result = 0;
word = STM32_OTP_CLOSE_ID;
ret = misc_read(dev, STM32_BSEC_OTP(word), &val, 4);
if (ret < 0)
result = ret;
if (ret != 4)
val = 0x0;
ret = misc_read(dev, STM32_BSEC_LOCK(word), &lock, 4);
if (ret < 0)
result = ret;
if (ret != 4)
lock = BSEC_LOCK_ERROR;
mask = get_otp_close_mask();
status = (val & mask) == mask;
if (closed)
*closed = status;
if (print)
printf("OTP %d: closed status: %d lock : %08x\n", word, status, lock);
return result;
}
static int fuse_key_value(struct udevice *dev, const struct stm32key *key, u32 addr, bool print)
{
struct udevice *dev;
u32 word, val;
int i, ret;
ret = get_misc_dev(&dev);
if (ret)
return ret;
for (i = 0, word = STM32_OTP_HASH_KEY_START;
i < STM32_OTP_HASH_KEY_SIZE;
i++, word++, addr += 4) {
for (i = 0, word = key->start; i < key->size; i++, word++, addr += 4) {
val = __be32_to_cpu(*(u32 *)addr);
if (print)
printf("Fuse OTP %i : %x\n", word, val);
printf("Fuse %s OTP %i : %08x\n", key->name, word, val);
ret = misc_write(dev, STM32_BSEC_OTP(word), &val, 4);
if (ret != 4) {
log_err("Fuse OTP %i failed\n", word);
log_err("Fuse %s OTP %i failed\n", key->name, word);
return ret;
}
/* on success, lock the OTP for HASH key */
val = 1;
/* on success, lock the OTP for the key */
val = BSEC_LOCK_PERM;
ret = misc_write(dev, STM32_BSEC_LOCK(word), &val, 4);
if (ret != 4) {
log_err("Lock OTP %i failed\n", word);
log_err("Lock %s OTP %i failed\n", key->name, word);
return ret;
}
}
@ -153,28 +228,103 @@ static int confirm_prog(void)
return 0;
}
static int do_stm32key_read(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
static void display_key_info(const struct stm32key *key)
{
u32 addr;
printf("%s : %s\n", key->name, key->desc);
printf("\tOTP%d..%d\n", key->start, key->start + key->size);
}
static int do_stm32key_list(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
int i;
for (i = 0; i < get_key_nb(); i++)
display_key_info(get_key(i));
return CMD_RET_SUCCESS;
}
static int do_stm32key_select(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
const struct stm32key *key;
int i;
if (argc == 1) {
read_hash_otp(true, NULL, NULL);
printf("Selected key:\n");
key = get_key(stm32key_index);
display_key_info(key);
return CMD_RET_SUCCESS;
}
for (i = 0; i < get_key_nb(); i++) {
key = get_key(i);
if (!strcmp(key->name, argv[1])) {
printf("%s selected\n", key->name);
stm32key_index = i;
return CMD_RET_SUCCESS;
}
}
printf("Unknown key %s\n", argv[1]);
return CMD_RET_FAILURE;
}
static int do_stm32key_read(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
const struct stm32key *key;
struct udevice *dev;
u32 addr;
int ret, i;
int result;
ret = get_misc_dev(&dev);
if (argc == 1) {
if (ret)
return CMD_RET_FAILURE;
key = get_key(stm32key_index);
ret = read_key_otp(dev, key, true, NULL);
if (ret != -ENOENT)
return CMD_RET_FAILURE;
return CMD_RET_SUCCESS;
}
if (!strcmp("-a", argv[1])) {
if (ret)
return CMD_RET_FAILURE;
result = CMD_RET_SUCCESS;
for (i = 0; i < get_key_nb(); i++) {
key = get_key(i);
ret = read_key_otp(dev, key, true, NULL);
if (ret != -ENOENT)
result = CMD_RET_FAILURE;
}
ret = read_close_status(dev, true, NULL);
if (ret)
result = CMD_RET_FAILURE;
return result;
}
addr = hextoul(argv[1], NULL);
if (!addr)
return CMD_RET_USAGE;
read_hash_value(addr);
key = get_key(stm32key_index);
printf("Read %s at 0x%08x\n", key->name, addr);
read_key_value(key, addr);
return CMD_RET_SUCCESS;
}
static int do_stm32key_fuse(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
const struct stm32key *key = get_key(stm32key_index);
struct udevice *dev;
u32 addr;
bool yes = false, lock, closed;
int ret;
bool yes = false, lock;
if (argc < 2)
return CMD_RET_USAGE;
@ -189,29 +339,38 @@ static int do_stm32key_fuse(struct cmd_tbl *cmdtp, int flag, int argc, char *con
if (!addr)
return CMD_RET_USAGE;
if (read_hash_otp(!yes, &lock, &closed) != -ENOENT) {
ret = get_misc_dev(&dev);
if (ret)
return CMD_RET_FAILURE;
if (read_key_otp(dev, key, !yes, &lock) != -ENOENT) {
printf("Error: can't fuse again the OTP\n");
return CMD_RET_FAILURE;
}
if (lock || closed) {
printf("Error: invalid OTP configuration (lock=%d, closed=%d)\n", lock, closed);
if (lock) {
printf("Error: %s is locked\n", key->name);
return CMD_RET_FAILURE;
}
if (!yes) {
printf("Writing %s with\n", key->name);
read_key_value(key, addr);
}
if (!yes && !confirm_prog())
return CMD_RET_FAILURE;
if (fuse_hash_value(addr, !yes))
if (fuse_key_value(dev, key, addr, !yes))
return CMD_RET_FAILURE;
printf("Hash key updated !\n");
printf("%s updated !\n", key->name);
return CMD_RET_SUCCESS;
}
static int do_stm32key_close(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
const struct stm32key *key;
bool yes, lock, closed;
struct udevice *dev;
u32 val;
@ -224,32 +383,36 @@ static int do_stm32key_close(struct cmd_tbl *cmdtp, int flag, int argc, char *co
yes = true;
}
ret = read_hash_otp(!yes, &lock, &closed);
if (ret) {
if (ret == -ENOENT)
printf("Error: OTP not programmed!\n");
ret = get_misc_dev(&dev);
if (ret)
return CMD_RET_FAILURE;
if (read_close_status(dev, !yes, &closed))
return CMD_RET_FAILURE;
}
if (closed) {
printf("Error: already closed!\n");
return CMD_RET_FAILURE;
}
/* check PKH status before to close */
key = get_key(STM32KEY_PKH);
ret = read_key_otp(dev, key, !yes, &lock);
if (ret) {
if (ret == -ENOENT)
printf("Error: %s not programmed!\n", key->name);
return CMD_RET_FAILURE;
}
if (!lock)
printf("Warning: OTP not locked!\n");
printf("Warning: %s not locked!\n", key->name);
if (!yes && !confirm_prog())
return CMD_RET_FAILURE;
ret = get_misc_dev(&dev);
if (ret)
return CMD_RET_FAILURE;
val = STM32_OTP_CLOSE_MASK;
val = get_otp_close_mask();
ret = misc_write(dev, STM32_BSEC_OTP(STM32_OTP_CLOSE_ID), &val, 4);
if (ret != 4) {
printf("Error: can't update OTP\n");
printf("Error: can't update OTP %d\n", STM32_OTP_CLOSE_ID);
return CMD_RET_FAILURE;
}
@ -259,11 +422,15 @@ static int do_stm32key_close(struct cmd_tbl *cmdtp, int flag, int argc, char *co
}
static char stm32key_help_text[] =
"read [<addr>]: Read the hash stored at addr in memory or in OTP\n"
"stm32key fuse [-y] <addr> : Fuse hash stored at addr in OTP\n"
"stm32key close [-y] : Close the device, the hash stored in OTP\n";
"list : list the supported key with description\n"
"stm32key select [<key>] : Select the key identified by <key> or display the key used for read/fuse command\n"
"stm32key read [<addr> | -a ] : Read the curent key at <addr> or current / all (-a) key in OTP\n"
"stm32key fuse [-y] <addr> : Fuse the current key at addr in OTP\n"
"stm32key close [-y] : Close the device\n";
U_BOOT_CMD_WITH_SUBCMDS(stm32key, "Fuse ST Hash key", stm32key_help_text,
U_BOOT_CMD_WITH_SUBCMDS(stm32key, "Manage key on STM32", stm32key_help_text,
U_BOOT_SUBCMD_MKENT(list, 1, 0, do_stm32key_list),
U_BOOT_SUBCMD_MKENT(select, 2, 0, do_stm32key_select),
U_BOOT_SUBCMD_MKENT(read, 2, 0, do_stm32key_read),
U_BOOT_SUBCMD_MKENT(fuse, 3, 0, do_stm32key_fuse),
U_BOOT_SUBCMD_MKENT(close, 2, 0, do_stm32key_close));

16
arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
View file

@ -61,7 +61,7 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, int argc,
dev = (int)dectoul(argv[2], NULL);
addr = STM32_DDR_BASE;
addr = CONFIG_SYS_LOAD_ADDR;
size = 0;
if (argc > 3) {
addr = hextoul(argv[3], NULL);
@ -126,21 +126,21 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, int argc,
char *bootm_argv[5] = {
"bootm", boot_addr_start, "-", dtb_addr, NULL
};
u32 uimage = data->uimage;
u32 dtb = data->dtb;
u32 initrd = data->initrd;
const void *uimage = (void *)data->uimage;
const void *dtb = (void *)data->dtb;
const void *initrd = (void *)data->initrd;
if (!dtb)
bootm_argv[3] = env_get("fdtcontroladdr");
else
snprintf(dtb_addr, sizeof(dtb_addr) - 1,
"0x%x", dtb);
"0x%p", dtb);
snprintf(boot_addr_start, sizeof(boot_addr_start) - 1,
"0x%x", uimage);
"0x%p", uimage);
if (initrd) {
snprintf(initrd_addr, sizeof(initrd_addr) - 1, "0x%x:0x%x",
snprintf(initrd_addr, sizeof(initrd_addr) - 1, "0x%p:0x%zx",
initrd, data->initrd_size);
bootm_argv[2] = initrd_addr;
}
@ -148,7 +148,7 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, int argc,
printf("Booting kernel at %s %s %s...\n\n\n",
boot_addr_start, bootm_argv[2], bootm_argv[3]);
/* Try bootm for legacy and FIT format image */
if (genimg_get_format((void *)uimage) != IMAGE_FORMAT_INVALID)
if (genimg_get_format(uimage) != IMAGE_FORMAT_INVALID)
do_bootm(cmdtp, 0, 4, bootm_argv);
else if (CONFIG_IS_ENABLED(CMD_BOOTZ))
do_bootz(cmdtp, 0, 4, bootm_argv);

57
arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
View file

@ -322,7 +322,7 @@ void stm32prog_header_check(uintptr_t raw_header, struct image_header_s *header)
header->image_length = 0x0;
}
static u32 stm32prog_header_checksum(u32 addr, struct image_header_s *header)
static u32 stm32prog_header_checksum(uintptr_t addr, struct image_header_s *header)
{
u32 i, checksum;
u8 *payload;
@ -398,7 +398,7 @@ static int parse_name(struct stm32prog_data *data,
if (strlen(p) < sizeof(part->name)) {
strcpy(part->name, p);
} else {
stm32prog_err("Layout line %d: partition name too long [%d]: %s",
stm32prog_err("Layout line %d: partition name too long [%zd]: %s",
i, strlen(p), p);
result = -EINVAL;
}
@ -537,7 +537,7 @@ int (* const parse[COL_NB_STM32])(struct stm32prog_data *data, int i, char *p,
};
static int parse_flash_layout(struct stm32prog_data *data,
ulong addr,
uintptr_t addr,
ulong size)
{
int column = 0, part_nb = 0, ret;
@ -1090,7 +1090,6 @@ static int create_gpt_partitions(struct stm32prog_data *data)
if (!buf)
return -ENOMEM;
puts("partitions : ");
/* initialize the selected device */
for (i = 0; i < data->dev_nb; i++) {
/* create gpt partition support only for full update on MMC */
@ -1098,6 +1097,7 @@ static int create_gpt_partitions(struct stm32prog_data *data)
!data->dev[i].full_update)
continue;
printf("partitions on mmc%d: ", data->dev[i].dev_id);
offset = 0;
rootfs_found = false;
memset(buf, 0, buflen);
@ -1197,8 +1197,8 @@ static int create_gpt_partitions(struct stm32prog_data *data)
sprintf(buf, "part list mmc %d", data->dev[i].dev_id);
run_command(buf, 0);
#endif
puts("done\n");
}
puts("done\n");
#ifdef DEBUG
run_command("mtd list", 0);
@ -1342,10 +1342,22 @@ static int dfu_init_entities(struct stm32prog_data *data)
struct stm32prog_part_t *part;
struct dfu_entity *dfu;
int alt_nb;
u32 otp_size = 0;
alt_nb = 1; /* number of virtual = CMD*/
if (IS_ENABLED(CONFIG_CMD_STM32PROG_OTP))
alt_nb++; /* OTP*/
if (IS_ENABLED(CONFIG_CMD_STM32PROG_OTP)) {
/* OTP_SIZE_SMC = 0 if SMC is not supported */
otp_size = OTP_SIZE_SMC;
/* check if PTA BSEC is supported */
ret = optee_ta_open(data);
log_debug("optee_ta_open(PTA_NVMEM) result %d\n", ret);
if (!ret && data->tee)
otp_size = OTP_SIZE_TA;
if (otp_size)
alt_nb++; /* OTP*/
}
if (CONFIG_IS_ENABLED(DM_PMIC))
alt_nb++; /* PMIC NVMEM*/
@ -1363,6 +1375,7 @@ static int dfu_init_entities(struct stm32prog_data *data)
puts("DFU alt info setting: ");
if (data->part_nb) {
alt_id = 0;
ret = 0;
for (phase = 1;
(phase <= PHASE_LAST_USER) &&
(alt_id < alt_nb) && !ret;
@ -1388,7 +1401,7 @@ static int dfu_init_entities(struct stm32prog_data *data)
char buf[ALT_BUF_LEN];
sprintf(buf, "@FlashLayout/0x%02x/1*256Ke ram %x 40000",
PHASE_FLASHLAYOUT, STM32_DDR_BASE);
PHASE_FLASHLAYOUT, CONFIG_SYS_LOAD_ADDR);
ret = dfu_alt_add(dfu, "ram", NULL, buf);
log_debug("dfu_alt_add(ram, NULL,%s) result %d\n", buf, ret);
}
@ -1396,12 +1409,8 @@ static int dfu_init_entities(struct stm32prog_data *data)
if (!ret)
ret = stm32prog_alt_add_virt(dfu, "virtual", PHASE_CMD, CMD_SIZE);
if (!ret && IS_ENABLED(CONFIG_CMD_STM32PROG_OTP)) {
ret = optee_ta_open(data);
log_debug("optee_ta result %d\n", ret);
ret = stm32prog_alt_add_virt(dfu, "OTP", PHASE_OTP,
data->tee ? OTP_SIZE_TA : OTP_SIZE_SMC);
}
if (!ret && IS_ENABLED(CONFIG_CMD_STM32PROG_OTP) && otp_size)
ret = stm32prog_alt_add_virt(dfu, "OTP", PHASE_OTP, otp_size);
if (!ret && CONFIG_IS_ENABLED(DM_PMIC))
ret = stm32prog_alt_add_virt(dfu, "PMIC", PHASE_PMIC, PMIC_SIZE);
@ -1440,7 +1449,7 @@ int stm32prog_otp_write(struct stm32prog_data *data, u32 offset, u8 *buffer,
if (offset + *size > otp_size)
*size = otp_size - offset;
memcpy((void *)((u32)data->otp_part + offset), buffer, *size);
memcpy((void *)((uintptr_t)data->otp_part + offset), buffer, *size);
return 0;
}
@ -1479,7 +1488,7 @@ int stm32prog_otp_read(struct stm32prog_data *data, u32 offset, u8 *buffer,
data->otp_part, OTP_SIZE_TA);
else if (IS_ENABLED(CONFIG_ARM_SMCCC))
result = stm32_smc_exec(STM32_SMC_BSEC, STM32_SMC_READ_ALL,
(u32)data->otp_part, 0);
(unsigned long)data->otp_part, 0);
if (result)
goto end_otp_read;
}
@ -1491,7 +1500,7 @@ int stm32prog_otp_read(struct stm32prog_data *data, u32 offset, u8 *buffer,
if (offset + *size > otp_size)
*size = otp_size - offset;
memcpy(buffer, (void *)((u32)data->otp_part + offset), *size);
memcpy(buffer, (void *)((uintptr_t)data->otp_part + offset), *size);
end_otp_read:
log_debug("%s: result %i\n", __func__, result);
@ -1521,7 +1530,7 @@ int stm32prog_otp_start(struct stm32prog_data *data)
data->otp_part, OTP_SIZE_TA);
} else if (IS_ENABLED(CONFIG_ARM_SMCCC)) {
arm_smccc_smc(STM32_SMC_BSEC, STM32_SMC_WRITE_ALL,
(u32)data->otp_part, 0, 0, 0, 0, 0, &res);
(uintptr_t)data->otp_part, 0, 0, 0, 0, 0, &res);
if (!res.a0) {
switch (res.a1) {
@ -1699,15 +1708,15 @@ static void stm32prog_end_phase(struct stm32prog_data *data, u64 offset)
{
if (data->phase == PHASE_FLASHLAYOUT) {
#if defined(CONFIG_LEGACY_IMAGE_FORMAT)
if (genimg_get_format((void *)STM32_DDR_BASE) == IMAGE_FORMAT_LEGACY) {
data->script = STM32_DDR_BASE;
if (genimg_get_format((void *)CONFIG_SYS_LOAD_ADDR) == IMAGE_FORMAT_LEGACY) {
data->script = CONFIG_SYS_LOAD_ADDR;
data->phase = PHASE_END;
log_notice("U-Boot script received\n");
return;
}
#endif
log_notice("\nFlashLayout received, size = %lld\n", offset);
if (parse_flash_layout(data, STM32_DDR_BASE, offset))
if (parse_flash_layout(data, CONFIG_SYS_LOAD_ADDR, offset))
stm32prog_err("Layout: invalid FlashLayout");
return;
}
@ -1884,6 +1893,10 @@ static void stm32prog_devices_init(struct stm32prog_data *data)
if (ret)
goto error;
/* empty flashlayout */
if (!data->dev_nb)
return;
/* initialize the selected device */
for (i = 0; i < data->dev_nb; i++) {
ret = init_device(data, &data->dev[i]);
@ -1947,7 +1960,7 @@ int stm32prog_dfu_init(struct stm32prog_data *data)
return dfu_init_entities(data);
}
int stm32prog_init(struct stm32prog_data *data, ulong addr, ulong size)
int stm32prog_init(struct stm32prog_data *data, uintptr_t addr, ulong size)
{
memset(data, 0x0, sizeof(*data));
data->read_phase = PHASE_RESET;

19
arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h
View file

@ -20,7 +20,12 @@
#define DEFAULT_ADDRESS 0xFFFFFFFF
#define CMD_SIZE 512
/* SMC is only supported in SPMIN for STM32MP15x */
#ifdef CONFIG_STM32MP15x
#define OTP_SIZE_SMC 1024
#else
#define OTP_SIZE_SMC 0
#endif
#define OTP_SIZE_TA 776
#define PMIC_SIZE 8
@ -154,7 +159,7 @@ struct stm32prog_data {
u32 offset;
char error[255];
struct stm32prog_part_t *cur_part;
u32 *otp_part;
void *otp_part;
u8 pmic_part[PMIC_SIZE];
/* SERIAL information */
@ -165,12 +170,12 @@ struct stm32prog_data {
u8 read_phase;
/* bootm information */
u32 uimage;
u32 dtb;
u32 initrd;
u32 initrd_size;
uintptr_t uimage;
uintptr_t dtb;
uintptr_t initrd;
size_t initrd_size;
u32 script;
uintptr_t script;
/* OPTEE PTA NVMEM */
struct udevice *tee;
@ -209,7 +214,7 @@ char *stm32prog_get_error(struct stm32prog_data *data);
}
/* Main function */
int stm32prog_init(struct stm32prog_data *data, ulong addr, ulong size);
int stm32prog_init(struct stm32prog_data *data, uintptr_t addr, ulong size);
void stm32prog_clean(struct stm32prog_data *data);
#ifdef CONFIG_CMD_STM32PROG_SERIAL

17
arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c
View file

@ -300,7 +300,7 @@ static void stm32prog_serial_putc(u8 w_byte)
}
/* Helper function ************************************************/
static u8 stm32prog_start(struct stm32prog_data *data, u32 address)
static u8 stm32prog_start(struct stm32prog_data *data, uintptr_t address)
{
u8 ret = 0;
struct dfu_entity *dfu_entity;
@ -353,7 +353,7 @@ static u8 stm32prog_start(struct stm32prog_data *data, u32 address)
} else {
void (*entry)(void) = (void *)address;
printf("## Starting application at 0x%x ...\n", address);
printf("## Starting application at 0x%p ...\n", (void *)address);
(*entry)();
printf("## Application terminated\n");
ret = -ENOEXEC;
@ -368,9 +368,9 @@ static u8 stm32prog_start(struct stm32prog_data *data, u32 address)
* @tmp_xor: Current xor value to update
* Return: The address area
*/
static u32 get_address(u8 *tmp_xor)
static uintptr_t get_address(u8 *tmp_xor)
{
u32 address = 0x0;
uintptr_t address = 0x0;
u8 data;
data = stm32prog_serial_getc();
@ -462,7 +462,7 @@ static void get_phase_command(struct stm32prog_data *data)
length = strlen(err_msg);
}
if (phase == PHASE_FLASHLAYOUT)
destination = STM32_DDR_BASE;
destination = CONFIG_SYS_LOAD_ADDR;
stm32prog_serial_putc(length + 5); /* Total length */
stm32prog_serial_putc(phase & 0xFF); /* partition ID */
@ -487,7 +487,7 @@ static void get_phase_command(struct stm32prog_data *data)
*/
static void read_memory_command(struct stm32prog_data *data)
{
u32 address = 0x0;
uintptr_t address = 0x0;
u8 rcv_data = 0x0, tmp_xor = 0x0;
u32 counter = 0x0;
@ -532,7 +532,7 @@ static void read_memory_command(struct stm32prog_data *data)
*/
static void start_command(struct stm32prog_data *data)
{
u32 address = 0;
uintptr_t address = 0;
u8 tmp_xor = 0x0;
u8 ret, rcv_data;
@ -546,8 +546,7 @@ static void start_command(struct stm32prog_data *data)
return;
}
/* validate partition */
ret = stm32prog_start(data,
address);
ret = stm32prog_start(data, address);
if (ret)
stm32prog_serial_result(ABORT_BYTE);

6
arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c
View file

@ -41,7 +41,7 @@ static int stm32prog_set_phase(struct stm32prog_data *data, u8 phase,
static int stm32prog_cmd_write(u64 offset, void *buf, long *len)
{
u8 phase;
u32 address;
uintptr_t address;
u8 *pt = buf;
void (*entry)(void);
int ret;
@ -58,7 +58,7 @@ static int stm32prog_cmd_write(u64 offset, void *buf, long *len)
address = (pt[1] << 24) | (pt[2] << 16) | (pt[3] << 8) | pt[4];
if (phase == PHASE_RESET) {
entry = (void *)address;
printf("## Starting application at 0x%x ...\n", address);
printf("## Starting application at 0x%p ...\n", entry);
(*entry)();
printf("## Application terminated\n");
return 0;
@ -90,7 +90,7 @@ static int stm32prog_cmd_read(u64 offset, void *buf, long *len)
}
phase = stm32prog_data->phase;
if (phase == PHASE_FLASHLAYOUT)
destination = STM32_DDR_BASE;
destination = CONFIG_SYS_LOAD_ADDR;
dfu_offset = stm32prog_data->offset;
/* mandatory header, size = PHASE_MIN_SIZE */

4
board/st/stm32mp1/stm32mp1.c
View file

@ -898,8 +898,8 @@ int mmc_get_env_dev(void)
int ft_board_setup(void *blob, struct bd_info *bd)
{
static const struct node_info nodes[] = {
{ "st,stm32f469-qspi", MTD_DEV_TYPE_NOR, },
{ "st,stm32f469-qspi", MTD_DEV_TYPE_SPINAND},
{ "jedec,spi-nor", MTD_DEV_TYPE_NOR, },
{ "spi-nand", MTD_DEV_TYPE_SPINAND},
{ "st,stm32mp15-fmc2", MTD_DEV_TYPE_NAND, },
{ "st,stm32mp1-fmc2-nfc", MTD_DEV_TYPE_NAND, },
};

1
configs/stm32746g-eval_defconfig
View file

@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_ARCH_STM32=y
CONFIG_SYS_TEXT_BASE=0x08000000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SYS_MALLOC_F_LEN=0xE00
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="stm32746g-eval"

10
configs/stm32746g-eval_spl_defconfig
View file

@ -1,8 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_STM32=y
CONFIG_SYS_TEXT_BASE=0x08008000
CONFIG_SYS_TEXT_BASE=0x08009000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SYS_MALLOC_F_LEN=0xE00
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
@ -13,10 +12,11 @@ CONFIG_SPL_TEXT_BASE=0x8000000
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_SIZE_LIMIT=0x9000
CONFIG_STM32F7=y
CONFIG_TARGET_STM32F746_DISCO=y
CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x8008000
CONFIG_SYS_LOAD_ADDR=0x8009000
CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
@ -29,13 +29,13 @@ CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_PAD_TO=0x8000
CONFIG_SPL_PAD_TO=0x9000
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_XIP_SUPPORT=y
CONFIG_SYS_SPL_ARGS_ADDR=0x81c0000
CONFIG_SYS_SPL_ARGS_ADDR=0x80c0000
CONFIG_SPL_DM_RESET=y
CONFIG_SYS_PBSIZE=1050
CONFIG_CMD_GPT=y

1
configs/stm32f429-discovery_defconfig
View file

@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_ARCH_STM32=y
CONFIG_SYS_TEXT_BASE=0x08000000
CONFIG_SYS_MALLOC_LEN=0x0200000
CONFIG_SYS_MALLOC_F_LEN=0xF00
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000

1
configs/stm32f429-evaluation_defconfig
View file

@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_ARCH_STM32=y
CONFIG_SYS_TEXT_BASE=0x08000000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SYS_MALLOC_F_LEN=0xF00
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="stm32429i-eval"

1
configs/stm32f469-discovery_defconfig
View file

@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_ARCH_STM32=y
CONFIG_SYS_TEXT_BASE=0x08000000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SYS_MALLOC_F_LEN=0xF00
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="stm32f469-disco"

1
configs/stm32f746-disco_defconfig
View file

@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_ARCH_STM32=y
CONFIG_SYS_TEXT_BASE=0x08000000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SYS_MALLOC_F_LEN=0xE00
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="stm32f746-disco"

10
configs/stm32f746-disco_spl_defconfig
View file

@ -1,8 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_STM32=y
CONFIG_SYS_TEXT_BASE=0x08008000
CONFIG_SYS_TEXT_BASE=0x08009000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SYS_MALLOC_F_LEN=0xE00
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
@ -13,10 +12,11 @@ CONFIG_SPL_TEXT_BASE=0x8000000
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_SIZE_LIMIT=0x9000
CONFIG_STM32F7=y
CONFIG_TARGET_STM32F746_DISCO=y
CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x8008000
CONFIG_SYS_LOAD_ADDR=0x8009000
CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
@ -29,13 +29,13 @@ CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_PAD_TO=0x8000
CONFIG_SPL_PAD_TO=0x9000
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_XIP_SUPPORT=y
CONFIG_SYS_SPL_ARGS_ADDR=0x81c0000
CONFIG_SYS_SPL_ARGS_ADDR=0x80c0000
CONFIG_SPL_DM_RESET=y
CONFIG_SYS_PBSIZE=1050
CONFIG_CMD_GPT=y

3
configs/stm32f769-disco_defconfig
View file

@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_ARCH_STM32=y
CONFIG_SYS_TEXT_BASE=0x08000000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SYS_MALLOC_F_LEN=0xE00
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="stm32f769-disco"
@ -41,7 +40,7 @@ CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_STM32_FLASH=y
CONFIG_SYS_MAX_FLASH_SECT=8
CONFIG_SYS_MAX_FLASH_SECT=12
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y

10
configs/stm32f769-disco_spl_defconfig
View file

@ -1,8 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_STM32=y
CONFIG_SYS_TEXT_BASE=0x08008000
CONFIG_SYS_TEXT_BASE=0x08009000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SYS_MALLOC_F_LEN=0xE00
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
@ -13,10 +12,11 @@ CONFIG_SPL_TEXT_BASE=0x8000000
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_SIZE_LIMIT=0x9000
CONFIG_STM32F7=y
CONFIG_TARGET_STM32F746_DISCO=y
CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x8008000
CONFIG_SYS_LOAD_ADDR=0x8009000
CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
@ -28,7 +28,7 @@ CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_PAD_TO=0x8000
CONFIG_SPL_PAD_TO=0x9000
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
@ -62,7 +62,7 @@ CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_STM32_FLASH=y
CONFIG_SYS_MAX_FLASH_SECT=8
CONFIG_SYS_MAX_FLASH_SECT=12
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y

1
configs/stm32h743-disco_defconfig
View file

@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_ARCH_STM32=y
CONFIG_SYS_TEXT_BASE=0x08000000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SYS_MALLOC_F_LEN=0xF00
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="stm32h743i-disco"

1
configs/stm32h743-eval_defconfig
View file

@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_ARCH_STM32=y
CONFIG_SYS_TEXT_BASE=0x08000000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SYS_MALLOC_F_LEN=0xF00
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="stm32h743i-eval"

1
configs/stm32h750-art-pi_defconfig
View file

@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_ARCH_STM32=y
CONFIG_SYS_TEXT_BASE=0x90000000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SYS_MALLOC_F_LEN=0xF00
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="stm32h750i-art-pi"

1
include/configs/stm32f746-disco.h
View file

@ -34,7 +34,6 @@
BOOTENV
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_UBOOT_START 0x080083FD
#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \
CONFIG_SPL_PAD_TO)

2
include/configs/stm32mp13_common.h
View file

@ -21,8 +21,6 @@
*/
#define CONFIG_SYS_BOOTMAPSZ SZ_256M
/* Extend size of kernel image for uncompression */
/*MMC SD*/
#define CONFIG_SYS_MMC_MAX_DEVICE 2

2
include/configs/stm32mp15_common.h
View file

@ -21,8 +21,6 @@
*/
#define CONFIG_SYS_BOOTMAPSZ SZ_256M
/* Extend size of kernel image for uncompression */
/*MMC SD*/
#define CONFIG_SYS_MMC_MAX_DEVICE 3