mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
ARM: dts: npcm7xx: add npcm750 full function node
add npcm750 BMC full function node Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
This commit is contained in:
Jim Liu
Tom Rini
parent
689525b12e
commit
88513fe584
4 changed files with 343 additions and 11 deletions
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@ -559,6 +559,9 @@
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#size-cells = <1>;
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compatible = "nuvoton,npcm750-pinctrl", "syscon", "simple-mfd";
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ranges = <0 0xf0010000 0x8000>;
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reg = <0xf0010000 0x8000>;
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syscon-gcr = <&gcr>;
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syscon-rst = <&rst>;
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gpio0: gpio@f0010000 {
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gpio-controller;
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#gpio-cells = <2>;
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@ -12,8 +12,8 @@
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compatible = "nuvoton,npcm750-evb", "nuvoton,npcm750";
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aliases {
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ethernet2 = &gmac0;
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ethernet3 = &gmac1;
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eth0 = &emc0;
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eth1 = &gmac0;
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serial0 = &serial0;
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serial1 = &serial1;
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serial2 = &serial2;
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@ -34,11 +34,11 @@
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i2c13 = &i2c13;
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i2c14 = &i2c14;
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i2c15 = &i2c15;
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spi0 = &spi0;
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spi1 = &spi1;
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fiu0 = &fiu0;
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fiu1 = &fiu3;
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fiu2 = &fiux;
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spi0 = &fiu0;
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spi1 = &fiu3;
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spi2 = &fiux;
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spi3 = &spi0;
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spi4 = &spi1;
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};
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chosen {
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@ -51,18 +51,20 @@
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};
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};
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&gmac0 {
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phy-mode = "rgmii-id";
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&udc0 {
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status = "okay";
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phys = <&usbphy1 0>;
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};
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&gmac1 {
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&gmac0 {
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phy-mode = "rgmii-id";
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snps,eee-force-disable;
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status = "okay";
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};
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&ehci1 {
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status = "okay";
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phys = <&usbphy2 3>;
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};
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&fiu0 {
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@ -151,7 +153,7 @@
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spix-mode;
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};
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&watchdog1 {
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&watchdog0 {
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status = "okay";
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};
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@ -159,6 +161,14 @@
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status = "okay";
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};
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&sha {
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status = "okay";
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};
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&aes {
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status = "okay";
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};
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&serial0 {
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status = "okay";
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clock-frequency = <24000000>;
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@ -403,3 +413,34 @@
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&pin255_input>;
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};
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&ehci1 {
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status = "okay";
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phys = <&usbphy2 3>;
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};
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&otp {
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status = "okay";
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};
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&usbphy1 {
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status = "okay";
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};
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&usbphy2 {
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status = "okay";
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};
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&emc0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&r1_pins
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&r1err_pins>;
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fixed-link {
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speed = <100>;
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full-dulpex;
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};
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};
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&sdhci0 {
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status = "okay";
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};
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@ -3,6 +3,7 @@
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// Copyright 2018 Google, Inc.
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#include "nuvoton-common-npcm7xx.dtsi"
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#include "nuvoton-npcm7xx-u-boot.dtsi"
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/ {
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#address-cells = <1>;
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287
arch/arm/dts/nuvoton-npcm7xx-u-boot.dtsi
Normal file
287
arch/arm/dts/nuvoton-npcm7xx-u-boot.dtsi
Normal file
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@ -0,0 +1,287 @@
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// SPDX-License-Identifier: GPL-2.0
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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wdt-reboot {
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compatible = "wdt-reboot";
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wdt = <&watchdog0>;
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};
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ahb {
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udc0:udc@f0830100 {
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compatible = "nuvoton,npcm750-udc";
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reg = <0xf0830100 0x200
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0xfffd0000 0x800>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rstc NPCM7XX_RESET_IPSRST3 NPCM7XX_RESET_UDC0>;
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status = "disabled";
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clocks = <&clk NPCM7XX_CLK_SU>;
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clock-names = "clk_usb_bridge";
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};
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udc1:udc@f0831100 {
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compatible = "nuvoton,npcm750-udc";
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reg = <0xf0831100 0x200
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0xfffd0800 0x800>;
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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clocks = <&clk NPCM7XX_CLK_SU>;
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clock-names = "clk_usb_bridge";
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};
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udc2: udc@f0832100 {
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compatible = "nuvoton,npcm750-udc";
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reg = <0xf0832100 0x200
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0xfffd1000 0x800>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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clocks = <&clk NPCM7XX_CLK_SU>;
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clock-names = "clk_usb_bridge";
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};
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udc3: udc@f0833100 {
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compatible = "nuvoton,npcm750-udc";
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reg = <0xf0833100 0x200
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0xfffd1800 0x800>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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clocks = <&clk NPCM7XX_CLK_SU>;
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clock-names = "clk_usb_bridge";
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};
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udc4: udc@f0834100 {
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compatible = "nuvoton,npcm750-udc";
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reg = <0xf0834100 0x200
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0xfffd2000 0x800>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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clocks = <&clk NPCM7XX_CLK_SU>;
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clock-names = "clk_usb_bridge";
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};
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udc5: udc@f0835100 {
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compatible = "nuvoton,npcm750-udc";
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reg = <0xf0835100 0x200
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0xfffd2800 0x800>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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clocks = <&clk NPCM7XX_CLK_SU>;
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clock-names = "clk_usb_bridge";
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};
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udc6: udc@f0836100 {
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compatible = "nuvoton,npcm750-udc";
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reg = <0xf0836100 0x200
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0xfffd3000 0x800>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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clocks = <&clk NPCM7XX_CLK_SU>;
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clock-names = "clk_usb_bridge";
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};
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udc7: udc@f0837100 {
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compatible = "nuvoton,npcm750-udc";
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reg = <0xf0837100 0x200
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0xfffd3800 0x800>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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clocks = <&clk NPCM7XX_CLK_SU>;
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clock-names = "clk_usb_bridge";
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};
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udc8: udc@f0838100 {
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compatible = "nuvoton,npcm750-udc";
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reg = <0xf0838100 0x200
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0xfffd4000 0x800>;
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interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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clocks = <&clk NPCM7XX_CLK_SU>;
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clock-names = "clk_usb_bridge";
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};
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udc9: udc@f0839100 {
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compatible = "nuvoton,npcm750-udc";
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reg = <0xf0839100 0x200
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0xfffd4800 0x800>;
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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clocks = <&clk NPCM7XX_CLK_SU>;
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clock-names = "clk_usb_bridge";
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};
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emc0: eth@f0825000 {
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device_type = "network";
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compatible = "nuvoton,npcm750-emc";
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reg = <0xf0825000 0x1000>;
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phy-mode = "rmii";
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id = <0>;
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syscon-gcr = <&gcr>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk NPCM7XX_CLK_AHB>;
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clock-names = "clk_emc";
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resets = <&rstc NPCM7XX_RESET_IPSRST1 NPCM7XX_RESET_EMC1>;
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pinctrl-names = "default";
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pinctrl-0 = <&r1_pins
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&r1md_pins>;
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status = "disabled";
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};
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ohci1: ohci@f0807000 {
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compatible = "nuvoton,npcm750-ohci";
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reg = <0xf0807000 0x1000>;
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_USB_HOST>;
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status = "disabled";
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};
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usbphy {
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compatible = "simple-bus", "nuvoton,npcm750-usb-phy";
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#address-cells = <1>;
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#size-cells = <0>;
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syscon = <&gcr>;
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usbphy1: usbphy1 {
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compatible = "nuvoton,npcm750-usb-phy";
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#phy-cells = <1>;
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reg = <1>;
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resets = <&rstc NPCM7XX_RESET_IPSRST3 NPCM7XX_RESET_USB_PHY_1>;
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status = "disabled";
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};
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usbphy2: usbphy2 {
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compatible = "nuvoton,npcm750-usb-phy";
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#phy-cells = <1>;
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reg = <2>;
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resets =<&rstc NPCM7XX_RESET_IPSRST3 NPCM7XX_RESET_USB_PHY_2>;
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status = "disabled";
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};
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};
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sdhci0: sdhci0@f0842000 {
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compatible = "nuvoton,npcm750-sdhci";
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reg = <0xf0842000 0x200>;
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index = <0x0>;
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bus-width = <0x8>;
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cap-mmc-highspeed;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk NPCM7XX_CLK_SDHC>;
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clock-frequency = <50000000>;
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pinctrl-names = "default";
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pinctrl-0 = <&mmc_pins
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&mmc8_pins>;
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status = "disabled";
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};
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sdhci1: sdhci1@f0840000 {
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compatible = "nuvoton,npcm750-sdhci";
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reg = <0xf0840000 0x2000>;
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index = <0x1>;
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bus-width = <0x4>;
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cap-mmc-highspeed;
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pinctrl-names = "default";
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pinctrl-0 = <&sd1_pins>;
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status = "disabled";
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};
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aes: aes@f0858000 {
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compatible = "nuvoton,npcm750-aes";
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reg = <0xf0858000 0x1000>;
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clocks = <&clk NPCM7XX_CLK_AHB>;
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clock-names = "clk_ahb";
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status = "disabled";
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};
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sha: sha@f085a000 {
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compatible = "nuvoton,npcm750-sha";
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reg = <0xf085a000 0x1000>;
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clocks = <&clk NPCM7XX_CLK_AHB>;
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clock-names = "clk_ahb";
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status = "disabled";
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};
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//ehci1
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usb@f0806000 {
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resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_USB_HOST>;
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};
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apb {
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otp:otp@189000 {
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compatible = "nuvoton,npcm750-otp";
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reg = <0x189000 0x1000
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0x18a000 0x1000>;
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status = "disabled";
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clocks = <&clk NPCM7XX_CLK_APB4>;
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clock-names = "clk_apb4";
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};
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rng@b000 {
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clocks = <&clk NPCM7XX_CLK_APB1>;
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};
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gpio_0: gpio0@10000 {
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compatible = "nuvoton,npcm-gpio";
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reg = <0x10000 0xB0>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-bank-name = "gpio0";
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};
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gpio_1: gpio1@11000 {
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compatible = "nuvoton,npcm-gpio";
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reg = <0x11000 0xB0>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-bank-name = "gpio1";
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};
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gpio_2: gpio2@12000 {
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compatible = "nuvoton,npcm-gpio";
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reg = <0x12000 0xB0>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-bank-name = "gpio2";
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};
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gpio_3: gpio3@13000 {
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compatible = "nuvoton,npcm-gpio";
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reg = <0x13000 0xB0>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-bank-name = "gpio3";
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};
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gpio_4: gpio4@14000 {
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compatible = "nuvoton,npcm-gpio";
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reg = <0x14000 0xB0>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-bank-name = "gpio4";
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};
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gpio_5: gpio5@15000 {
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compatible = "nuvoton,npcm-gpio";
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reg = <0x15000 0xB0>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-bank-name = "gpio5";
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};
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gpio_6: gpio6@16000 {
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compatible = "nuvoton,npcm-gpio";
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reg = <0x16000 0xB0>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-bank-name = "gpio6";
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};
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gpio_7: gpio7@17000 {
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compatible = "nuvoton,npcm-gpio";
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reg = <0x17000 0xB0>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-bank-name = "gpio7";
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};
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};
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};
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};
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