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https://github.com/AsahiLinux/u-boot
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video: Drop CONFIG_AM335X_LCD
This relies on the old LCD implementation which is to be removed. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass
Anatolij Gustschin
parent
0852d58361
commit
82f7b869f5
13 changed files with 0 additions and 1135 deletions
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@ -227,10 +227,6 @@ void enable_basic_clocks(void)
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&cmper->usb0clkctrl,
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&cmper->emiffwclkctrl,
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&cmper->emifclkctrl,
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#if CONFIG_IS_ENABLED(AM335X_LCD) && !CONFIG_IS_ENABLED(DM_VIDEO)
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&cmper->lcdclkctrl,
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&cmper->lcdcclkstctrl,
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#endif
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0
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};
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@ -254,74 +254,6 @@ void lcdbacklight_en(void)
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brightness != 0 ? 0x0A : 0x02, 0xFF);
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}
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#if IS_ENABLED(CONFIG_AM335X_LCD)
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static void splash_screen(void)
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{
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struct udevice *video_dev;
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struct udevice *console_dev;
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struct video_priv *vid_priv;
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struct mtd_info *mtd;
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size_t len;
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int ret;
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struct mtd_device *mtd_dev;
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struct part_info *part;
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u8 pnum;
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ret = uclass_get_device(UCLASS_VIDEO, 0, &video_dev);
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if (ret != 0) {
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debug("video device not found\n");
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goto exit;
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}
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vid_priv = dev_get_uclass_priv(video_dev);
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mtdparts_init();
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if (find_dev_and_part(SPLASH_SCREEN_NAND_PART, &mtd_dev, &pnum, &part)) {
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debug("Could not find nand partition\n");
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goto splash_screen_text;
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}
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mtd = get_nand_dev_by_index(mtd_dev->id->num);
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if (!mtd) {
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debug("MTD partition is not valid\n");
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goto splash_screen_text;
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}
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len = SPLASH_SCREEN_BMP_FILE_SIZE;
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ret = nand_read_skip_bad(mtd, part->offset, &len, NULL,
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SPLASH_SCREEN_BMP_FILE_SIZE,
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(u_char *)SPLASH_SCREEN_BMP_LOAD_ADDR);
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if (ret != 0) {
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debug("Reading NAND partition failed\n");
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goto splash_screen_text;
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}
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ret = video_bmp_display(video_dev, SPLASH_SCREEN_BMP_LOAD_ADDR, 0, 0, false);
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if (ret != 0) {
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debug("No valid bmp image found!!\n");
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goto splash_screen_text;
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} else {
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goto exit;
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}
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splash_screen_text:
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vid_priv->colour_fg = CONSOLE_COLOR_RED;
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vid_priv->colour_bg = CONSOLE_COLOR_BLACK;
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if (!uclass_first_device_err(UCLASS_VIDEO_CONSOLE, &console_dev)) {
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debug("Found console\n");
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vidconsole_position_cursor(console_dev, 17, 7);
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vidconsole_put_string(console_dev, SPLASH_SCREEN_TEXT);
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} else {
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debug("No console device found\n");
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}
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exit:
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return;
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}
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#endif /* CONFIG_AM335X_LCD */
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int board_late_init(void)
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{
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int ret;
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@ -340,8 +272,6 @@ int board_late_init(void)
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return 0;
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lcdbacklight_en();
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if (IS_ENABLED(CONFIG_AM335X_LCD))
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splash_screen();
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return 0;
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}
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@ -131,7 +131,6 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0451
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CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
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CONFIG_USB_ETHER=y
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CONFIG_SYS_WHITE_ON_BLACK=y
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CONFIG_AM335X_LCD=y
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CONFIG_BMP_16BPP=y
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CONFIG_SPL_WDT=y
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# CONFIG_SPL_USE_TINY_PRINTF is not set
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@ -588,8 +588,6 @@ config ATMEL_HLCD
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help
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HLCDC supports video output to an attached LCD panel.
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source "drivers/video/ti/Kconfig"
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source "drivers/video/exynos/Kconfig"
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config LOGICORE_DP_TX
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@ -26,7 +26,6 @@ obj-${CONFIG_EXYNOS_FB} += exynos/
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obj-${CONFIG_VIDEO_ROCKCHIP} += rockchip/
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obj-${CONFIG_VIDEO_STM32} += stm32/
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obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
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obj-y += ti/
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obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o
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obj-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o
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@ -1,8 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
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#
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config AM335X_LCD
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bool "Enable AM335x video support"
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help
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Supports video output to an attached LCD panel.
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@ -1,10 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
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#
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ifdef CONFIG_DM_VIDEO
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obj-$(CONFIG_AM335X_LCD) += tilcdc.o tilcdc-panel.o
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else
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obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
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endif
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@ -1,318 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2013-2018 Hannes Schmelzer <oe5hpm@oevsv.at>
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* B&R Industrial Automation GmbH - http://www.br-automation.com
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* Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
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*
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* minimal framebuffer driver for TI's AM335x SoC to be compatible with
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* Wolfgang Denk's LCD-Framework (CONFIG_LCD, common/lcd.c)
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*
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* - supporting 16/24/32bit RGB/TFT raster Mode (not using palette)
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* - sets up LCD controller as in 'am335x_lcdpanel' struct given
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* - starts output DMA from gd->fb_base buffer
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*/
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#include <common.h>
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#include <lcd.h>
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#include <log.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include "am335x-fb.h"
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#define LCDC_FMAX 200000000
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/* LCD Control Register */
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#define LCDC_CTRL_CLK_DIVISOR_MASK GENMASK(15, 8)
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#define LCDC_CTRL_RASTER_MODE BIT(0)
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#define LCDC_CTRL_CLK_DIVISOR(x) (((x) & GENMASK(7, 0)) << 8)
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/* LCD Clock Enable Register */
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#define LCDC_CLKC_ENABLE_CORECLKEN BIT(0)
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#define LCDC_CLKC_ENABLE_LIDDCLKEN BIT(1)
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#define LCDC_CLKC_ENABLE_DMACLKEN BIT(2)
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/* LCD DMA Control Register */
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#define LCDC_DMA_CTRL_BURST_SIZE(x) (((x) & GENMASK(2, 0)) << 4)
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#define LCDC_DMA_CTRL_BURST_1 0x0
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#define LCDC_DMA_CTRL_BURST_2 0x1
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#define LCDC_DMA_CTRL_BURST_4 0x2
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#define LCDC_DMA_CTRL_BURST_8 0x3
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#define LCDC_DMA_CTRL_BURST_16 0x4
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#define LCDC_DMA_CTRL_FIFO_TH(x) (((x) & GENMASK(2, 0)) << 8)
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/* LCD Timing_0 Register */
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#define LCDC_RASTER_TIMING_0_HORMSB(x) ((((x) - 1) & BIT(10)) >> 7)
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#define LCDC_RASTER_TIMING_0_HORLSB(x) (((((x) >> 4) - 1) & GENMASK(5, 0)) << 4)
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#define LCDC_RASTER_TIMING_0_HSWLSB(x) ((((x) - 1) & GENMASK(5, 0)) << 10)
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#define LCDC_RASTER_TIMING_0_HFPLSB(x) ((((x) - 1) & GENMASK(7, 0)) << 16)
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#define LCDC_RASTER_TIMING_0_HBPLSB(x) ((((x) - 1) & GENMASK(7, 0)) << 24)
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/* LCD Timing_1 Register */
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#define LCDC_RASTER_TIMING_1_VERLSB(x) (((x) - 1) & GENMASK(9, 0))
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#define LCDC_RASTER_TIMING_1_VSW(x) ((((x) - 1) & GENMASK(5, 0)) << 10)
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#define LCDC_RASTER_TIMING_1_VFP(x) (((x) & GENMASK(7, 0)) << 16)
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#define LCDC_RASTER_TIMING_1_VBP(x) (((x) & GENMASK(7, 0)) << 24)
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/* LCD Timing_2 Register */
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#define LCDC_RASTER_TIMING_2_HFPMSB(x) ((((x) - 1) & GENMASK(9, 8)) >> 8)
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#define LCDC_RASTER_TIMING_2_HBPMSB(x) ((((x) - 1) & GENMASK(9, 8)) >> 4)
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#define LCDC_RASTER_TIMING_2_ACB(x) (((x) & GENMASK(7, 0)) << 8)
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#define LCDC_RASTER_TIMING_2_ACBI(x) (((x) & GENMASK(3, 0)) << 16)
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#define LCDC_RASTER_TIMING_2_VSYNC_INVERT BIT(20)
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#define LCDC_RASTER_TIMING_2_HSYNC_INVERT BIT(21)
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#define LCDC_RASTER_TIMING_2_PXCLK_INVERT BIT(22)
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#define LCDC_RASTER_TIMING_2_DE_INVERT BIT(23)
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#define LCDC_RASTER_TIMING_2_HSVS_RISEFALL BIT(24)
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#define LCDC_RASTER_TIMING_2_HSVS_CONTROL BIT(25)
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#define LCDC_RASTER_TIMING_2_VERMSB(x) ((((x) - 1) & BIT(10)) << 16)
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#define LCDC_RASTER_TIMING_2_HSWMSB(x) ((((x) - 1) & GENMASK(9, 6)) << 21)
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/* LCD Raster Ctrl Register */
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#define LCDC_RASTER_CTRL_ENABLE BIT(0)
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#define LCDC_RASTER_CTRL_TFT_MODE BIT(7)
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#define LCDC_RASTER_CTRL_DATA_ORDER BIT(8)
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#define LCDC_RASTER_CTRL_REQDLY(x) (((x) & GENMASK(7, 0)) << 12)
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#define LCDC_RASTER_CTRL_PALMODE_RAWDATA (0x02 << 20)
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#define LCDC_RASTER_CTRL_TFT_ALT_ENABLE BIT(23)
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#define LCDC_RASTER_CTRL_TFT_24BPP_MODE BIT(25)
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#define LCDC_RASTER_CTRL_TFT_24BPP_UNPACK BIT(26)
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struct am335x_lcdhw {
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unsigned int pid; /* 0x00 */
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unsigned int ctrl; /* 0x04 */
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unsigned int gap0; /* 0x08 */
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unsigned int lidd_ctrl; /* 0x0C */
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unsigned int lidd_cs0_conf; /* 0x10 */
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unsigned int lidd_cs0_addr; /* 0x14 */
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unsigned int lidd_cs0_data; /* 0x18 */
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unsigned int lidd_cs1_conf; /* 0x1C */
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unsigned int lidd_cs1_addr; /* 0x20 */
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unsigned int lidd_cs1_data; /* 0x24 */
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unsigned int raster_ctrl; /* 0x28 */
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unsigned int raster_timing0; /* 0x2C */
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unsigned int raster_timing1; /* 0x30 */
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unsigned int raster_timing2; /* 0x34 */
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unsigned int raster_subpanel; /* 0x38 */
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unsigned int raster_subpanel2; /* 0x3C */
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unsigned int lcddma_ctrl; /* 0x40 */
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unsigned int lcddma_fb0_base; /* 0x44 */
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unsigned int lcddma_fb0_ceiling; /* 0x48 */
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unsigned int lcddma_fb1_base; /* 0x4C */
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unsigned int lcddma_fb1_ceiling; /* 0x50 */
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unsigned int sysconfig; /* 0x54 */
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unsigned int irqstatus_raw; /* 0x58 */
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unsigned int irqstatus; /* 0x5C */
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unsigned int irqenable_set; /* 0x60 */
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unsigned int irqenable_clear; /* 0x64 */
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unsigned int gap1; /* 0x68 */
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unsigned int clkc_enable; /* 0x6C */
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unsigned int clkc_reset; /* 0x70 */
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};
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DECLARE_GLOBAL_DATA_PTR;
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#if !defined(LCD_CNTL_BASE)
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#error "hw-base address of LCD-Controller (LCD_CNTL_BASE) not defined!"
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#endif
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/* Macro definitions */
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#define FBSIZE(x) (((x)->hactive * (x)->vactive * (x)->bpp) >> 3)
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#define LCDC_RASTER_TIMING_2_INVMASK(x) ((x) & GENMASK(25, 20))
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static struct am335x_lcdhw *lcdhw = (void *)LCD_CNTL_BASE;
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int lcd_get_size(int *line_length)
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{
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*line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
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return *line_length * panel_info.vl_row + 0x20;
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}
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struct dpll_data {
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unsigned long rounded_rate;
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u16 rounded_m;
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u8 rounded_n;
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u8 rounded_div;
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};
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/**
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* am335x_dpll_round_rate() - Round a target rate for an OMAP DPLL
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*
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* @dpll_data: struct dpll_data pointer for the DPLL
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* @rate: New DPLL clock rate
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* Return: rounded rate and the computed m, n and div values in the dpll_data
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* structure, or -ve error code.
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*/
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static ulong am335x_dpll_round_rate(struct dpll_data *dd, ulong rate)
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{
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unsigned int m, n, d;
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unsigned long rounded_rate;
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int err, err_r;
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dd->rounded_rate = -EFAULT;
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err = rate;
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err_r = err;
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for (d = 2; err && d < 255; d++) {
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for (m = 2; m < 2047; m++) {
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if ((V_OSCK * m) < (rate * d))
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continue;
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n = (V_OSCK * m) / (rate * d);
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if (n > 127)
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break;
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if (((V_OSCK * m) / n) > LCDC_FMAX)
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break;
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rounded_rate = (V_OSCK * m) / n / d;
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err = abs(rounded_rate - rate);
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if (err < err_r) {
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err_r = err;
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dd->rounded_rate = rounded_rate;
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dd->rounded_m = m;
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dd->rounded_n = n;
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dd->rounded_div = d;
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if (err == 0)
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break;
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}
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}
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}
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debug("DPLL display: best error %d Hz (M %d, N %d, DIV %d)\n",
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err_r, dd->rounded_m, dd->rounded_n, dd->rounded_div);
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return dd->rounded_rate;
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}
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/**
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* am335x_fb_set_pixel_clk_rate() - Set pixel clock rate.
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*
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* @am335x_lcdhw: Base address of the LCD controller registers.
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* @rate: New clock rate in Hz.
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* Return: new rate, or -ve error code.
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*/
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static ulong am335x_fb_set_pixel_clk_rate(struct am335x_lcdhw *regs, ulong rate)
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{
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struct dpll_params dpll_disp = { 1, 0, 1, -1, -1, -1, -1 };
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struct dpll_data dd;
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ulong round_rate;
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u32 reg;
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round_rate = am335x_dpll_round_rate(&dd, rate);
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if (IS_ERR_VALUE(round_rate))
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return round_rate;
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dpll_disp.m = dd.rounded_m;
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dpll_disp.n = dd.rounded_n;
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do_setup_dpll(&dpll_disp_regs, &dpll_disp);
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reg = readl(®s->ctrl) & ~LCDC_CTRL_CLK_DIVISOR_MASK;
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reg |= LCDC_CTRL_CLK_DIVISOR(dd.rounded_div);
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writel(reg, ®s->ctrl);
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return round_rate;
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}
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int am335xfb_init(struct am335x_lcdpanel *panel)
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{
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u32 raster_ctrl = 0;
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struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
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ulong rate;
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u32 reg;
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if (gd->fb_base == 0) {
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printf("ERROR: no valid fb_base stored in GLOBAL_DATA_PTR!\n");
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return -1;
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}
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if (panel == NULL) {
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printf("ERROR: missing ptr to am335x_lcdpanel!\n");
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return -1;
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}
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/* We can already set the bits for the raster_ctrl in this check */
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switch (panel->bpp) {
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case 16:
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break;
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case 32:
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raster_ctrl |= LCDC_RASTER_CTRL_TFT_24BPP_UNPACK;
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/* fallthrough */
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case 24:
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raster_ctrl |= LCDC_RASTER_CTRL_TFT_24BPP_MODE;
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break;
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default:
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pr_err("am335x-fb: invalid bpp value: %d\n", panel->bpp);
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return -1;
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}
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/* check given clock-frequency */
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if (panel->pxl_clk > (LCDC_FMAX / 2)) {
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pr_err("am335x-fb: requested pxl-clk: %d not supported!\n",
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panel->pxl_clk);
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return -1;
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}
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debug("setting up LCD-Controller for %dx%dx%d (hfp=%d,hbp=%d,hsw=%d / ",
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panel->hactive, panel->vactive, panel->bpp,
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panel->hfp, panel->hbp, panel->hsw);
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debug("vfp=%d,vbp=%d,vsw=%d / clk=%d)\n",
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panel->vfp, panel->vfp, panel->vsw, panel->pxl_clk);
|
||||
debug("using frambuffer at 0x%08x with size %d.\n",
|
||||
(unsigned int)gd->fb_base, FBSIZE(panel));
|
||||
|
||||
rate = am335x_fb_set_pixel_clk_rate(lcdhw, panel->pxl_clk);
|
||||
if (IS_ERR_VALUE(rate))
|
||||
return rate;
|
||||
|
||||
/* clock source for LCDC from dispPLL M2 */
|
||||
writel(0x0, &cmdpll->clklcdcpixelclk);
|
||||
|
||||
/* palette default entry */
|
||||
memset((void *)gd->fb_base, 0, 0x20);
|
||||
*(unsigned int *)gd->fb_base = 0x4000;
|
||||
/* point fb behind palette */
|
||||
gd->fb_base += 0x20;
|
||||
|
||||
/* turn ON display through powercontrol function if accessible */
|
||||
if (panel->panel_power_ctrl != NULL)
|
||||
panel->panel_power_ctrl(1);
|
||||
|
||||
debug("am335x-fb: wait for stable power ...\n");
|
||||
mdelay(panel->pup_delay);
|
||||
lcdhw->clkc_enable = LCDC_CLKC_ENABLE_CORECLKEN |
|
||||
LCDC_CLKC_ENABLE_LIDDCLKEN | LCDC_CLKC_ENABLE_DMACLKEN;
|
||||
lcdhw->raster_ctrl = 0;
|
||||
|
||||
reg = lcdhw->ctrl & LCDC_CTRL_CLK_DIVISOR_MASK;
|
||||
reg |= LCDC_CTRL_RASTER_MODE;
|
||||
lcdhw->ctrl = reg;
|
||||
|
||||
lcdhw->lcddma_fb0_base = gd->fb_base;
|
||||
lcdhw->lcddma_fb0_ceiling = gd->fb_base + FBSIZE(panel);
|
||||
lcdhw->lcddma_fb1_base = gd->fb_base;
|
||||
lcdhw->lcddma_fb1_ceiling = gd->fb_base + FBSIZE(panel);
|
||||
lcdhw->lcddma_ctrl = LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_16);
|
||||
|
||||
lcdhw->raster_timing0 = LCDC_RASTER_TIMING_0_HORLSB(panel->hactive) |
|
||||
LCDC_RASTER_TIMING_0_HORMSB(panel->hactive) |
|
||||
LCDC_RASTER_TIMING_0_HFPLSB(panel->hfp) |
|
||||
LCDC_RASTER_TIMING_0_HBPLSB(panel->hbp) |
|
||||
LCDC_RASTER_TIMING_0_HSWLSB(panel->hsw);
|
||||
lcdhw->raster_timing1 = LCDC_RASTER_TIMING_1_VBP(panel->vbp) |
|
||||
LCDC_RASTER_TIMING_1_VFP(panel->vfp) |
|
||||
LCDC_RASTER_TIMING_1_VSW(panel->vsw) |
|
||||
LCDC_RASTER_TIMING_1_VERLSB(panel->vactive);
|
||||
lcdhw->raster_timing2 = LCDC_RASTER_TIMING_2_HSWMSB(panel->hsw) |
|
||||
LCDC_RASTER_TIMING_2_VERMSB(panel->vactive) |
|
||||
LCDC_RASTER_TIMING_2_INVMASK(panel->pol) |
|
||||
LCDC_RASTER_TIMING_2_HBPMSB(panel->hbp) |
|
||||
LCDC_RASTER_TIMING_2_HFPMSB(panel->hfp) |
|
||||
0x0000FF00; /* clk cycles for ac-bias */
|
||||
lcdhw->raster_ctrl = raster_ctrl |
|
||||
LCDC_RASTER_CTRL_PALMODE_RAWDATA |
|
||||
LCDC_RASTER_CTRL_TFT_MODE |
|
||||
LCDC_RASTER_CTRL_ENABLE;
|
||||
|
||||
debug("am335x-fb: waiting picture to be stable.\n.");
|
||||
mdelay(panel->pon_delay);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1,71 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2013-2018 Hannes Schmelzer <oe5hpm@oevsv.at> -
|
||||
* B&R Industrial Automation GmbH - http://www.br-automation.com
|
||||
*/
|
||||
|
||||
#ifndef AM335X_FB_H
|
||||
#define AM335X_FB_H
|
||||
|
||||
#define HSVS_CONTROL BIT(25) /*
|
||||
* 0 = lcd_lp and lcd_fp are driven on
|
||||
* opposite edges of pixel clock than
|
||||
* the lcd_pixel_o
|
||||
* 1 = lcd_lp and lcd_fp are driven
|
||||
* according to bit 24 Note that this
|
||||
* bit MUST be set to '0' for Passive
|
||||
* Matrix displays the edge timing is
|
||||
* fixed
|
||||
*/
|
||||
#define HSVS_RISEFALL BIT(24) /*
|
||||
* 0 = lcd_lp and lcd_fp are driven on
|
||||
* the rising edge of pixel clock (bit
|
||||
* 25 must be set to 1)
|
||||
* 1 = lcd_lp and lcd_fp are driven on
|
||||
* the falling edge of pixel clock (bit
|
||||
* 25 must be set to 1)
|
||||
*/
|
||||
#define DE_INVERT BIT(23) /*
|
||||
* 0 = DE is low-active
|
||||
* 1 = DE is high-active
|
||||
*/
|
||||
#define PXCLK_INVERT BIT(22) /*
|
||||
* 0 = pix-clk is high-active
|
||||
* 1 = pic-clk is low-active
|
||||
*/
|
||||
#define HSYNC_INVERT BIT(21) /*
|
||||
* 0 = HSYNC is active high
|
||||
* 1 = HSYNC is avtive low
|
||||
*/
|
||||
#define VSYNC_INVERT BIT(20) /*
|
||||
* 0 = VSYNC is active high
|
||||
* 1 = VSYNC is active low
|
||||
*/
|
||||
|
||||
struct am335x_lcdpanel {
|
||||
unsigned int hactive; /* Horizontal active area */
|
||||
unsigned int vactive; /* Vertical active area */
|
||||
unsigned int bpp; /* bits per pixel */
|
||||
unsigned int hfp; /* Horizontal front porch */
|
||||
unsigned int hbp; /* Horizontal back porch */
|
||||
unsigned int hsw; /* Horizontal Sync Pulse Width */
|
||||
unsigned int vfp; /* Vertical front porch */
|
||||
unsigned int vbp; /* Vertical back porch */
|
||||
unsigned int vsw; /* Vertical Sync Pulse Width */
|
||||
unsigned int pxl_clk; /* Pixel clock */
|
||||
unsigned int pol; /* polarity of sync, clock signals */
|
||||
unsigned int pup_delay; /*
|
||||
* time in ms after power on to
|
||||
* initialization of lcd-controller
|
||||
* (VCC ramp up time)
|
||||
*/
|
||||
unsigned int pon_delay; /*
|
||||
* time in ms after initialization of
|
||||
* lcd-controller (pic stabilization)
|
||||
*/
|
||||
void (*panel_power_ctrl)(int); /* fp for power on/off display */
|
||||
};
|
||||
|
||||
int am335xfb_init(struct am335x_lcdpanel *panel);
|
||||
|
||||
#endif /* AM335X_FB_H */
|
||||
|
|
@ -1,172 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* OMAP panel support
|
||||
*
|
||||
* Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <backlight.h>
|
||||
#include <clk.h>
|
||||
#include <display.h>
|
||||
#include <dm.h>
|
||||
#include <dm/device_compat.h>
|
||||
#include <log.h>
|
||||
#include <panel.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <linux/err.h>
|
||||
#include "tilcdc.h"
|
||||
|
||||
struct tilcdc_panel_priv {
|
||||
struct tilcdc_panel_info info;
|
||||
struct display_timing timing;
|
||||
struct udevice *backlight;
|
||||
struct gpio_desc enable;
|
||||
};
|
||||
|
||||
static int tilcdc_panel_enable_backlight(struct udevice *dev)
|
||||
{
|
||||
struct tilcdc_panel_priv *priv = dev_get_priv(dev);
|
||||
|
||||
if (dm_gpio_is_valid(&priv->enable))
|
||||
dm_gpio_set_value(&priv->enable, 1);
|
||||
|
||||
if (priv->backlight)
|
||||
return backlight_enable(priv->backlight);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tilcdc_panel_set_backlight(struct udevice *dev, int percent)
|
||||
{
|
||||
struct tilcdc_panel_priv *priv = dev_get_priv(dev);
|
||||
|
||||
if (dm_gpio_is_valid(&priv->enable))
|
||||
dm_gpio_set_value(&priv->enable, 1);
|
||||
|
||||
if (priv->backlight)
|
||||
return backlight_set_brightness(priv->backlight, percent);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int tilcdc_panel_get_display_info(struct udevice *dev,
|
||||
struct tilcdc_panel_info *info)
|
||||
{
|
||||
struct tilcdc_panel_priv *priv = dev_get_priv(dev);
|
||||
|
||||
memcpy(info, &priv->info, sizeof(*info));
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tilcdc_panel_get_display_timing(struct udevice *dev,
|
||||
struct display_timing *timing)
|
||||
{
|
||||
struct tilcdc_panel_priv *priv = dev_get_priv(dev);
|
||||
|
||||
memcpy(timing, &priv->timing, sizeof(*timing));
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tilcdc_panel_remove(struct udevice *dev)
|
||||
{
|
||||
struct tilcdc_panel_priv *priv = dev_get_priv(dev);
|
||||
|
||||
if (dm_gpio_is_valid(&priv->enable))
|
||||
dm_gpio_free(dev, &priv->enable);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tilcdc_panel_probe(struct udevice *dev)
|
||||
{
|
||||
struct tilcdc_panel_priv *priv = dev_get_priv(dev);
|
||||
int err;
|
||||
|
||||
err = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
|
||||
"backlight", &priv->backlight);
|
||||
if (err)
|
||||
dev_warn(dev, "failed to get backlight\n");
|
||||
|
||||
err = gpio_request_by_name(dev, "enable-gpios", 0, &priv->enable,
|
||||
GPIOD_IS_OUT);
|
||||
if (err) {
|
||||
dev_warn(dev, "failed to get enable GPIO\n");
|
||||
if (err != -ENOENT)
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tilcdc_panel_of_to_plat(struct udevice *dev)
|
||||
{
|
||||
struct tilcdc_panel_priv *priv = dev_get_priv(dev);
|
||||
ofnode node;
|
||||
int err;
|
||||
|
||||
err = ofnode_decode_display_timing(dev_ofnode(dev), 0, &priv->timing);
|
||||
if (err) {
|
||||
dev_err(dev, "failed to get display timing\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
node = dev_read_subnode(dev, "panel-info");
|
||||
if (!ofnode_valid(node)) {
|
||||
dev_err(dev, "missing 'panel-info' node\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
err |= ofnode_read_u32(node, "ac-bias", &priv->info.ac_bias);
|
||||
err |= ofnode_read_u32(node, "ac-bias-intrpt",
|
||||
&priv->info.ac_bias_intrpt);
|
||||
err |= ofnode_read_u32(node, "dma-burst-sz", &priv->info.dma_burst_sz);
|
||||
err |= ofnode_read_u32(node, "bpp", &priv->info.bpp);
|
||||
err |= ofnode_read_u32(node, "fdd", &priv->info.fdd);
|
||||
err |= ofnode_read_u32(node, "sync-edge", &priv->info.sync_edge);
|
||||
err |= ofnode_read_u32(node, "sync-ctrl", &priv->info.sync_ctrl);
|
||||
err |= ofnode_read_u32(node, "raster-order", &priv->info.raster_order);
|
||||
err |= ofnode_read_u32(node, "fifo-th", &priv->info.fifo_th);
|
||||
if (err) {
|
||||
dev_err(dev, "failed to get panel info\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
/* optional */
|
||||
priv->info.tft_alt_mode = ofnode_read_bool(node, "tft-alt-mode");
|
||||
priv->info.invert_pxl_clk = ofnode_read_bool(node, "invert-pxl-clk");
|
||||
|
||||
dev_dbg(dev, "LCD: %dx%d, bpp=%d, clk=%d Hz\n",
|
||||
priv->timing.hactive.typ, priv->timing.vactive.typ,
|
||||
priv->info.bpp, priv->timing.pixelclock.typ);
|
||||
dev_dbg(dev, " hbp=%d, hfp=%d, hsw=%d\n",
|
||||
priv->timing.hback_porch.typ, priv->timing.hfront_porch.typ,
|
||||
priv->timing.hsync_len.typ);
|
||||
dev_dbg(dev, " vbp=%d, vfp=%d, vsw=%d\n",
|
||||
priv->timing.vback_porch.typ, priv->timing.vfront_porch.typ,
|
||||
priv->timing.vsync_len.typ);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct panel_ops tilcdc_panel_ops = {
|
||||
.enable_backlight = tilcdc_panel_enable_backlight,
|
||||
.set_backlight = tilcdc_panel_set_backlight,
|
||||
.get_display_timing = tilcdc_panel_get_display_timing,
|
||||
};
|
||||
|
||||
static const struct udevice_id tilcdc_panel_ids[] = {
|
||||
{.compatible = "ti,tilcdc,panel"},
|
||||
{}
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(tilcdc_panel) = {
|
||||
.name = "tilcdc_panel",
|
||||
.id = UCLASS_PANEL,
|
||||
.of_match = tilcdc_panel_ids,
|
||||
.ops = &tilcdc_panel_ops,
|
||||
.of_to_plat = tilcdc_panel_of_to_plat,
|
||||
.probe = tilcdc_panel_probe,
|
||||
.remove = tilcdc_panel_remove,
|
||||
.priv_auto = sizeof(struct tilcdc_panel_priv),
|
||||
};
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
|
||||
*/
|
||||
|
||||
#ifndef _TILCDC_PANEL_H
|
||||
#define _TILCDC_PANEL_H
|
||||
|
||||
#include "tilcdc.h"
|
||||
|
||||
int tilcdc_panel_get_display_info(struct udevice *dev,
|
||||
struct tilcdc_panel_info *info);
|
||||
|
||||
#endif /* _TILCDC_PANEL_H */
|
||||
|
|
@ -1,426 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clk.h>
|
||||
#include <dm.h>
|
||||
#include <dm/device_compat.h>
|
||||
#include <lcd.h>
|
||||
#include <log.h>
|
||||
#include <panel.h>
|
||||
#include <video.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/utils.h>
|
||||
#include "tilcdc.h"
|
||||
#include "tilcdc-panel.h"
|
||||
|
||||
#define LCDC_FMAX 200000000
|
||||
|
||||
/* LCD Control Register */
|
||||
#define LCDC_CTRL_CLK_DIVISOR_MASK GENMASK(15, 8)
|
||||
#define LCDC_CTRL_RASTER_MODE BIT(0)
|
||||
#define LCDC_CTRL_CLK_DIVISOR(x) (((x) & GENMASK(7, 0)) << 8)
|
||||
/* LCD Clock Enable Register */
|
||||
#define LCDC_CLKC_ENABLE_CORECLKEN BIT(0)
|
||||
#define LCDC_CLKC_ENABLE_LIDDCLKEN BIT(1)
|
||||
#define LCDC_CLKC_ENABLE_DMACLKEN BIT(2)
|
||||
/* LCD DMA Control Register */
|
||||
#define LCDC_DMA_CTRL_BURST_SIZE(x) (((x) & GENMASK(2, 0)) << 4)
|
||||
#define LCDC_DMA_CTRL_BURST_1 0x0
|
||||
#define LCDC_DMA_CTRL_BURST_2 0x1
|
||||
#define LCDC_DMA_CTRL_BURST_4 0x2
|
||||
#define LCDC_DMA_CTRL_BURST_8 0x3
|
||||
#define LCDC_DMA_CTRL_BURST_16 0x4
|
||||
#define LCDC_DMA_CTRL_FIFO_TH(x) (((x) & GENMASK(2, 0)) << 8)
|
||||
/* LCD Timing_0 Register */
|
||||
#define LCDC_RASTER_TIMING_0_HORMSB(x) ((((x) - 1) & BIT(10)) >> 7)
|
||||
#define LCDC_RASTER_TIMING_0_HORLSB(x) (((((x) >> 4) - 1) & GENMASK(5, 0)) << 4)
|
||||
#define LCDC_RASTER_TIMING_0_HSWLSB(x) ((((x) - 1) & GENMASK(5, 0)) << 10)
|
||||
#define LCDC_RASTER_TIMING_0_HFPLSB(x) ((((x) - 1) & GENMASK(7, 0)) << 16)
|
||||
#define LCDC_RASTER_TIMING_0_HBPLSB(x) ((((x) - 1) & GENMASK(7, 0)) << 24)
|
||||
/* LCD Timing_1 Register */
|
||||
#define LCDC_RASTER_TIMING_1_VERLSB(x) (((x) - 1) & GENMASK(9, 0))
|
||||
#define LCDC_RASTER_TIMING_1_VSW(x) ((((x) - 1) & GENMASK(5, 0)) << 10)
|
||||
#define LCDC_RASTER_TIMING_1_VFP(x) (((x) & GENMASK(7, 0)) << 16)
|
||||
#define LCDC_RASTER_TIMING_1_VBP(x) (((x) & GENMASK(7, 0)) << 24)
|
||||
/* LCD Timing_2 Register */
|
||||
#define LCDC_RASTER_TIMING_2_HFPMSB(x) ((((x) - 1) & GENMASK(9, 8)) >> 8)
|
||||
#define LCDC_RASTER_TIMING_2_HBPMSB(x) ((((x) - 1) & GENMASK(9, 8)) >> 4)
|
||||
#define LCDC_RASTER_TIMING_2_ACB(x) (((x) & GENMASK(7, 0)) << 8)
|
||||
#define LCDC_RASTER_TIMING_2_ACBI(x) (((x) & GENMASK(3, 0)) << 16)
|
||||
#define LCDC_RASTER_TIMING_2_VSYNC_INVERT BIT(20)
|
||||
#define LCDC_RASTER_TIMING_2_HSYNC_INVERT BIT(21)
|
||||
#define LCDC_RASTER_TIMING_2_PXCLK_INVERT BIT(22)
|
||||
#define LCDC_RASTER_TIMING_2_DE_INVERT BIT(23)
|
||||
#define LCDC_RASTER_TIMING_2_HSVS_RISEFALL BIT(24)
|
||||
#define LCDC_RASTER_TIMING_2_HSVS_CONTROL BIT(25)
|
||||
#define LCDC_RASTER_TIMING_2_VERMSB(x) ((((x) - 1) & BIT(10)) << 16)
|
||||
#define LCDC_RASTER_TIMING_2_HSWMSB(x) ((((x) - 1) & GENMASK(9, 6)) << 21)
|
||||
/* LCD Raster Ctrl Register */
|
||||
#define LCDC_RASTER_CTRL_ENABLE BIT(0)
|
||||
#define LCDC_RASTER_CTRL_TFT_MODE BIT(7)
|
||||
#define LCDC_RASTER_CTRL_DATA_ORDER BIT(8)
|
||||
#define LCDC_RASTER_CTRL_REQDLY(x) (((x) & GENMASK(7, 0)) << 12)
|
||||
#define LCDC_RASTER_CTRL_PALMODE_RAWDATA (0x02 << 20)
|
||||
#define LCDC_RASTER_CTRL_TFT_ALT_ENABLE BIT(23)
|
||||
#define LCDC_RASTER_CTRL_TFT_24BPP_MODE BIT(25)
|
||||
#define LCDC_RASTER_CTRL_TFT_24BPP_UNPACK BIT(26)
|
||||
|
||||
enum {
|
||||
LCDC_MAX_WIDTH = 2048,
|
||||
LCDC_MAX_HEIGHT = 2048,
|
||||
LCDC_MAX_LOG2_BPP = VIDEO_BPP32,
|
||||
};
|
||||
|
||||
struct tilcdc_regs {
|
||||
u32 pid;
|
||||
u32 ctrl;
|
||||
u32 gap0;
|
||||
u32 lidd_ctrl;
|
||||
u32 lidd_cs0_conf;
|
||||
u32 lidd_cs0_addr;
|
||||
u32 lidd_cs0_data;
|
||||
u32 lidd_cs1_conf;
|
||||
u32 lidd_cs1_addr;
|
||||
u32 lidd_cs1_data;
|
||||
u32 raster_ctrl;
|
||||
u32 raster_timing0;
|
||||
u32 raster_timing1;
|
||||
u32 raster_timing2;
|
||||
u32 raster_subpanel;
|
||||
u32 raster_subpanel2;
|
||||
u32 lcddma_ctrl;
|
||||
u32 lcddma_fb0_base;
|
||||
u32 lcddma_fb0_ceiling;
|
||||
u32 lcddma_fb1_base;
|
||||
u32 lcddma_fb1_ceiling;
|
||||
u32 sysconfig;
|
||||
u32 irqstatus_raw;
|
||||
u32 irqstatus;
|
||||
u32 irqenable_set;
|
||||
u32 irqenable_clear;
|
||||
u32 gap1;
|
||||
u32 clkc_enable;
|
||||
u32 clkc_reset;
|
||||
};
|
||||
|
||||
struct tilcdc_priv {
|
||||
struct tilcdc_regs *regs;
|
||||
struct clk gclk;
|
||||
struct clk dpll_m2_clk;
|
||||
};
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static ulong tilcdc_set_pixel_clk_rate(struct udevice *dev, ulong rate)
|
||||
{
|
||||
struct tilcdc_priv *priv = dev_get_priv(dev);
|
||||
struct tilcdc_regs *regs = priv->regs;
|
||||
ulong mult_rate, mult_round_rate, best_err, err;
|
||||
u32 v;
|
||||
int div, i;
|
||||
|
||||
best_err = rate;
|
||||
div = 0;
|
||||
for (i = 2; i <= 255; i++) {
|
||||
mult_rate = rate * i;
|
||||
mult_round_rate = clk_round_rate(&priv->gclk, mult_rate);
|
||||
if (IS_ERR_VALUE(mult_round_rate))
|
||||
return mult_round_rate;
|
||||
|
||||
err = mult_rate - mult_round_rate;
|
||||
if (err < best_err) {
|
||||
best_err = err;
|
||||
div = i;
|
||||
if (err == 0)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (div == 0) {
|
||||
dev_err(dev, "failed to find a divisor\n");
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
mult_rate = clk_set_rate(&priv->gclk, rate * div);
|
||||
v = readl(®s->ctrl) & ~LCDC_CTRL_CLK_DIVISOR_MASK;
|
||||
v |= LCDC_CTRL_CLK_DIVISOR(div);
|
||||
writel(v, ®s->ctrl);
|
||||
rate = mult_rate / div;
|
||||
dev_dbg(dev, "rate=%ld, div=%d, err=%ld\n", rate, div, err);
|
||||
return rate;
|
||||
}
|
||||
|
||||
static int tilcdc_remove(struct udevice *dev)
|
||||
{
|
||||
struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
|
||||
struct tilcdc_priv *priv = dev_get_priv(dev);
|
||||
|
||||
uc_plat->base -= 0x20;
|
||||
uc_plat->size += 0x20;
|
||||
clk_release_all(&priv->gclk, 1);
|
||||
clk_release_all(&priv->dpll_m2_clk, 1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tilcdc_probe(struct udevice *dev)
|
||||
{
|
||||
struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
|
||||
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
|
||||
struct tilcdc_priv *priv = dev_get_priv(dev);
|
||||
struct tilcdc_regs *regs = priv->regs;
|
||||
struct udevice *panel, *clk_dev;
|
||||
struct tilcdc_panel_info info;
|
||||
struct display_timing timing;
|
||||
ulong rate;
|
||||
u32 reg;
|
||||
int err;
|
||||
|
||||
/* Before relocation we don't need to do anything */
|
||||
if (!(gd->flags & GD_FLG_RELOC))
|
||||
return 0;
|
||||
|
||||
err = uclass_get_device(UCLASS_PANEL, 0, &panel);
|
||||
if (err) {
|
||||
dev_err(dev, "failed to get panel\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
err = panel_get_display_timing(panel, &timing);
|
||||
if (err) {
|
||||
dev_err(dev, "failed to get display timing\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
if (timing.pixelclock.typ > (LCDC_FMAX / 2)) {
|
||||
dev_err(dev, "invalid display clock-frequency: %d Hz\n",
|
||||
timing.pixelclock.typ);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (timing.hactive.typ > LCDC_MAX_WIDTH)
|
||||
timing.hactive.typ = LCDC_MAX_WIDTH;
|
||||
|
||||
if (timing.vactive.typ > LCDC_MAX_HEIGHT)
|
||||
timing.vactive.typ = LCDC_MAX_HEIGHT;
|
||||
|
||||
err = tilcdc_panel_get_display_info(panel, &info);
|
||||
if (err) {
|
||||
dev_err(dev, "failed to get panel info\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
switch (info.bpp) {
|
||||
case 16:
|
||||
case 24:
|
||||
case 32:
|
||||
break;
|
||||
default:
|
||||
dev_err(dev, "invalid seting, bpp: %d\n", info.bpp);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
switch (info.dma_burst_sz) {
|
||||
case 1:
|
||||
case 2:
|
||||
case 4:
|
||||
case 8:
|
||||
case 16:
|
||||
break;
|
||||
default:
|
||||
dev_err(dev, "invalid setting, dma-burst-sz: %d\n",
|
||||
info.dma_burst_sz);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
err = uclass_get_device_by_name(UCLASS_CLK, "lcd_gclk@534", &clk_dev);
|
||||
if (err) {
|
||||
dev_err(dev, "failed to get lcd_gclk device\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
err = clk_request(clk_dev, &priv->gclk);
|
||||
if (err) {
|
||||
dev_err(dev, "failed to get %s clock\n", clk_dev->name);
|
||||
return err;
|
||||
}
|
||||
|
||||
rate = tilcdc_set_pixel_clk_rate(dev, timing.pixelclock.typ);
|
||||
if (IS_ERR_VALUE(rate)) {
|
||||
dev_err(dev, "failed to set pixel clock rate\n");
|
||||
return rate;
|
||||
}
|
||||
|
||||
err = uclass_get_device_by_name(UCLASS_CLK, "dpll_disp_m2_ck@4a4",
|
||||
&clk_dev);
|
||||
if (err) {
|
||||
dev_err(dev, "failed to get dpll_disp_m2 clock device\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
err = clk_request(clk_dev, &priv->dpll_m2_clk);
|
||||
if (err) {
|
||||
dev_err(dev, "failed to get %s clock\n", clk_dev->name);
|
||||
return err;
|
||||
}
|
||||
|
||||
err = clk_set_parent(&priv->gclk, &priv->dpll_m2_clk);
|
||||
if (err) {
|
||||
dev_err(dev, "failed to set %s clock as %s's parent\n",
|
||||
priv->dpll_m2_clk.dev->name, priv->gclk.dev->name);
|
||||
return err;
|
||||
}
|
||||
|
||||
/* palette default entry */
|
||||
memset((void *)uc_plat->base, 0, 0x20);
|
||||
*(unsigned int *)uc_plat->base = 0x4000;
|
||||
/* point fb behind palette */
|
||||
uc_plat->base += 0x20;
|
||||
uc_plat->size -= 0x20;
|
||||
|
||||
writel(LCDC_CLKC_ENABLE_CORECLKEN | LCDC_CLKC_ENABLE_LIDDCLKEN |
|
||||
LCDC_CLKC_ENABLE_DMACLKEN, ®s->clkc_enable);
|
||||
writel(0, ®s->raster_ctrl);
|
||||
|
||||
reg = readl(®s->ctrl) & LCDC_CTRL_CLK_DIVISOR_MASK;
|
||||
reg |= LCDC_CTRL_RASTER_MODE;
|
||||
writel(reg, ®s->ctrl);
|
||||
|
||||
reg = (timing.hactive.typ * timing.vactive.typ * info.bpp) >> 3;
|
||||
reg += uc_plat->base;
|
||||
writel(uc_plat->base, ®s->lcddma_fb0_base);
|
||||
writel(reg, ®s->lcddma_fb0_ceiling);
|
||||
writel(uc_plat->base, ®s->lcddma_fb1_base);
|
||||
writel(reg, ®s->lcddma_fb1_ceiling);
|
||||
|
||||
reg = LCDC_DMA_CTRL_FIFO_TH(info.fifo_th);
|
||||
switch (info.dma_burst_sz) {
|
||||
case 1:
|
||||
reg |= LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_1);
|
||||
break;
|
||||
case 2:
|
||||
reg |= LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_2);
|
||||
break;
|
||||
case 4:
|
||||
reg |= LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_4);
|
||||
break;
|
||||
case 8:
|
||||
reg |= LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_8);
|
||||
break;
|
||||
case 16:
|
||||
reg |= LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_16);
|
||||
break;
|
||||
}
|
||||
|
||||
writel(reg, ®s->lcddma_ctrl);
|
||||
|
||||
writel(LCDC_RASTER_TIMING_0_HORLSB(timing.hactive.typ) |
|
||||
LCDC_RASTER_TIMING_0_HORMSB(timing.hactive.typ) |
|
||||
LCDC_RASTER_TIMING_0_HFPLSB(timing.hfront_porch.typ) |
|
||||
LCDC_RASTER_TIMING_0_HBPLSB(timing.hback_porch.typ) |
|
||||
LCDC_RASTER_TIMING_0_HSWLSB(timing.hsync_len.typ),
|
||||
®s->raster_timing0);
|
||||
|
||||
writel(LCDC_RASTER_TIMING_1_VBP(timing.vback_porch.typ) |
|
||||
LCDC_RASTER_TIMING_1_VFP(timing.vfront_porch.typ) |
|
||||
LCDC_RASTER_TIMING_1_VSW(timing.vsync_len.typ) |
|
||||
LCDC_RASTER_TIMING_1_VERLSB(timing.vactive.typ),
|
||||
®s->raster_timing1);
|
||||
|
||||
reg = LCDC_RASTER_TIMING_2_ACB(info.ac_bias) |
|
||||
LCDC_RASTER_TIMING_2_ACBI(info.ac_bias_intrpt) |
|
||||
LCDC_RASTER_TIMING_2_HSWMSB(timing.hsync_len.typ) |
|
||||
LCDC_RASTER_TIMING_2_VERMSB(timing.vactive.typ) |
|
||||
LCDC_RASTER_TIMING_2_HBPMSB(timing.hback_porch.typ) |
|
||||
LCDC_RASTER_TIMING_2_HFPMSB(timing.hfront_porch.typ);
|
||||
|
||||
if (timing.flags & DISPLAY_FLAGS_VSYNC_LOW)
|
||||
reg |= LCDC_RASTER_TIMING_2_VSYNC_INVERT;
|
||||
|
||||
if (timing.flags & DISPLAY_FLAGS_HSYNC_LOW)
|
||||
reg |= LCDC_RASTER_TIMING_2_HSYNC_INVERT;
|
||||
|
||||
if (info.invert_pxl_clk)
|
||||
reg |= LCDC_RASTER_TIMING_2_PXCLK_INVERT;
|
||||
|
||||
if (info.sync_edge)
|
||||
reg |= LCDC_RASTER_TIMING_2_HSVS_RISEFALL;
|
||||
|
||||
if (info.sync_ctrl)
|
||||
reg |= LCDC_RASTER_TIMING_2_HSVS_CONTROL;
|
||||
|
||||
writel(reg, ®s->raster_timing2);
|
||||
|
||||
reg = LCDC_RASTER_CTRL_PALMODE_RAWDATA | LCDC_RASTER_CTRL_TFT_MODE |
|
||||
LCDC_RASTER_CTRL_ENABLE | LCDC_RASTER_CTRL_REQDLY(info.fdd);
|
||||
|
||||
if (info.tft_alt_mode)
|
||||
reg |= LCDC_RASTER_CTRL_TFT_ALT_ENABLE;
|
||||
|
||||
if (info.bpp == 24)
|
||||
reg |= LCDC_RASTER_CTRL_TFT_24BPP_MODE;
|
||||
else if (info.bpp == 32)
|
||||
reg |= LCDC_RASTER_CTRL_TFT_24BPP_MODE |
|
||||
LCDC_RASTER_CTRL_TFT_24BPP_UNPACK;
|
||||
|
||||
if (info.raster_order)
|
||||
reg |= LCDC_RASTER_CTRL_DATA_ORDER;
|
||||
|
||||
writel(reg, ®s->raster_ctrl);
|
||||
|
||||
uc_priv->xsize = timing.hactive.typ;
|
||||
uc_priv->ysize = timing.vactive.typ;
|
||||
uc_priv->bpix = log_2_n_round_up(info.bpp);
|
||||
|
||||
err = panel_enable_backlight(panel);
|
||||
if (err) {
|
||||
dev_err(dev, "failed to enable panel backlight\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tilcdc_of_to_plat(struct udevice *dev)
|
||||
{
|
||||
struct tilcdc_priv *priv = dev_get_priv(dev);
|
||||
|
||||
priv->regs = (struct tilcdc_regs *)dev_read_addr(dev);
|
||||
if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) {
|
||||
dev_err(dev, "failed to get base address\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
dev_dbg(dev, "LCD: base address=0x%x\n", (unsigned int)priv->regs);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tilcdc_bind(struct udevice *dev)
|
||||
{
|
||||
struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
|
||||
|
||||
uc_plat->size = ((LCDC_MAX_WIDTH * LCDC_MAX_HEIGHT *
|
||||
(1 << LCDC_MAX_LOG2_BPP)) >> 3) + 0x20;
|
||||
|
||||
dev_dbg(dev, "frame buffer size 0x%x\n", uc_plat->size);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct udevice_id tilcdc_ids[] = {
|
||||
{.compatible = "ti,am33xx-tilcdc"},
|
||||
{}
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(tilcdc) = {
|
||||
.name = "tilcdc",
|
||||
.id = UCLASS_VIDEO,
|
||||
.of_match = tilcdc_ids,
|
||||
.bind = tilcdc_bind,
|
||||
.of_to_plat = tilcdc_of_to_plat,
|
||||
.probe = tilcdc_probe,
|
||||
.remove = tilcdc_remove,
|
||||
.priv_auto = sizeof(struct tilcdc_priv)
|
||||
};
|
||||
|
|
@ -1,38 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
|
||||
*/
|
||||
|
||||
#ifndef _TILCDC_H
|
||||
#define _TILCDC_H
|
||||
|
||||
/**
|
||||
* tilcdc_panel_info: Panel parameters
|
||||
*
|
||||
* @ac_bias: AC Bias Pin Frequency
|
||||
* @ac_bias_intrpt: AC Bias Pin Transitions per Interrupt
|
||||
* @dma_burst_sz: DMA burst size
|
||||
* @bpp: Bits per pixel
|
||||
* @fdd: FIFO DMA Request Delay
|
||||
* @tft_alt_mode: TFT Alternative Signal Mapping (Only for active)
|
||||
* @invert_pxl_clk: Invert pixel clock
|
||||
* @sync_edge: Horizontal and Vertical Sync Edge: 0=rising 1=falling
|
||||
* @sync_ctrl: Horizontal and Vertical Sync: Control: 0=ignore
|
||||
* @raster_order: Raster Data Order Select: 1=Most-to-least 0=Least-to-most
|
||||
* @fifo_th: DMA FIFO threshold
|
||||
*/
|
||||
struct tilcdc_panel_info {
|
||||
u32 ac_bias;
|
||||
u32 ac_bias_intrpt;
|
||||
u32 dma_burst_sz;
|
||||
u32 bpp;
|
||||
u32 fdd;
|
||||
bool tft_alt_mode;
|
||||
bool invert_pxl_clk;
|
||||
u32 sync_edge;
|
||||
u32 sync_ctrl;
|
||||
u32 raster_order;
|
||||
u32 fifo_th;
|
||||
};
|
||||
|
||||
#endif /* _TILCDC_H */
|
||||
Loading…
Reference in a new issue