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arm: mvebu: Don't disable cache at startup on Armada XP at all

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This patch leaces the cache configuration untouched for the AXP in the
setup done by the BootROM. Resulting in the cache still being enabled
at the startup of U-Boot. This leads to a slightly faster boot to the
U-Boot prompt (or Linux of course).

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
This commit is contained in:
Stefan Roese 2015-12-03 12:39:45 +01:00
parent e5f0a64034
commit c86d53fd88
1 changed files with 13 additions and 12 deletions
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25
arch/arm/mach-mvebu/cpu.c
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@ -246,13 +246,15 @@ int arch_cpu_init(void)
* in the macros / defines in the U-Boot header (soc.h).
*/
/*
* To fully release / unlock this area from cache, we need
* to flush all caches and disable the L2 cache.
*/
icache_disable();
dcache_disable();
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
if (mvebu_soc_family() == MVEBU_SOC_A38X) {
/*
* To fully release / unlock this area from cache, we need
* to flush all caches and disable the L2 cache.
*/
icache_disable();
dcache_disable();
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
}
/*
* We need to call mvebu_mbus_probe() before calling
@ -399,14 +401,13 @@ void enable_caches(void)
void v7_outer_cache_enable(void)
{
struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
/* The L2 cache is already disabled at this point */
if (mvebu_soc_family() == MVEBU_SOC_AXP) {
struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
u32 u;
/* The L2 cache is already disabled at this point */
/*
* For Aurora cache in no outer mode, enable via the CP15
* coprocessor broadcasting of cache commands to L2.