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This commit is contained in:
Tom Rini 2022-10-03 15:39:46 -04:00
commit 2d45913534
872 changed files with 26399 additions and 6425 deletions
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4
.azure-pipelines.yml
View file

@ -243,6 +243,9 @@ stages:
sandbox_clang:
TEST_PY_BD: "sandbox"
OVERRIDE: "-O clang-13"
sandbox_nolto:
TEST_PY_BD: "sandbox"
BUILD_ENV: "NO_LTO=1"
sandbox_spl:
TEST_PY_BD: "sandbox_spl"
TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
@ -354,6 +357,7 @@ stages:
export TEST_PY_ID="${TEST_PY_ID}"
export TEST_PY_TEST_SPEC="${TEST_PY_TEST_SPEC}"
export OVERRIDE="${OVERRIDE}"
export BUILD_ENV="${BUILD_ENV}"
EOF
cat << "EOF" >> test.sh
# the below corresponds to .gitlab-ci.yml "before_script"

7
.gitlab-ci.yml
View file

@ -33,6 +33,7 @@ stages:
script:
# If we've been asked to use clang only do one configuration.
- export UBOOT_TRAVIS_BUILD_DIR=/tmp/${TEST_PY_BD}
- echo BUILD_ENV ${BUILD_ENV}
- tools/buildman/buildman -o ${UBOOT_TRAVIS_BUILD_DIR} -w -E -W -e
--board ${TEST_PY_BD} ${OVERRIDE}
- cp ~/grub_x86.efi $UBOOT_TRAVIS_BUILD_DIR/
@ -254,6 +255,12 @@ sandbox with clang test.py:
OVERRIDE: "-O clang-13"
<<: *buildman_and_testpy_dfn
sandbox without LTO test.py:
variables:
TEST_PY_BD: "sandbox"
BUILD_ENV: "NO_LTO=1"
<<: *buildman_and_testpy_dfn
sandbox_spl test.py:
variables:
TEST_PY_BD: "sandbox_spl"

2
Kconfig
View file

@ -540,7 +540,7 @@ config PLATFORM_ELFENTRY
config STACK_SIZE
hex "Define max stack size that can be used by U-Boot"
default 0x4000000 if ARCH_VERSAL || ARCH_ZYNQMP
default 0x4000000 if ARCH_VERSAL_NET || ARCH_VERSAL || ARCH_ZYNQMP
default 0x200000 if MICROBLAZE
default 0x1000000
help

33
MAINTAINERS
View file

@ -356,20 +356,26 @@ F: doc/device-tree-bindings/phy/phy-mtk-*
F: doc/device-tree-bindings/usb/mediatek,*
F: doc/README.mediatek
F: drivers/clk/mediatek/
F: drivers/cpu/mtk_cpu.c
F: drivers/i2c/mtk_i2c.c
F: drivers/mmc/mtk-sd.c
F: drivers/phy/phy-mtk-*
F: drivers/pinctrl/mediatek/
F: drivers/power/domain/mtk-power-domain.c
F: drivers/ram/mediatek/
F: drivers/spi/mtk_snfi_spi.c
F: drivers/spi/mtk_spim.c
F: drivers/timer/mtk_timer.c
F: drivers/usb/host/xhci-mtk.c
F: drivers/usb/mtu3/
F: drivers/watchdog/mtk_wdt.c
F: drivers/net/mtk_eth.c
F: drivers/net/mtk_eth.h
F: drivers/reset/reset-mediatek.c
F: tools/mtk_image.c
F: tools/mtk_image.h
F: tools/mtk_nand_headers.c
F: tools/mtk_nand_headers.h
N: mediatek
ARM METHODE SUPPORT
@ -629,6 +635,13 @@ F: arch/arm/mach-uniphier/
F: configs/uniphier_*_defconfig
N: uniphier
ARM VERSAL NET
M: Michal Simek <michal.simek@amd.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
F: arch/arm/mach-versal-net/
N: (?<!uni)versal-net
ARM VERSAL
M: Michal Simek <michal.simek@amd.com>
S: Maintained
@ -725,6 +738,13 @@ S: Maintained
F: drivers/pci/pcie_phytium.c
F: arch/arm/dts/phytium-durian.dts
ASPEED FMC SPI DRIVER
M: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
M: Cédric Le Goater <clg@kaod.org>
R: Aspeed BMC SW team <BMC-SW@aspeedtech.com>
S: Maintained
F: drivers/spi/spi-aspeed-smc.c
BINMAN
M: Simon Glass <sjg@chromium.org>
M: Alper Nebi Yasak <alpernebiyasak@gmail.com>
@ -789,6 +809,13 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-coldfire.git
F: arch/m68k/
F: doc/arch/m68k.rst
CYCLIC
M: Stefan Roese <sr@denx.de>
S: Maintained
F: cmd/cyclic.c
F: common/cyclic.c
F: include/cyclic.h
DFU
M: Lukasz Majewski <lukma@denx.de>
S: Maintained
@ -1376,8 +1403,12 @@ F: configs/k2g_hs_evm_defconfig
F: configs/k2l_hs_evm_defconfig
F: configs/am65x_hs_evm_r5_defconfig
F: configs/am65x_hs_evm_a53_defconfig
F: configs/j721e_hs_evm_r5_defconfig
F: configs/j7200_hs_evm_a72_defconfig
F: configs/j7200_hs_evm_r5_defconfig
F: configs/j721e_hs_evm_a72_defconfig
F: configs/j721e_hs_evm_r5_defconfig
F: configs/j721s2_hs_evm_a72_defconfig
F: configs/j721s2_hs_evm_r5_defconfig
TPM DRIVERS
M: Ilias Apalodimas <ilias.apalodimas@linaro.org>

26
Makefile
View file

@ -521,8 +521,8 @@ env_h := include/generated/environment.h
no-dot-config-targets := clean clobber mrproper distclean \
help %docs check% coccicheck \
ubootversion backup tests check qcheck tcheck pylint \
pylint_err
ubootversion backup tests check pcheck qcheck tcheck \
pylint pylint_err
config-targets := 0
mixed-targets := 0
@ -643,6 +643,13 @@ export CFLAGS_EFI # Compiler flags to add when building EFI app
export CFLAGS_NON_EFI # Compiler flags to remove when building EFI app
export EFI_TARGET # binutils target if EFI is natively supported
export LTO_ENABLE
# This is y if LTO is enabled for this build. See NO_LTO=1 to disable LTO
ifeq ($(NO_LTO),)
LTO_ENABLE=$(if $(CONFIG_LTO),y)
endif
# If board code explicitly specified LDSCRIPT or CONFIG_SYS_LDSCRIPT, use
# that (or fail if absent). Otherwise, search for a linker script in a
# standard location.
@ -708,16 +715,16 @@ endif
LTO_CFLAGS :=
LTO_FINAL_LDFLAGS :=
export LTO_CFLAGS LTO_FINAL_LDFLAGS
ifdef CONFIG_LTO
ifeq ($(LTO_ENABLE),y)
ifeq ($(cc-name),clang)
LTO_CFLAGS += -flto
LTO_CFLAGS += -DLTO_ENABLE -flto
LTO_FINAL_LDFLAGS += -flto
AR = $(shell $(CC) -print-prog-name=llvm-ar)
NM = $(shell $(CC) -print-prog-name=llvm-nm)
else
NPROC := $(shell nproc 2>/dev/null || echo 1)
LTO_CFLAGS += -flto=$(NPROC)
LTO_CFLAGS += -DLTO_ENABLE -flto=$(NPROC)
LTO_FINAL_LDFLAGS += -fuse-linker-plugin -flto=$(NPROC)
# use plugin aware tools
@ -1467,6 +1474,7 @@ endif
u-boot-spl.kwb: u-boot.bin spl/u-boot-spl.bin FORCE
$(call if_changed,mkimage)
$(BOARD_SIZE_CHECK)
u-boot.sha1: u-boot.bin
tools/ubsha1 u-boot.bin
@ -1724,7 +1732,7 @@ ARCH_POSTLINK := $(wildcard $(srctree)/arch/$(ARCH)/Makefile.postlink)
# Generate linker list symbols references to force compiler to not optimize
# them away when compiling with LTO
ifdef CONFIG_LTO
ifeq ($(LTO_ENABLE),y)
u-boot-keep-syms-lto := keep-syms-lto.o
u-boot-keep-syms-lto_c := $(patsubst %.o,%.c,$(u-boot-keep-syms-lto))
@ -1746,7 +1754,7 @@ endif
# Rule to link u-boot
# May be overridden by arch/$(ARCH)/config.mk
ifdef CONFIG_LTO
ifeq ($(LTO_ENABLE),y)
quiet_cmd_u-boot__ ?= LTO $@
cmd_u-boot__ ?= \
$(CC) -nostdlib -nostartfiles \
@ -2318,6 +2326,7 @@ help:
@echo 'Test targets:'
@echo ''
@echo ' check - Run all automated tests that use sandbox'
@echo ' pcheck - Run quick automated tests in parallel'
@echo ' qcheck - Run quick automated tests that use sandbox'
@echo ' tcheck - Run quick automated tests on tools'
@echo ' pylint - Run pylint on all Python files'
@ -2363,6 +2372,9 @@ help:
tests check:
$(srctree)/test/run
pcheck:
$(srctree)/test/run parallel
qcheck:
$(srctree)/test/run quick

2
README
View file

@ -415,8 +415,6 @@ The following options need to be configured:
the defaults discussed just above.
- Cache Configuration for ARM:
CONFIG_SYS_L2_PL310 - Enable support for ARM PL310 L2 cache
controller
CONFIG_SYS_PL310_BASE - Physical base address of PL310
controller register space

2
arch/Kconfig
View file

@ -146,7 +146,6 @@ config SANDBOX
select DM_SPI
select DM_SPI_FLASH
select GZIP_COMPRESSED
select HAVE_BLOCK_DEVICE
select LZO
select OF_BOARD_SETUP
select PCI_ENDPOINT
@ -167,7 +166,6 @@ config SANDBOX
imply CMD_IO
imply CMD_IOTRACE
imply CMD_LZMADEC
imply CMD_SATA
imply CMD_SF
imply CMD_SF_TEST
imply CRC32_VERIFY

8
arch/arc/lib/bootm.c
View file

@ -22,10 +22,10 @@ static int cleanup_before_linux(void)
return 0;
}
__weak int board_prep_linux(bootm_headers_t *images) { return 0; }
__weak int board_prep_linux(struct bootm_headers *images) { return 0; }
/* Subcommand: PREP */
static int boot_prep_linux(bootm_headers_t *images)
static int boot_prep_linux(struct bootm_headers *images)
{
int ret;
@ -49,7 +49,7 @@ __weak void board_jump_and_run(ulong entry, int zero, int arch, uint params)
}
/* Subcommand: GO */
static void boot_jump_linux(bootm_headers_t *images, int flag)
static void boot_jump_linux(struct bootm_headers *images, int flag)
{
ulong kernel_entry;
unsigned int r0, r2;
@ -79,7 +79,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
board_jump_and_run(kernel_entry, r0, 0, r2);
}
int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
int do_bootm_linux(int flag, int argc, char *argv[], struct bootm_headers *images)
{
/* No need for those on ARC */
if ((flag & BOOTM_STATE_OS_BD_T) || (flag & BOOTM_STATE_OS_CMDLINE))

32
arch/arm/Kconfig
View file

@ -488,6 +488,15 @@ config TPL_SYS_THUMB_BUILD
density. For ARM architectures that support Thumb2 this flag will
result in Thumb2 code generated by GCC.
config SYS_L2_PL310
bool "ARM PL310 L2 cache controller"
help
Enable support for ARM PL310 L2 cache controller in U-Boot
config SPL_SYS_L2_PL310
bool "ARM PL310 L2 cache controller in SPL"
help
Enable support for ARM PL310 L2 cache controller in SPL
config SYS_L2CACHE_OFF
bool "L2cache off"
@ -618,6 +627,7 @@ config ARCH_KIRKWOOD
select BOARD_EARLY_INIT_F
select CPU_ARM926EJS
select GPIO_EXTRA_HEADER
select TIMER
config ARCH_MVEBU
bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
@ -629,6 +639,8 @@ config ARCH_MVEBU
select GPIO_EXTRA_HEADER
select SPL_DM_SPI if SPL
select SPL_DM_SPI_FLASH if SPL
select SPL_TIMER if SPL
select TIMER
select OF_CONTROL
select OF_SEPARATE
select SPI
@ -639,6 +651,7 @@ config ARCH_ORION5X
select CPU_ARM926EJS
select GPIO_EXTRA_HEADER
select SPL_SEPARATE_BSS if SPL
select TIMER
config TARGET_STV0991
bool "Support stv0991"
@ -989,6 +1002,7 @@ config ARCH_MX6
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
select SYS_L2_PL310 if !SYS_L2CACHE_OFF
imply MXC_GPIO
imply SYS_THUMB_BUILD
imply SPL_SEPARATE_BSS
@ -1016,7 +1030,6 @@ config ARCH_NPCM
config ARCH_APPLE
bool "Apple SoCs"
select ARM64
select BLK
select CLK
select CMD_USB
select DM
@ -1238,6 +1251,18 @@ config ARCH_VERSAL
imply BOARD_LATE_INIT
imply ENV_VARS_UBOOT_RUNTIME_CONFIG
config ARCH_VERSAL_NET
bool "Support Xilinx Keystone Platform"
select ARM64
select CLK
select DM
select DM_ETH if NET
select DM_MMC if MMC
select DM_SERIAL
select OF_CONTROL
imply BOARD_LATE_INIT
imply ENV_VARS_UBOOT_RUNTIME_CONFIG
config ARCH_VF610
bool "Freescale Vybrid"
select CPU_V7A
@ -1249,6 +1274,7 @@ config ARCH_VF610
config ARCH_ZYNQ
bool "Xilinx Zynq based platform"
select ARM_TWD_TIMER
select CLK
select CLK_ZYNQ
select CPU_V7A
@ -1268,7 +1294,9 @@ config ARCH_ZYNQ
select SPL_DM_SPI_FLASH if SPL
select SPL_OF_CONTROL if SPL
select SPL_SEPARATE_BSS if SPL
select SPL_TIMER if SPL
select SUPPORT_SPL
select TIMER
imply ARCH_EARLY_INIT_R
imply BOARD_LATE_INIT
imply CMD_CLK
@ -2284,6 +2312,8 @@ source "arch/arm/mach-zynqmp/Kconfig"
source "arch/arm/mach-versal/Kconfig"
source "arch/arm/mach-versal-net/Kconfig"
source "arch/arm/mach-zynqmp-r5/Kconfig"
source "arch/arm/cpu/armv7/Kconfig"

1
arch/arm/Makefile
View file

@ -88,6 +88,7 @@ machine-$(CONFIG_ARCH_OCTEONTX) += octeontx
machine-$(CONFIG_ARCH_OCTEONTX2) += octeontx2
machine-$(CONFIG_ARCH_UNIPHIER) += uniphier
machine-$(CONFIG_ARCH_VERSAL) += versal
machine-$(CONFIG_ARCH_VERSAL_NET) += versal-net
machine-$(CONFIG_ARCH_ZYNQ) += zynq
machine-$(CONFIG_ARCH_ZYNQMP) += zynqmp
machine-$(CONFIG_ARCH_ZYNQMP_R5) += zynqmp-r5

4
arch/arm/config.mk
View file

@ -15,11 +15,11 @@ CFLAGS_NON_EFI := -fno-pic -ffixed-r9 -ffunction-sections -fdata-sections \
-fstack-protector-strong
CFLAGS_EFI := -fpic -fshort-wchar
ifneq ($(CONFIG_LTO)$(CONFIG_USE_PRIVATE_LIBGCC),yy)
ifneq ($(LTO_ENABLE)$(CONFIG_USE_PRIVATE_LIBGCC),yy)
LDFLAGS_FINAL += --gc-sections
endif
ifndef CONFIG_LTO
ifneq ($(LTO_ENABLE),y)
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
endif

20
arch/arm/dts/Makefile
View file

@ -233,8 +233,11 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
tegra210-p3450-0000.dtb
ifdef CONFIG_ARMADA_32BIT
ifdef CONFIG_ARMADA_375
dtb-$(CONFIG_ARCH_MVEBU) += \
armada-375-db.dtb
else
dtb-$(CONFIG_ARCH_MVEBU) += \
armada-375-db.dtb \
armada-385-atl-x530.dtb \
armada-385-atl-x530DP.dtb \
armada-385-db-88f6820-amc.dtb \
@ -254,6 +257,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
armada-xp-maxbcm.dtb \
armada-xp-synology-ds414.dtb \
armada-xp-theadorable.dtb
endif
else
dtb-$(CONFIG_ARCH_MVEBU) += \
armada-3720-db.dtb \
@ -379,6 +383,9 @@ dtb-$(CONFIG_ARCH_VERSAL) += \
versal-mini-emmc0.dtb \
versal-mini-emmc1.dtb \
xilinx-versal-virt.dtb
dtb-$(CONFIG_ARCH_VERSAL_NET) += \
versal-net-mini.dtb \
xilinx-versal-net-virt.dtb
dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \
zynqmp-r5.dtb
dtb-$(CONFIG_AM33XX) += \
@ -388,8 +395,6 @@ dtb-$(CONFIG_AM33XX) += \
am335x-boneblack-wireless.dtb \
am335x-boneblue.dtb \
am335x-brppt1-mmc.dtb \
am335x-brppt1-nand.dtb \
am335x-brppt1-spi.dtb \
am335x-brxre1.dtb \
am335x-brsmarc1.dtb \
am335x-draco.dtb \
@ -1233,6 +1238,15 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7622-bananapi-bpi-r64.dtb \
mt7623n-bananapi-bpi-r2.dtb \
mt7629-rfb.dtb \
mt7981-rfb.dtb \
mt7981-emmc-rfb.dtb \
mt7981-sd-rfb.dtb \
mt7986a-rfb.dtb \
mt7986b-rfb.dtb \
mt7986a-sd-rfb.dtb \
mt7986b-sd-rfb.dtb \
mt7986a-emmc-rfb.dtb \
mt7986b-emmc-rfb.dtb \
mt8183-pumpkin.dtb \
mt8512-bm1-emmc.dtb \
mt8516-pumpkin.dtb \

112
arch/arm/dts/am335x-brppt1-mmc-u-boot.dtsi Normal file
View file

@ -0,0 +1,112 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2022 B&R Industrial Automation GmbH -
* https://www.br-automation.com/
*/
/ {
ocp {
u-boot,dm-pre-reloc;
};
};
&l4_wkup {
u-boot,dm-pre-reloc;
segment@200000 {
u-boot,dm-pre-reloc;
target-module@0
{
u-boot,dm-pre-reloc;
compatible = "simple-bus";
};
target-module@7000 {
u-boot,dm-pre-reloc;
compatible = "simple-bus";
};
target-module@9000 {
u-boot,dm-pre-reloc;
compatible = "simple-bus";
};
};
};
&wkup_cm {
u-boot,dm-pre-reloc;
};
&l4_wkup_clkctrl {
u-boot,dm-pre-reloc;
};
&l4_per {
u-boot,dm-pre-reloc;
segment@0 {
u-boot,dm-pre-reloc;
compatible = "simple-bus";
target-module@4c000 {
u-boot,dm-pre-reloc;
compatible = "simple-bus";
};
};
segment@100000 {
u-boot,dm-pre-reloc;
compatible = "simple-bus";
target-module@ac000 {
u-boot,dm-pre-reloc;
compatible = "simple-bus";
};
target-module@ae000 {
u-boot,dm-pre-reloc;
compatible = "simple-bus";
};
};
};
&prcm {
u-boot,dm-pre-reloc;
};
&gpio0_target {
u-boot,dm-pre-reloc;
};
&prcm_clocks {
compatible = "simple-bus";
};
&scm_clocks {
compatible = "simple-bus";
};
&i2c0 {
u-boot,dm-pre-reloc;
};
&uart0 {
u-boot,dm-pre-reloc;
};
&mmc1 {
u-boot,dm-pre-reloc;
};
&mmc2 {
u-boot,dm-pre-reloc;
};
&gpio0 {
u-boot,dm-pre-reloc;
};
&gpio1 {
u-boot,dm-pre-reloc;
};
&gpio2 {
u-boot,dm-pre-reloc;
};
&gpio3 {
u-boot,dm-pre-reloc;
};

201
arch/arm/dts/am335x-brppt1-mmc.dts
View file

@ -12,25 +12,10 @@
model = "BRPPT1 (MMC) Panel";
compatible = "ti,am33xx";
fset: factory-settings {
bl-version = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456890";
version = <0x0100>;
order-no = "6PPT30 (MMC)";
hw-revision = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456890";
serial-no = "0";
device-id = <0x0>;
parent-id = <0x0>;
hw-variant = <0x1>;
};
aliases {
ds1bkl0 = &pwmbacklight;
ds1bkl1 = &tps_bl;
ds1timing = &timing0;
ds1ctrl = &lcdc;
gpmc = &gpmc;
mmc = &mmc2;
fset = &fset;
};
chosen {
@ -43,110 +28,21 @@
reg = <0x80000000 0x10000000>; /* 256 MB */
};
panel {
status = "disabled";
compatible = "ti,tilcdc,panel";
enable-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
backlight = <&pwmbacklight>;
bkl-pwm = <&pwmbacklight>;
bkl-tps = <&tps_bl>;
panel-info {
ac-bias = <255>;
ac-bias-intrpt = <0>;
dma-burst-sz = <16>;
bpp = <32>;
fdd = <0x80>;
sync-edge = <0>;
sync-ctrl = <1>;
raster-order = <0>;
fifo-th = <0>;
};
display-timings {
native-mode = <&timing0>;
timing0: lcd {
clock-frequency = <32000000>;
hactive = <800>;
vactive = <480>;
hfront-porch = <2>;
hback-porch = <192>;
hsync-len = <1>;
vfront-porch = <20>;
vback-porch = <2>;
vsync-len = <1>;
hsync-active = <1>;
vsync-active = <1>;
pupdelay = <10>;
pondelay = <10>;
};
};
};
vmmcsd_fixed: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "vmmcsd_fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
pwm0: omap-pwm@timer5 {
compatible = "ti,omap-dmtimer-pwm";
ti,timers = <&timer5>;
#pwm-cells = <3>;
};
pwm1: omap-pwm@timer6 {
compatible = "ti,omap-dmtimer-pwm";
ti,timers = <&timer6>;
#pwm-cells = <3>;
};
beeper: pwm-beep {
compatible = "pwm-beeper";
pwms = <&pwm0 0 0 0>;
};
pwmbacklight: pwm-bkl {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000 0>;
default-brightness-level = <255>;
brightness-levels = <0 16 32 64 128 170 202 234 255>;
power-supply = <&vmmcsd_fixed>;
enable-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
};
};
&uart0 { /* console uart */
u-boot,dm-spl;
status = "okay";
};
&uart1 {
status = "okay";
};
&i2c0 {
u-boot,dm-spl;
status = "okay";
clock-frequency = <400000>;
tps: tps@24 { /* PMIC controller */
u-boot,dm-spl;
reg = <0x24>;
compatible = "ti,tps65217";
tps_bl: backlight {
compatible = "ti,tps65217-bl";
isel = <1>; /* 1 - ISET1, 2 ISET2 */
fdim = <1000>; /* TPS65217_BL_FDIM_1kHZ */
default-brightness = <50>;
};
};
};
&i2c2 {
@ -158,10 +54,6 @@
status = "okay";
};
&cppi41dma {
status = "okay";
};
&usb {
status = "okay";
};
@ -217,7 +109,6 @@
};
&mmc1 {
u-boot,dm-spl;
vmmc-supply = <&vmmcsd_fixed>;
bus-width = <0x4>;
ti,non-removable;
@ -227,7 +118,6 @@
};
&mmc2 {
u-boot,dm-spl;
vmmc-supply = <&vmmcsd_fixed>;
bus-width = <0x8>;
ti,non-removable;
@ -236,79 +126,22 @@
status = "okay";
};
&l4_per {
segment@300000 {
target-module@e000 {
u-boot,dm-pre-reloc;
lcdc: lcdc@0 {
u-boot,dm-pre-reloc;
status = "disabled";
};
};
};
};
&elm {
status = "okay";
};
&sham {
status = "okay";
};
&aes {
status = "okay";
};
&gpio0 {
u-boot,dm-spl;
ti,no-reset-on-init;
};
&gpio1 {
u-boot,dm-spl;
ti,no-reset-on-init;
};
&gpio2 {
u-boot,dm-spl;
ti,no-reset-on-init;
};
&gpio3 {
u-boot,dm-spl;
ti,no-reset-on-init;
};
&wdt2 {
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&tscadc {
status = "okay";
tsc {
ti,wires = <4>;
ti,x-plate-resistance = <200>;
ti,zx-cutoff-ratio = <40>;
ti,min_deviation = <60>;
ti,max_deviation = <600>;
ti,coordinate-readouts = <5>;
ti,wire-config = <0x00 0x11 0x22 0x33>;
bnr-buttons {
Home-Button {};
};
};
adc {
ti,adc-channels = <5 6 7>;
};
};
&timer6 { /* used for cpsw end device */
status = "okay";
ti,no-reset-on-init;
@ -320,37 +153,3 @@
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&wdt2 {
status = "okay";
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&epwmss0 {
status = "okay";
};
&tscadc {
status = "okay";
};
&dcan0 {
status = "okay";
};
&dcan1 {
status = "okay";
};
&sham {
status = "disabled";
};
&aes {
status = "disabled";
};
&rng {
status = "disabled";
};

374
arch/arm/dts/am335x-brppt1-nand.dts
View file

@ -1,374 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 B&R Industrial Automation GmbH
* http://www.br-automation.com
*
*/
/dts-v1/;
#include "am33xx.dtsi"
/ {
model = "BRPPT1 (NAND) Panel";
compatible = "ti,am33xx";
fset: factory-settings {
bl-version = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456890";
version = <0x0100>;
order-no = "6PPT30 (NAND)";
hw-revision = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456890";
serial-no = "0";
device-id = <0x0>;
parent-id = <0x0>;
hw-variant = <0x1>;
};
aliases {
ds1bkl0 = &pwmbacklight;
ds1bkl1 = &tps_bl;
ds1timing = &timing0;
ds1ctrl = &lcdc;
gpmc = &gpmc;
mmc = &mmc2;
fset = &fset;
};
chosen {
bootargs = "console=ttyO0,115200 earlyprintk";
stdout-path = &uart0;
};
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
};
panel {
status = "disabled";
compatible = "ti,tilcdc,panel";
enable-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
backlight = <&pwmbacklight>;
bkl-pwm = <&pwmbacklight>;
bkl-tps = <&tps_bl>;
panel-info {
ac-bias = <255>;
ac-bias-intrpt = <0>;
dma-burst-sz = <16>;
bpp = <32>;
fdd = <0x80>;
sync-edge = <0>;
sync-ctrl = <1>;
raster-order = <0>;
fifo-th = <0>;
};
display-timings {
native-mode = <&timing0>;
timing0: lcd {
clock-frequency = <32000000>;
hactive = <800>;
vactive = <480>;
hfront-porch = <2>;
hback-porch = <192>;
hsync-len = <1>;
vfront-porch = <20>;
vback-porch = <2>;
vsync-len = <1>;
hsync-active = <1>;
vsync-active = <1>;
pupdelay = <10>;
pondelay = <10>;
};
};
};
vmmcsd_fixed: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "vmmcsd_fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
pwm0: omap-pwm@timer5 {
compatible = "ti,omap-dmtimer-pwm";
ti,timers = <&timer5>;
#pwm-cells = <3>;
};
pwm1: omap-pwm@timer6 {
compatible = "ti,omap-dmtimer-pwm";
ti,timers = <&timer6>;
#pwm-cells = <3>;
};
beeper: pwm-beep {
compatible = "pwm-beeper";
pwms = <&pwm0 0 0 0>;
};
pwmbacklight: pwm-bkl {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000 0>;
default-brightness-level = <255>;
brightness-levels = <0 16 32 64 128 170 202 234 255>;
power-supply = <&vmmcsd_fixed>;
enable-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
};
};
&uart0 { /* console uart */
u-boot,dm-spl;
status = "okay";
};
&uart1 {
status = "okay";
};
&i2c0 {
u-boot,dm-spl;
status = "okay";
clock-frequency = <400000>;
tps: tps@24 { /* PMIC controller */
u-boot,dm-spl;
reg = <0x24>;
compatible = "ti,tps65217";
tps_bl: backlight {
compatible = "ti,tps65217-bl";
isel = <1>; /* 1 - ISET1, 2 ISET2 */
fdim = <1000>; /* TPS65217_BL_FDIM_1kHZ */
default-brightness = <50>;
};
};
};
&i2c2 {
status = "okay";
clock-frequency = <100000>;
};
&edma {
status = "okay";
};
&cppi41dma {
status = "okay";
};
&usb {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb0_phy {
status = "okay";
};
&usb1_phy {
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";
};
&usb1 {
status = "okay";
dr_mode = "host";
};
&davinci_mdio {
status = "okay";
phy0: ethernet-phy@0 {
reg = <1>;
};
phy1: ethernet-phy@1 {
reg = <2>;
};
};
&mac {
dual_emac;
status = "okay";
};
&cpsw_emac0 {
phy-handle = <&phy0>;
dual_emac_res_vlan = <1>;
phy-mode = "mii";
};
&cpsw_emac1 {
phy-handle = <&phy1>;
dual_emac_res_vlan = <2>;
phy-mode = "mii";
};
&mmc2 {
vmmc-supply = <&vmmcsd_fixed>;
bus-width = <0x4>;
ti,non-removable;
ti,needs-special-hs-handling;
ti,vcc-aux-disable-is-sleep;
status = "disabled";
};
&l4_per {
segment@300000 {
target-module@e000 {
u-boot,dm-pre-reloc;
lcdc: lcdc@0 {
u-boot,dm-pre-reloc;
status = "disabled";
};
};
};
};
&elm {
status = "okay";
};
&sham {
status = "okay";
};
&aes {
status = "okay";
};
&gpio0 {
u-boot,dm-spl;
ti,no-reset-on-init;
};
&gpio1 {
u-boot,dm-spl;
ti,no-reset-on-init;
};
&gpio2 {
u-boot,dm-spl;
ti,no-reset-on-init;
};
&gpio3 {
u-boot,dm-spl;
ti,no-reset-on-init;
};
&wdt2 {
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&tscadc {
status = "okay";
tsc {
ti,wires = <4>;
ti,x-plate-resistance = <200>;
ti,zx-cutoff-ratio = <40>;
ti,min_deviation = <60>;
ti,max_deviation = <600>;
ti,coordinate-readouts = <5>;
ti,wire-config = <0x00 0x11 0x22 0x33>;
bnr-buttons {
Home-Button {};
};
};
adc {
ti,adc-channels = <5 6 7>;
};
};
&gpmc {
u-boot,dm-spl;
status = "okay";
pinctrl-names = "default";
ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
interrupt-parent = <&gpmc>;
rb-gpios = <&gpmc 1 GPIO_ACTIVE_HIGH>; /* gpmc_wait1 */
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <44>;
gpmc,cs-wr-off-ns = <44>;
gpmc,adv-on-ns = <6>;
gpmc,adv-rd-off-ns = <34>;
gpmc,adv-wr-off-ns = <44>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <40>;
gpmc,oe-on-ns = <0>;
gpmc,oe-off-ns = <54>;
gpmc,access-ns = <64>;
gpmc,rd-cycle-ns = <82>;
gpmc,wr-cycle-ns = <82>;
gpmc,wait-on-read = "true";
gpmc,wait-on-write = "true";
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wait-monitoring-ns = <0>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
gpmc,wait-pin = <1>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "NAND.MLO";
reg = <0x00000000 0x000020000>;
};
partition@1 {
label = "NAND.cfgscr";
reg = <0x00020000 0x00020000>;
};
partition@2 {
label = "NAND.dtb";
reg = <0x00040000 0x00020000>;
};
partition@3 {
label = "NAND.u-boot-env";
reg = <0x00060000 0x00020000>;
};
partition@4 {
label = "NAND.u-boot";
reg = <0x00080000 0x00080000>;
};
partition@5 {
label = "NAND.kernel";
reg = <0x00100000 0x00400000>;
};
partition@6 {
label = "NAND.rootfs";
reg = <0x00500000 0x08000000>;
};
partition@7 {
label = "NAND.user";
reg = <0x08500000 0x17b00000>;
};
};
};

377
arch/arm/dts/am335x-brppt1-spi.dts
View file

@ -1,377 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 B&R Industrial Automation GmbH
* http://www.br-automation.com
*
*/
/dts-v1/;
#include "am33xx.dtsi"
/ {
model = "BRPPT1 (MMC) Panel";
compatible = "ti,am33xx";
fset: factory-settings {
bl-version = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456890";
version = <0x0100>;
order-no = "6PPT30 (SPI)";
hw-revision = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456890";
serial-no = "0";
device-id = <0x0>;
parent-id = <0x0>;
hw-variant = <0x1>;
};
aliases {
ds1bkl0 = &pwmbacklight;
ds1bkl1 = &tps_bl;
ds1timing = &timing0;
ds1ctrl = &lcdc;
gpmc = &gpmc;
mmc = &mmc2;
spi0 = &spi0;
fset = &fset;
};
chosen {
bootargs = "console=ttyO0,115200 earlyprintk";
stdout-path = &uart0;
};
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
};
panel {
status = "disabled";
compatible = "ti,tilcdc,panel";
enable-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
backlight = <&pwmbacklight>;
bkl-pwm = <&pwmbacklight>;
bkl-tps = <&tps_bl>;
panel-info {
ac-bias = <255>;
ac-bias-intrpt = <0>;
dma-burst-sz = <16>;
bpp = <32>;
fdd = <0x80>;
sync-edge = <0>;
sync-ctrl = <1>;
raster-order = <0>;
fifo-th = <0>;
};
display-timings {
native-mode = <&timing0>;
timing0: lcd {
clock-frequency = <32000000>;
hactive = <800>;
vactive = <480>;
hfront-porch = <2>;
hback-porch = <192>;
hsync-len = <1>;
vfront-porch = <20>;
vback-porch = <2>;
vsync-len = <1>;
hsync-active = <1>;
vsync-active = <1>;
pupdelay = <10>;
pondelay = <10>;
};
};
};
vmmcsd_fixed: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "vmmcsd_fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
pwm0: omap-pwm@timer5 {
compatible = "ti,omap-dmtimer-pwm";
ti,timers = <&timer5>;
#pwm-cells = <3>;
};
pwm1: omap-pwm@timer6 {
compatible = "ti,omap-dmtimer-pwm";
ti,timers = <&timer6>;
#pwm-cells = <3>;
};
beeper: pwm-beep {
compatible = "pwm-beeper";
pwms = <&pwm0 0 0 0>;
};
pwmbacklight: pwm-bkl {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000 0>;
default-brightness-level = <255>;
brightness-levels = <0 16 32 64 128 170 202 234 255>;
power-supply = <&vmmcsd_fixed>;
enable-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
};
};
&uart0 { /* console uart */
u-boot,dm-spl;
status = "okay";
};
&uart1 {
status = "okay";
};
&i2c0 {
u-boot,dm-spl;
status = "okay";
clock-frequency = <400000>;
tps: tps@24 { /* PMIC controller */
u-boot,dm-spl;
reg = <0x24>;
compatible = "ti,tps65217";
tps_bl: backlight {
compatible = "ti,tps65217-bl";
isel = <1>; /* 1 - ISET1, 2 ISET2 */
fdim = <1000>; /* TPS65217_BL_FDIM_1kHZ */
default-brightness = <50>;
};
};
};
&i2c2 {
status = "okay";
clock-frequency = <100000>;
};
&spi0 {
u-boot,dm-spl;
status = "okay";
cs-gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>,
<&gpio0 6 GPIO_ACTIVE_HIGH>,
<0>,
<0>;
spi-max-frequency = <24000000>;
spi_flash: spiflash@0 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
compatible = "spidev", "jedec,spi-nor";
spi-max-frequency = <24000000>;
reg = <0>;
};
};
&edma {
status = "okay";
};
&cppi41dma {
status = "okay";
};
&usb {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb0_phy {
status = "okay";
};
&usb1_phy {
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";
};
&usb1 {
status = "okay";
dr_mode = "host";
};
&davinci_mdio {
status = "okay";
phy0: ethernet-phy@0 {
reg = <1>;
};
phy1: ethernet-phy@1 {
reg = <2>;
};
};
&mac {
status = "okay";
};
&cpsw_emac0 {
phy-handle = <&phy0>;
dual_emac_res_vlan = <1>;
phy-mode = "mii";
};
&cpsw_emac1 {
phy-handle = <&phy1>;
dual_emac_res_vlan = <2>;
phy-mode = "mii";
};
&mmc1 {
u-boot,dm-spl;
vmmc-supply = <&vmmcsd_fixed>;
bus-width = <0x4>;
ti,non-removable;
ti,needs-special-hs-handling;
ti,vcc-aux-disable-is-sleep;
status = "okay";
};
&mmc2 {
u-boot,dm-spl;
vmmc-supply = <&vmmcsd_fixed>;
bus-width = <0x8>;
ti,non-removable;
ti,needs-special-hs-handling;
ti,vcc-aux-disable-is-sleep;
status = "okay";
};
&l4_per {
segment@300000 {
target-module@e000 {
u-boot,dm-pre-reloc;
lcdc: lcdc@0 {
u-boot,dm-pre-reloc;
status = "disabled";
};
};
};
};
&elm {
status = "okay";
};
&sham {
status = "okay";
};
&aes {
status = "okay";
};
&gpio0 {
u-boot,dm-spl;
ti,no-reset-on-init;
};
&gpio1 {
u-boot,dm-spl;
ti,no-reset-on-init;
};
&gpio2 {
u-boot,dm-spl;
ti,no-reset-on-init;
};
&gpio3 {
u-boot,dm-spl;
ti,no-reset-on-init;
};
&wdt2 {
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&tscadc {
status = "okay";
tsc {
ti,wires = <4>;
ti,x-plate-resistance = <200>;
ti,zx-cutoff-ratio = <40>;
ti,min_deviation = <60>;
ti,max_deviation = <600>;
ti,coordinate-readouts = <5>;
ti,wire-config = <0x00 0x11 0x22 0x33>;
bnr-buttons {
Home-Button {};
};
};
adc {
ti,adc-channels = <5 6 7>;
};
};
&timer6 { /* used for cpsw end device */
status = "okay";
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&timer7 { /* used for cpsw end device */
status = "okay";
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&wdt2 {
status = "okay";
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&epwmss0 {
status = "okay";
};
&tscadc {
status = "okay";
};
&dcan0 {
status = "okay";
};
&dcan1 {
status = "okay";
};
&sham {
status = "disabled";
};
&aes {
status = "disabled";
};
&rng {
status = "disabled";
};

4
arch/arm/dts/armada-375.dtsi
View file

@ -187,7 +187,7 @@
reg = <0xc000 0x58>;
};
timer@c600 {
timer0: timer@c600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xc600 0x20>;
interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
@ -416,7 +416,7 @@
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
timer@20300 {
timer1: timer@20300 {
compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
reg = <0x20300 0x30>, <0x21040 0x30>;
interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,

27
arch/arm/dts/armada-xp-theadorable.dts
View file

@ -107,20 +107,6 @@
status = "okay";
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
reg = <0>;
};
};
ethernet@70000 {
status = "okay";
phy = <&phy0>;
phy-mode = "sgmii";
};
usb@50000 {
status = "okay";
};
@ -166,6 +152,18 @@
clock-frequency = <100000>;
};
&mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
};
&eth0 {
status = "okay";
phy = <&phy0>;
phy-mode = "sgmii";
};
&spi0 {
status = "okay";
@ -198,7 +196,6 @@
};
};
&pciec {
status = "okay";

33
arch/arm/dts/ast2500-evb.dts
View file

@ -78,6 +78,39 @@
pinctrl-0 = <&pinctrl_sd2_default>;
};
&fmc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fwspics1_default>;
flash@0 {
status = "okay";
spi-max-frequency = <50000000>;
spi-tx-bus-width = <2>;
spi-rx-bus-width = <2>;
};
flash@1 {
status = "okay";
spi-max-frequency = <50000000>;
spi-tx-bus-width = <2>;
spi-rx-bus-width = <2>;
};
};
&spi1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1cs1_default>;
flash@0 {
status = "okay";
spi-max-frequency = <50000000>;
spi-tx-bus-width = <2>;
spi-rx-bus-width = <2>;
};
};
&i2c3 {
status = "okay";

23
arch/arm/dts/ast2500.dtsi
View file

@ -57,23 +57,26 @@
ranges;
fmc: flash-controller@1e620000 {
reg = < 0x1e620000 0xc4
0x20000000 0x10000000 >;
reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-fmc";
clocks = <&scu ASPEED_CLK_AHB>;
num-cs = <3>;
status = "disabled";
interrupts = <19>;
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
flash@2 {
reg = < 2 >;
compatible = "jedec,spi-nor";
@ -82,17 +85,20 @@
};
spi1: flash-controller@1e630000 {
reg = < 0x1e630000 0xc4
0x30000000 0x08000000 >;
reg = <0x1e630000 0xc4>, <0x30000000 0x08000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-spi";
clocks = <&scu ASPEED_CLK_AHB>;
num-cs = <2>;
status = "disabled";
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
@ -101,17 +107,20 @@
};
spi2: flash-controller@1e631000 {
reg = < 0x1e631000 0xc4
0x38000000 0x08000000 >;
reg = <0x1e631000 0xc4>, <0x38000000 0x08000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-spi";
clocks = <&scu ASPEED_CLK_AHB>;
num-cs = <2>;
status = "disabled";
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";

8
arch/arm/dts/ast2600-evb.dts
View file

@ -72,12 +72,10 @@
&fmc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fmcquad_default>;
flash@0 {
compatible = "spi-flash", "sst,w25q256";
status = "okay";
spi-max-frequency = <50000000>;
spi-tx-bus-width = <4>;
@ -85,7 +83,6 @@
};
flash@1 {
compatible = "spi-flash", "sst,w25q256";
status = "okay";
spi-max-frequency = <50000000>;
spi-tx-bus-width = <4>;
@ -93,7 +90,6 @@
};
flash@2 {
compatible = "spi-flash", "sst,w25q256";
status = "okay";
spi-max-frequency = <50000000>;
spi-tx-bus-width = <4>;
@ -103,14 +99,12 @@
&spi1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1_default &pinctrl_spi1abr_default
&pinctrl_spi1cs1_default &pinctrl_spi1wp_default
&pinctrl_spi1wp_default &pinctrl_spi1quad_default>;
flash@0 {
compatible = "spi-flash", "sst,w25q256";
status = "okay";
spi-max-frequency = <50000000>;
spi-tx-bus-width = <4>;
@ -120,13 +114,11 @@
&spi2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2_default &pinctrl_spi2cs1_default
&pinctrl_spi2cs2_default &pinctrl_spi2quad_default>;
flash@0 {
compatible = "spi-flash", "sst,w25q256";
status = "okay";
spi-max-frequency = <50000000>;
spi-tx-bus-width = <4>;

34
arch/arm/dts/ast2600.dtsi
View file

@ -129,74 +129,78 @@
};
fmc: flash-controller@1e620000 {
reg = < 0x1e620000 0xc4
0x20000000 0x10000000 >;
reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2600-fmc";
status = "disabled";
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scu ASPEED_CLK_AHB>;
num-cs = <3>;
flash@0 {
reg = < 0 >;
reg = <0>;
compatible = "jedec,spi-nor";
status = "disabled";
};
flash@1 {
reg = < 1 >;
reg = <1>;
compatible = "jedec,spi-nor";
status = "disabled";
};
flash@2 {
reg = < 2 >;
reg = <2>;
compatible = "jedec,spi-nor";
status = "disabled";
};
};
spi1: flash-controller@1e630000 {
reg = < 0x1e630000 0xc4
0x30000000 0x08000000 >;
reg = <0x1e630000 0xc4>, <0x30000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2600-spi";
clocks = <&scu ASPEED_CLK_AHB>;
num-cs = <2>;
status = "disabled";
flash@0 {
reg = < 0 >;
reg = <0>;
compatible = "jedec,spi-nor";
status = "disabled";
};
flash@1 {
reg = < 1 >;
reg = <1>;
compatible = "jedec,spi-nor";
status = "disabled";
};
};
spi2: flash-controller@1e631000 {
reg = < 0x1e631000 0xc4
0x50000000 0x08000000 >;
reg = <0x1e631000 0xc4>, <0x50000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2600-spi";
clocks = <&scu ASPEED_CLK_AHB>;
num-cs = <3>;
status = "disabled";
flash@0 {
reg = < 0 >;
reg = <0>;
compatible = "jedec,spi-nor";
status = "disabled";
};
flash@1 {
reg = < 1 >;
reg = <1>;
compatible = "jedec,spi-nor";
status = "disabled";
};
flash@2 {
reg = < 2 >;
reg = <2>;
compatible = "jedec,spi-nor";
status = "disabled";
};

17
arch/arm/dts/at91-sam9x60_curiosity.dts
View file

@ -44,6 +44,11 @@
<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
pinctrl_onewire_tm_default: onewire_tm_default {
atmel,pins =
<AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
};
};
};
@ -66,6 +71,18 @@
memory {
reg = <0x20000000 0x8000000>;
};
onewire_tm: onewire {
gpios = <&pioD 14 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_onewire_tm_default>;
status = "okay";
w1_eeprom: w1_eeprom@0 {
compatible = "maxim,ds24b33";
status = "okay";
};
};
};
&macb0 {

59
arch/arm/dts/at91-sama5d27_giantboard.dts
View file

@ -30,7 +30,7 @@
sdmmc1: sdio-host@b0000000 {
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc1_cmd_dat_default &pinctrl_sdmmc1_ck_cd_default>;
pinctrl-0 = <&pinctrl_sdmmc1_default>;
status = "okay";
u-boot,dm-pre-reloc;
};
@ -73,10 +73,9 @@
u-boot,dm-pre-reloc;
};
pioA: gpio@fc038000 {
pinctrl {
pinctrl_sdmmc1_cmd_dat_default: sdmmc1_cmd_dat_default {
pioA: pinctrl@fc038000 {
pinctrl_sdmmc1_default: sdmmc1_default {
cmd_data {
pinmux = <PIN_PA28__SDMMC1_CMD>,
<PIN_PA18__SDMMC1_DAT0>,
<PIN_PA19__SDMMC1_DAT1>,
@ -86,41 +85,41 @@
u-boot,dm-pre-reloc;
};
pinctrl_sdmmc1_ck_cd_default: sdmmc1_ck_cd_default {
ck_cd {
pinmux = <PIN_PA22__SDMMC1_CK>,
<PIN_PA30__SDMMC1_CD>;
bias-disable;
u-boot,dm-pre-reloc;
};
};
pinctrl_uart1_default: uart1_default {
pinmux = <PIN_PD2__URXD1>,
<PIN_PD3__UTXD1>;
bias-disable;
u-boot,dm-pre-reloc;
};
pinctrl_uart1_default: uart1_default {
pinmux = <PIN_PD2__URXD1>,
<PIN_PD3__UTXD1>;
bias-disable;
u-boot,dm-pre-reloc;
};
pinctrl_i2c0_default: i2c0_default {
pinmux = <PIN_PD21__TWD0>,
<PIN_PD22__TWCK0>;
bias-disable;
};
pinctrl_i2c0_default: i2c0_default {
pinmux = <PIN_PD21__TWD0>,
<PIN_PD22__TWCK0>;
bias-disable;
};
pinctrl_i2c1_default: i2c1_default {
pinmux = <PIN_PD4__TWD1>,
<PIN_PD5__TWCK1>;
bias-disable;
};
pinctrl_i2c1_default: i2c1_default {
pinmux = <PIN_PD4__TWD1>,
<PIN_PD5__TWCK1>;
bias-disable;
};
pinctrl_usb_default: usb_default {
pinmux = <PIN_PB10__GPIO>;
bias-disable;
};
pinctrl_usb_default: usb_default {
pinmux = <PIN_PB10__GPIO>;
bias-disable;
};
pinctrl_usba_vbus: usba_vbus {
pinmux = <PIN_PA31__GPIO>;
bias-disable;
};
pinctrl_usba_vbus: usba_vbus {
pinmux = <PIN_PA31__GPIO>;
bias-disable;
};
};
};

78
arch/arm/dts/at91-sama5d27_som1_ek.dts
View file

@ -83,7 +83,7 @@
sdmmc0: sdio-host@a0000000 {
bus-width = <8>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc0_cmd_dat_default &pinctrl_sdmmc0_ck_cd_default>;
pinctrl-0 = <&pinctrl_sdmmc0_default>;
status = "okay";
u-boot,dm-pre-reloc;
};
@ -91,7 +91,7 @@
sdmmc1: sdio-host@b0000000 {
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc1_cmd_dat_default &pinctrl_sdmmc1_ck_cd_default>;
pinctrl-0 = <&pinctrl_sdmmc1_default>;
status = "okay"; /* conflict with qspi0 */
u-boot,dm-pre-reloc;
};
@ -129,7 +129,7 @@
u-boot,dm-pre-reloc;
};
pioA: gpio@fc038000 {
pioA: pinctrl@fc038000 {
pinctrl {
pinctrl_lcd_base: pinctrl_lcd_base {
pinmux = <PIN_PC5__LCDVSYNC>,
@ -166,43 +166,47 @@
bias-disable;
};
pinctrl_sdmmc0_cmd_dat_default: sdmmc0_cmd_dat_default {
pinmux = <PIN_PA1__SDMMC0_CMD>,
<PIN_PA2__SDMMC0_DAT0>,
<PIN_PA3__SDMMC0_DAT1>,
<PIN_PA4__SDMMC0_DAT2>,
<PIN_PA5__SDMMC0_DAT3>,
<PIN_PA6__SDMMC0_DAT4>,
<PIN_PA7__SDMMC0_DAT5>,
<PIN_PA8__SDMMC0_DAT6>,
<PIN_PA9__SDMMC0_DAT7>;
bias-pull-up;
u-boot,dm-pre-reloc;
pinctrl_sdmmc0_default: sdmmc0_default {
cmd_dat {
pinmux = <PIN_PA1__SDMMC0_CMD>,
<PIN_PA2__SDMMC0_DAT0>,
<PIN_PA3__SDMMC0_DAT1>,
<PIN_PA4__SDMMC0_DAT2>,
<PIN_PA5__SDMMC0_DAT3>,
<PIN_PA6__SDMMC0_DAT4>,
<PIN_PA7__SDMMC0_DAT5>,
<PIN_PA8__SDMMC0_DAT6>,
<PIN_PA9__SDMMC0_DAT7>;
bias-pull-up;
u-boot,dm-pre-reloc;
};
ck_cd {
pinmux = <PIN_PA0__SDMMC0_CK>,
<PIN_PA10__SDMMC0_RSTN>,
<PIN_PA13__SDMMC0_CD>;
bias-disable;
u-boot,dm-pre-reloc;
};
};
pinctrl_sdmmc0_ck_cd_default: sdmmc0_ck_cd_default {
pinmux = <PIN_PA0__SDMMC0_CK>,
<PIN_PA10__SDMMC0_RSTN>,
<PIN_PA13__SDMMC0_CD>;
bias-disable;
u-boot,dm-pre-reloc;
};
pinctrl_sdmmc1_default: sdmmc1_default {
cmd_dat {
pinmux = <PIN_PA28__SDMMC1_CMD>,
<PIN_PA18__SDMMC1_DAT0>,
<PIN_PA19__SDMMC1_DAT1>,
<PIN_PA20__SDMMC1_DAT2>,
<PIN_PA21__SDMMC1_DAT3>;
bias-pull-up;
u-boot,dm-pre-reloc;
};
pinctrl_sdmmc1_cmd_dat_default: sdmmc1_cmd_dat_default {
pinmux = <PIN_PA28__SDMMC1_CMD>,
<PIN_PA18__SDMMC1_DAT0>,
<PIN_PA19__SDMMC1_DAT1>,
<PIN_PA20__SDMMC1_DAT2>,
<PIN_PA21__SDMMC1_DAT3>;
bias-pull-up;
u-boot,dm-pre-reloc;
};
pinctrl_sdmmc1_ck_cd_default: sdmmc1_ck_cd_default {
pinmux = <PIN_PA22__SDMMC1_CK>,
<PIN_PA30__SDMMC1_CD>;
bias-disable;
u-boot,dm-pre-reloc;
ck_cd {
pinmux = <PIN_PA22__SDMMC1_CK>,
<PIN_PA30__SDMMC1_CD>;
bias-disable;
u-boot,dm-pre-reloc;
};
};
pinctrl_uart1_default: uart1_default {

6
arch/arm/dts/at91-sama5d27_wlsom1_ek-u-boot.dtsi
View file

@ -37,11 +37,7 @@
u-boot,dm-pre-reloc;
};
&pinctrl_sdmmc0_cmd_dat_default {
u-boot,dm-pre-reloc;
};
&pinctrl_sdmmc0_ck_cd_default {
&pinctrl_sdmmc0_default {
u-boot,dm-pre-reloc;
};

92
arch/arm/dts/at91-sama5d27_wlsom1_ek.dts
View file

@ -34,7 +34,7 @@
sdmmc0: sdio-host@a0000000 {
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc0_cmd_dat_default &pinctrl_sdmmc0_ck_cd_default>;
pinctrl-0 = <&pinctrl_sdmmc0_default>;
status = "okay";
};
@ -78,44 +78,44 @@
status = "okay";
};
pioA: gpio@fc038000 {
pinctrl {
pinctrl_lcd_base: pinctrl_lcd_base {
pinmux = <PIN_PC30__LCDVSYNC>,
<PIN_PC31__LCDHSYNC>,
<PIN_PD1__LCDDEN>,
<PIN_PD0__LCDPCK>;
bias-disable;
};
pioA: pinctrl@fc038000 {
pinctrl_lcd_base: pinctrl_lcd_base {
pinmux = <PIN_PC30__LCDVSYNC>,
<PIN_PC31__LCDHSYNC>,
<PIN_PD1__LCDDEN>,
<PIN_PD0__LCDPCK>;
bias-disable;
};
pinctrl_lcd_pwm: pinctrl_lcd_pwm {
pinmux = <PIN_PC28__LCDPWM>;
bias-disable;
};
pinctrl_lcd_pwm: pinctrl_lcd_pwm {
pinmux = <PIN_PC28__LCDPWM>;
bias-disable;
};
pinctrl_lcd_rgb666: pinctrl_lcd_rgb666 {
pinmux = <PIN_PC10__LCDDAT2>,
<PIN_PC11__LCDDAT3>,
<PIN_PC12__LCDDAT4>,
<PIN_PC13__LCDDAT5>,
<PIN_PC14__LCDDAT6>,
<PIN_PC15__LCDDAT7>,
<PIN_PC16__LCDDAT10>,
<PIN_PC17__LCDDAT11>,
<PIN_PC18__LCDDAT12>,
<PIN_PC19__LCDDAT13>,
<PIN_PC20__LCDDAT14>,
<PIN_PC21__LCDDAT15>,
<PIN_PC22__LCDDAT18>,
<PIN_PC23__LCDDAT19>,
<PIN_PC24__LCDDAT20>,
<PIN_PC25__LCDDAT21>,
<PIN_PC26__LCDDAT22>,
<PIN_PC27__LCDDAT23>;
bias-disable;
};
pinctrl_lcd_rgb666: pinctrl_lcd_rgb666 {
pinmux = <PIN_PC10__LCDDAT2>,
<PIN_PC11__LCDDAT3>,
<PIN_PC12__LCDDAT4>,
<PIN_PC13__LCDDAT5>,
<PIN_PC14__LCDDAT6>,
<PIN_PC15__LCDDAT7>,
<PIN_PC16__LCDDAT10>,
<PIN_PC17__LCDDAT11>,
<PIN_PC18__LCDDAT12>,
<PIN_PC19__LCDDAT13>,
<PIN_PC20__LCDDAT14>,
<PIN_PC21__LCDDAT15>,
<PIN_PC22__LCDDAT18>,
<PIN_PC23__LCDDAT19>,
<PIN_PC24__LCDDAT20>,
<PIN_PC25__LCDDAT21>,
<PIN_PC26__LCDDAT22>,
<PIN_PC27__LCDDAT23>;
bias-disable;
};
pinctrl_sdmmc0_cmd_dat_default: sdmmc0_cmd_dat_default {
pinctrl_sdmmc0_default: sdmmc0_default {
cmd_data {
pinmux = <PIN_PA1__SDMMC0_CMD>,
<PIN_PA2__SDMMC0_DAT0>,
<PIN_PA3__SDMMC0_DAT1>,
@ -124,24 +124,24 @@
bias-disable;
};
pinctrl_sdmmc0_ck_cd_default: sdmmc0_ck_cd_default {
ck_cd_vddsel {
pinmux = <PIN_PA0__SDMMC0_CK>,
<PIN_PA11__SDMMC0_VDDSEL>,
<PIN_PA12__SDMMC0_WP>,
<PIN_PA13__SDMMC0_CD>;
bias-disable;
};
};
pinctrl_uart0_default: uart0_default {
pinmux = <PIN_PB26__URXD0>,
<PIN_PB27__UTXD0>;
bias-disable;
};
pinctrl_uart0_default: uart0_default {
pinmux = <PIN_PB26__URXD0>,
<PIN_PB27__UTXD0>;
bias-disable;
};
pinctrl_onewire_tm_default: onewire_tm_default {
pinmux = <PIN_PC9__GPIO>;
bias-pull-up;
};
pinctrl_onewire_tm_default: onewire_tm_default {
pinmux = <PIN_PC9__GPIO>;
bias-pull-up;
};
};
};

120
arch/arm/dts/at91-sama5d2_icp.dts
View file

@ -86,75 +86,73 @@
};
};
pioA: gpio@fc038000 {
pioA: pinctrl@fc038000 {
status = "okay";
pinctrl {
pinctrl_i2c1_default: i2c1_default {
pinmux = <PIN_PD19__TWD1>,
<PIN_PD20__TWCK1>;
bias-disable;
};
pinctrl_i2c1_default: i2c1_default {
pinmux = <PIN_PD19__TWD1>,
<PIN_PD20__TWCK1>;
bias-disable;
};
pinctrl_macb0_rmii: macb0_rmii {
pinmux = <PIN_PD1__GRXCK>,
<PIN_PD2__GTXER>,
<PIN_PD5__GRX2>,
<PIN_PD6__GRX3>,
<PIN_PD7__GTX2>,
<PIN_PD8__GTX3>,
<PIN_PD9__GTXCK>,
<PIN_PD10__GTXEN>,
<PIN_PD11__GRXDV>,
<PIN_PD12__GRXER>,
<PIN_PD13__GRX0>,
<PIN_PD14__GRX1>,
<PIN_PD15__GTX0>,
<PIN_PD16__GTX1>,
<PIN_PD17__GMDC>,
<PIN_PD18__GMDIO>;
bias-disable;
};
pinctrl_macb0_rmii: macb0_rmii {
pinmux = <PIN_PD1__GRXCK>,
<PIN_PD2__GTXER>,
<PIN_PD5__GRX2>,
<PIN_PD6__GRX3>,
<PIN_PD7__GTX2>,
<PIN_PD8__GTX3>,
<PIN_PD9__GTXCK>,
<PIN_PD10__GTXEN>,
<PIN_PD11__GRXDV>,
<PIN_PD12__GRXER>,
<PIN_PD13__GRX0>,
<PIN_PD14__GRX1>,
<PIN_PD15__GTX0>,
<PIN_PD16__GTX1>,
<PIN_PD17__GMDC>,
<PIN_PD18__GMDIO>;
bias-disable;
};
pinctrl_macb0_phy_irq: macb0_phy_irq {
pinmux = <PIN_PD3__GPIO>;
bias-disable;
};
pinctrl_macb0_phy_irq: macb0_phy_irq {
pinmux = <PIN_PD3__GPIO>;
bias-disable;
};
pinctrl_macb0_rst: macb0_sw_rst {
pinmux = <PIN_PD4__GPIO>;
bias-pull-up;
};
pinctrl_macb0_rst: macb0_sw_rst {
pinmux = <PIN_PD4__GPIO>;
bias-pull-up;
};
pinctrl_mikrobus1_uart: mikrobus1_uart {
pinmux = <PIN_PB26__URXD0>,
<PIN_PB27__UTXD0>;
bias-disable;
};
pinctrl_mikrobus1_uart: mikrobus1_uart {
pinmux = <PIN_PB26__URXD0>,
<PIN_PB27__UTXD0>;
bias-disable;
};
pinctrl_qspi1_sck_cs_default: qspi1_sck_cs_default {
pinmux = <PIN_PA6__QSPI1_SCK>,
<PIN_PA11__QSPI1_CS>;
bias-disable;
};
pinctrl_qspi1_sck_cs_default: qspi1_sck_cs_default {
pinmux = <PIN_PA6__QSPI1_SCK>,
<PIN_PA11__QSPI1_CS>;
bias-disable;
};
pinctrl_qspi1_dat_default: qspi1_dat_default {
pinmux = <PIN_PA7__QSPI1_IO0>,
<PIN_PA8__QSPI1_IO1>,
<PIN_PA9__QSPI1_IO2>,
<PIN_PA10__QSPI1_IO3>;
bias-pull-up;
};
pinctrl_qspi1_dat_default: qspi1_dat_default {
pinmux = <PIN_PA7__QSPI1_IO0>,
<PIN_PA8__QSPI1_IO1>,
<PIN_PA9__QSPI1_IO2>,
<PIN_PA10__QSPI1_IO3>;
bias-pull-up;
};
pinctrl_sdmmc0_default: sdmmc0_default {
pinmux = <PIN_PA1__SDMMC0_CMD>,
<PIN_PA2__SDMMC0_DAT0>,
<PIN_PA3__SDMMC0_DAT1>,
<PIN_PA4__SDMMC0_DAT2>,
<PIN_PA5__SDMMC0_DAT3>,
<PIN_PA0__SDMMC0_CK>,
<PIN_PA13__SDMMC0_CD>;
bias-disable;
};
pinctrl_sdmmc0_default: sdmmc0_default {
pinmux = <PIN_PA1__SDMMC0_CMD>,
<PIN_PA2__SDMMC0_DAT0>,
<PIN_PA3__SDMMC0_DAT1>,
<PIN_PA4__SDMMC0_DAT2>,
<PIN_PA5__SDMMC0_DAT3>,
<PIN_PA0__SDMMC0_CK>,
<PIN_PA13__SDMMC0_CD>;
bias-disable;
};
};
};

98
arch/arm/dts/at91-sama5d2_ptc_ek.dts
View file

@ -94,7 +94,7 @@
sdmmc0: sdio-host@a0000000 {
bus-width = <8>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc0_cmd_dat_default &pinctrl_sdmmc0_ck_cd_default>;
pinctrl-0 = <&pinctrl_sdmmc0_default>;
status = "okay";
u-boot,dm-pre-reloc;
};
@ -102,7 +102,7 @@
sdmmc1: sdio-host@b0000000 {
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc1_cmd_dat_default &pinctrl_sdmmc1_ck_cd_default>;
pinctrl-0 = <&pinctrl_sdmmc1_default>;
status = "disabled"; /* conflicts with nand and qspi0*/
u-boot,dm-pre-reloc;
};
@ -137,34 +137,34 @@
};
};
pioA: gpio@fc038000 {
pinctrl {
pinctrl_i2c1_default: i2c1_default {
pinmux = <PIN_PC6__TWD1>,
<PIN_PC7__TWCK1>;
bias-disable;
};
pioA: pinctrl@fc038000 {
pinctrl_i2c1_default: i2c1_default {
pinmux = <PIN_PC6__TWD1>,
<PIN_PC7__TWCK1>;
bias-disable;
};
pinctrl_macb0_phy_irq: macb0_phy_irq {
pinmux = <PIN_PB24__GPIO>;
bias-disable;
};
pinctrl_macb0_phy_irq: macb0_phy_irq {
pinmux = <PIN_PB24__GPIO>;
bias-disable;
};
pinctrl_macb0_rmii: macb0_rmii {
pinmux = <PIN_PB14__GTXCK>,
<PIN_PB15__GTXEN>,
<PIN_PB16__GRXDV>,
<PIN_PB17__GRXER>,
<PIN_PB18__GRX0>,
<PIN_PB19__GRX1>,
<PIN_PB20__GTX0>,
<PIN_PB21__GTX1>,
<PIN_PB22__GMDC>,
<PIN_PB23__GMDIO>;
bias-disable;
};
pinctrl_macb0_rmii: macb0_rmii {
pinmux = <PIN_PB14__GTXCK>,
<PIN_PB15__GTXEN>,
<PIN_PB16__GRXDV>,
<PIN_PB17__GRXER>,
<PIN_PB18__GRX0>,
<PIN_PB19__GRX1>,
<PIN_PB20__GTX0>,
<PIN_PB21__GTX1>,
<PIN_PB22__GMDC>,
<PIN_PB23__GMDIO>;
bias-disable;
};
pinctrl_sdmmc0_cmd_dat_default: sdmmc0_cmd_dat_default {
pinctrl_sdmmc0_default: sdmmc0_default {
cmd_dat {
pinmux = <PIN_PA1__SDMMC0_CMD>,
<PIN_PA2__SDMMC0_DAT0>,
<PIN_PA3__SDMMC0_DAT1>,
@ -178,7 +178,7 @@
u-boot,dm-pre-reloc;
};
pinctrl_sdmmc0_ck_cd_default: sdmmc0_ck_cd_default {
ck_cd {
pinmux = <PIN_PA0__SDMMC0_CK>,
<PIN_PA10__SDMMC0_RSTN>,
<PIN_PA11__SDMMC0_VDDSEL>,
@ -186,8 +186,10 @@
bias-disable;
u-boot,dm-pre-reloc;
};
};
pinctrl_sdmmc1_cmd_dat_default: sdmmc1_cmd_dat_default {
pinctrl_sdmmc1_default: sdmmc1_default {
cmd_dat {
pinmux = <PIN_PA28__SDMMC1_CMD>,
<PIN_PA18__SDMMC1_DAT0>,
<PIN_PA19__SDMMC1_DAT1>,
@ -197,34 +199,34 @@
u-boot,dm-pre-reloc;
};
pinctrl_sdmmc1_ck_cd_default: sdmmc1_ck_cd_default {
ck_cd {
pinmux = <PIN_PA22__SDMMC1_CK>,
<PIN_PA30__SDMMC1_CD>;
bias-disable;
u-boot,dm-pre-reloc;
};
};
pinctrl_uart0_default: uart0_default {
pinmux = <PIN_PB26__URXD0>,
<PIN_PB27__UTXD0>;
bias-disable;
u-boot,dm-pre-reloc;
};
pinctrl_uart0_default: uart0_default {
pinmux = <PIN_PB26__URXD0>,
<PIN_PB27__UTXD0>;
bias-disable;
u-boot,dm-pre-reloc;
};
pinctrl_usb_default: usb_default {
pinmux = <PIN_PB12__GPIO>;
bias-disable;
};
pinctrl_usb_default: usb_default {
pinmux = <PIN_PB12__GPIO>;
bias-disable;
};
pinctrl_usba_vbus: usba_vbus {
pinmux = <PIN_PB11__GPIO>;
bias-disable;
};
pinctrl_usba_vbus: usba_vbus {
pinmux = <PIN_PB11__GPIO>;
bias-disable;
};
pinctrl_onewire_tm_default: onewire_tm_default {
pinmux = <PIN_PB31__GPIO>;
bias-pull-up;
};
pinctrl_onewire_tm_default: onewire_tm_default {
pinmux = <PIN_PB31__GPIO>;
bias-pull-up;
};
};
};

204
arch/arm/dts/at91-sama5d2_xplained.dts
View file

@ -44,7 +44,7 @@
sdmmc0: sdio-host@a0000000 {
bus-width = <8>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc0_cmd_dat_default &pinctrl_sdmmc0_ck_cd_default>;
pinctrl-0 = <&pinctrl_sdmmc0_default>;
status = "okay";
u-boot,dm-pre-reloc;
};
@ -52,7 +52,7 @@
sdmmc1: sdio-host@b0000000 {
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc1_cmd_dat_default &pinctrl_sdmmc1_ck_cd_default>;
pinctrl-0 = <&pinctrl_sdmmc1_default>;
status = "okay"; /* conflict with qspi0 */
u-boot,dm-pre-reloc;
};
@ -143,85 +143,85 @@
};
};
pioA: gpio@fc038000 {
pinctrl {
pinctrl_i2c1_default: i2c1_default {
pinmux = <PIN_PD4__TWD1>,
<PIN_PD5__TWCK1>;
bias-disable;
};
pioA: pinctrl@fc038000 {
pinctrl_i2c1_default: i2c1_default {
pinmux = <PIN_PD4__TWD1>,
<PIN_PD5__TWCK1>;
bias-disable;
};
pinctrl_lcd_base: pinctrl_lcd_base {
pinmux = <PIN_PC30__LCDVSYNC>,
<PIN_PC31__LCDHSYNC>,
<PIN_PD1__LCDDEN>,
<PIN_PD0__LCDPCK>;
bias-disable;
};
pinctrl_lcd_base: pinctrl_lcd_base {
pinmux = <PIN_PC30__LCDVSYNC>,
<PIN_PC31__LCDHSYNC>,
<PIN_PD1__LCDDEN>,
<PIN_PD0__LCDPCK>;
bias-disable;
};
pinctrl_lcd_pwm: pinctrl_lcd_pwm {
pinmux = <PIN_PC28__LCDPWM>;
bias-disable;
};
pinctrl_lcd_pwm: pinctrl_lcd_pwm {
pinmux = <PIN_PC28__LCDPWM>;
bias-disable;
};
pinctrl_lcd_rgb666: pinctrl_lcd_rgb666 {
pinmux = <PIN_PC10__LCDDAT2>,
<PIN_PC11__LCDDAT3>,
<PIN_PC12__LCDDAT4>,
<PIN_PC13__LCDDAT5>,
<PIN_PC14__LCDDAT6>,
<PIN_PC15__LCDDAT7>,
<PIN_PC16__LCDDAT10>,
<PIN_PC17__LCDDAT11>,
<PIN_PC18__LCDDAT12>,
<PIN_PC19__LCDDAT13>,
<PIN_PC20__LCDDAT14>,
<PIN_PC21__LCDDAT15>,
<PIN_PC22__LCDDAT18>,
<PIN_PC23__LCDDAT19>,
<PIN_PC24__LCDDAT20>,
<PIN_PC25__LCDDAT21>,
<PIN_PC26__LCDDAT22>,
<PIN_PC27__LCDDAT23>;
bias-disable;
};
pinctrl_lcd_rgb666: pinctrl_lcd_rgb666 {
pinmux = <PIN_PC10__LCDDAT2>,
<PIN_PC11__LCDDAT3>,
<PIN_PC12__LCDDAT4>,
<PIN_PC13__LCDDAT5>,
<PIN_PC14__LCDDAT6>,
<PIN_PC15__LCDDAT7>,
<PIN_PC16__LCDDAT10>,
<PIN_PC17__LCDDAT11>,
<PIN_PC18__LCDDAT12>,
<PIN_PC19__LCDDAT13>,
<PIN_PC20__LCDDAT14>,
<PIN_PC21__LCDDAT15>,
<PIN_PC22__LCDDAT18>,
<PIN_PC23__LCDDAT19>,
<PIN_PC24__LCDDAT20>,
<PIN_PC25__LCDDAT21>,
<PIN_PC26__LCDDAT22>,
<PIN_PC27__LCDDAT23>;
bias-disable;
};
pinctrl_macb0_phy_irq: macb0_phy_irq {
pinmux = <PIN_PC9__GPIO>;
bias-disable;
};
pinctrl_macb0_phy_irq: macb0_phy_irq {
pinmux = <PIN_PC9__GPIO>;
bias-disable;
};
pinctrl_macb0_rmii: macb0_rmii {
pinmux = <PIN_PB14__GTXCK>,
<PIN_PB15__GTXEN>,
<PIN_PB16__GRXDV>,
<PIN_PB17__GRXER>,
<PIN_PB18__GRX0>,
<PIN_PB19__GRX1>,
<PIN_PB20__GTX0>,
<PIN_PB21__GTX1>,
<PIN_PB22__GMDC>,
<PIN_PB23__GMDIO>;
bias-disable;
};
pinctrl_macb0_rmii: macb0_rmii {
pinmux = <PIN_PB14__GTXCK>,
<PIN_PB15__GTXEN>,
<PIN_PB16__GRXDV>,
<PIN_PB17__GRXER>,
<PIN_PB18__GRX0>,
<PIN_PB19__GRX1>,
<PIN_PB20__GTX0>,
<PIN_PB21__GTX1>,
<PIN_PB22__GMDC>,
<PIN_PB23__GMDIO>;
bias-disable;
};
pinctrl_qspi0_sck_cs_default: qspi0_sck_cs_default {
pinmux = <PIN_PA22__QSPI0_SCK>,
<PIN_PA23__QSPI0_CS>;
bias-disable;
u-boot,dm-pre-reloc;
};
pinctrl_qspi0_sck_cs_default: qspi0_sck_cs_default {
pinmux = <PIN_PA22__QSPI0_SCK>,
<PIN_PA23__QSPI0_CS>;
bias-disable;
u-boot,dm-pre-reloc;
};
pinctrl_qspi0_dat_default: qspi0_dat_default {
pinmux = <PIN_PA24__QSPI0_IO0>,
<PIN_PA25__QSPI0_IO1>,
<PIN_PA26__QSPI0_IO2>,
<PIN_PA27__QSPI0_IO3>;
bias-pull-up;
u-boot,dm-pre-reloc;
};
pinctrl_qspi0_dat_default: qspi0_dat_default {
pinmux = <PIN_PA24__QSPI0_IO0>,
<PIN_PA25__QSPI0_IO1>,
<PIN_PA26__QSPI0_IO2>,
<PIN_PA27__QSPI0_IO3>;
bias-pull-up;
u-boot,dm-pre-reloc;
};
pinctrl_sdmmc0_cmd_dat_default: sdmmc0_cmd_dat_default {
pinctrl_sdmmc0_default: sdmmc0_default {
cmd_dat {
pinmux = <PIN_PA1__SDMMC0_CMD>,
<PIN_PA2__SDMMC0_DAT0>,
<PIN_PA3__SDMMC0_DAT1>,
@ -235,7 +235,7 @@
u-boot,dm-pre-reloc;
};
pinctrl_sdmmc0_ck_cd_default: sdmmc0_ck_cd_default {
ck_cd_default {
pinmux = <PIN_PA0__SDMMC0_CK>,
<PIN_PA10__SDMMC0_RSTN>,
<PIN_PA11__SDMMC0_VDDSEL>,
@ -243,8 +243,10 @@
bias-disable;
u-boot,dm-pre-reloc;
};
};
pinctrl_sdmmc1_cmd_dat_default: sdmmc1_cmd_dat_default {
pinctrl_sdmmc1_default: sdmmc1_default {
cmd_dat {
pinmux = <PIN_PA28__SDMMC1_CMD>,
<PIN_PA18__SDMMC1_DAT0>,
<PIN_PA19__SDMMC1_DAT1>,
@ -254,42 +256,42 @@
u-boot,dm-pre-reloc;
};
pinctrl_sdmmc1_ck_cd_default: sdmmc1_ck_cd_default {
ck_cd {
pinmux = <PIN_PA22__SDMMC1_CK>,
<PIN_PA30__SDMMC1_CD>;
bias-disable;
u-boot,dm-pre-reloc;
};
};
pinctrl_spi0_default: spi0_default {
pinmux = <PIN_PA14__SPI0_SPCK>,
<PIN_PA15__SPI0_MOSI>,
<PIN_PA16__SPI0_MISO>;
bias-disable;
u-boot,dm-pre-reloc;
};
pinctrl_spi0_default: spi0_default {
pinmux = <PIN_PA14__SPI0_SPCK>,
<PIN_PA15__SPI0_MOSI>,
<PIN_PA16__SPI0_MISO>;
bias-disable;
u-boot,dm-pre-reloc;
};
pinctrl_uart1_default: uart1_default {
pinmux = <PIN_PD2__URXD1>,
<PIN_PD3__UTXD1>;
bias-disable;
u-boot,dm-pre-reloc;
};
pinctrl_uart1_default: uart1_default {
pinmux = <PIN_PD2__URXD1>,
<PIN_PD3__UTXD1>;
bias-disable;
u-boot,dm-pre-reloc;
};
pinctrl_usb_default: usb_default {
pinmux = <PIN_PB10__GPIO>;
bias-disable;
};
pinctrl_usb_default: usb_default {
pinmux = <PIN_PB10__GPIO>;
bias-disable;
};
pinctrl_usba_vbus: usba_vbus {
pinmux = <PIN_PA31__GPIO>;
bias-disable;
};
pinctrl_usba_vbus: usba_vbus {
pinmux = <PIN_PA31__GPIO>;
bias-disable;
};
pinctrl_onewire_tm_default: onewire_tm_default {
pinmux = <PIN_PB0__GPIO>;
bias-pull-up;
};
pinctrl_onewire_tm_default: onewire_tm_default {
pinmux = <PIN_PB0__GPIO>;
bias-pull-up;
};
};
};

2
arch/arm/dts/at91-sama7g5ek-u-boot.dtsi
View file

@ -28,7 +28,7 @@
u-boot,dm-pre-reloc;
};
&pinctrl {
&pioA {
u-boot,dm-pre-reloc;
};

85
arch/arm/dts/at91-sama7g5ek.dts
View file

@ -690,46 +690,67 @@
};
pinctrl_sdmmc0_default: sdmmc0_default {
pinmux = <PIN_PA1__SDMMC0_CMD>,
<PIN_PA3__SDMMC0_DAT0>,
<PIN_PA4__SDMMC0_DAT1>,
<PIN_PA5__SDMMC0_DAT2>,
<PIN_PA6__SDMMC0_DAT3>,
<PIN_PA7__SDMMC0_DAT4>,
<PIN_PA8__SDMMC0_DAT5>,
<PIN_PA9__SDMMC0_DAT6>,
<PIN_PA10__SDMMC0_DAT7>,
<PIN_PA0__SDMMC0_CK>,
<PIN_PA2__SDMMC0_RSTN>,
<PIN_PA14__SDMMC0_CD>,
<PIN_PA11__SDMMC0_DS>;
cmd_data {
pinmux = <PIN_PA1__SDMMC0_CMD>,
<PIN_PA3__SDMMC0_DAT0>,
<PIN_PA4__SDMMC0_DAT1>,
<PIN_PA5__SDMMC0_DAT2>,
<PIN_PA6__SDMMC0_DAT3>,
<PIN_PA7__SDMMC0_DAT4>,
<PIN_PA8__SDMMC0_DAT5>,
<PIN_PA9__SDMMC0_DAT6>,
<PIN_PA10__SDMMC0_DAT7>;
slew-rate = <0>;
bias-pull-up;
};
ck_cd_rstn_vddsel {
pinmux = <PIN_PA0__SDMMC0_CK>,
<PIN_PA2__SDMMC0_RSTN>,
<PIN_PA14__SDMMC0_CD>,
<PIN_PA11__SDMMC0_DS>;
slew-rate = <0>;
bias-pull-up;
};
};
pinctrl_sdmmc1_default: sdmmc1_default {
pinmux = <PIN_PB29__SDMMC1_CMD>,
<PIN_PB31__SDMMC1_DAT0>,
<PIN_PC0__SDMMC1_DAT1>,
<PIN_PC1__SDMMC1_DAT2>,
<PIN_PC2__SDMMC1_DAT3>,
<PIN_PB30__SDMMC1_CK>,
<PIN_PB28__SDMMC1_RSTN>,
<PIN_PC5__SDMMC1_1V8SEL>,
<PIN_PC4__SDMMC1_CD>;
slew-rate = <0>;
bias-pull-up;
cmd_data {
pinmux = <PIN_PB29__SDMMC1_CMD>,
<PIN_PB31__SDMMC1_DAT0>,
<PIN_PC0__SDMMC1_DAT1>,
<PIN_PC1__SDMMC1_DAT2>,
<PIN_PC2__SDMMC1_DAT3>;
slew-rate = <0>;
bias-pull-up;
};
ck_cd_rstn_vddsel {
pinmux = <PIN_PB30__SDMMC1_CK>,
<PIN_PB28__SDMMC1_RSTN>,
<PIN_PC5__SDMMC1_1V8SEL>,
<PIN_PC4__SDMMC1_CD>;
slew-rate = <0>;
bias-pull-up;
};
};
pinctrl_sdmmc2_default: sdmmc2_default {
pinmux = <PIN_PD3__SDMMC2_CMD>,
<PIN_PD5__SDMMC2_DAT0>,
<PIN_PD6__SDMMC2_DAT1>,
<PIN_PD7__SDMMC2_DAT2>,
<PIN_PD8__SDMMC2_DAT3>,
<PIN_PD4__SDMMC2_CK>;
slew-rate = <0>;
bias-pull-up;
cmd_data {
pinmux = <PIN_PD3__SDMMC2_CMD>,
<PIN_PD5__SDMMC2_DAT0>,
<PIN_PD6__SDMMC2_DAT1>,
<PIN_PD7__SDMMC2_DAT2>,
<PIN_PD8__SDMMC2_DAT3>;
slew-rate = <0>;
bias-pull-up;
};
ck {
pinmux = <PIN_PD4__SDMMC2_CK>;
slew-rate = <0>;
bias-pull-up;
};
};
pinctrl_spdifrx_default: spdifrx_default {

2
arch/arm/dts/dragonboard410c-uboot.dtsi
View file

@ -14,7 +14,7 @@
soc {
u-boot,dm-pre-reloc;
qcom,tlmm@1000000 {
pinctrl@1000000 {
u-boot,dm-pre-reloc;
uart {

17
arch/arm/dts/dragonboard410c.dts
View file

@ -60,9 +60,13 @@
reg = <0x60000 0x8000>;
};
pinctrl: qcom,tlmm@1000000 {
compatible = "qcom,tlmm-apq8016";
soc_gpios: pinctrl@1000000 {
compatible = "qcom,msm8916-pinctrl";
reg = <0x1000000 0x400000>;
gpio-controller;
gpio-count = <122>;
gpio-bank-name="soc";
#gpio-cells = <2>;
blsp1_uart: uart {
function = "blsp1_uart";
@ -86,15 +90,6 @@
pinctrl-0 = <&blsp1_uart>;
};
soc_gpios: pinctrl@1000000 {
compatible = "qcom,apq8016-pinctrl";
reg = <0x1000000 0x300000>;
gpio-controller;
gpio-count = <122>;
gpio-bank-name="soc";
#gpio-cells = <2>;
};
ehci@78d9000 {
compatible = "qcom,ehci-host";
reg = <0x78d9000 0x400>;

2
arch/arm/dts/dragonboard820c-uboot.dtsi
View file

@ -13,7 +13,7 @@
soc {
u-boot,dm-pre-reloc;
qcom,tlmm@1010000 {
pinctrl@1010000 {
u-boot,dm-pre-reloc;
uart {

4
arch/arm/dts/dragonboard820c.dts
View file

@ -64,8 +64,8 @@
reg = <0x300000 0x90000>;
};
pinctrl: qcom,tlmm@1010000 {
compatible = "qcom,tlmm-apq8096";
pinctrl: pinctrl@1010000 {
compatible = "qcom,msm8996-pinctrl";
reg = <0x1010000 0x400000>;
blsp8_uart: uart {

18
arch/arm/dts/mt7622-rfb.dts
View file

@ -159,6 +159,14 @@
};
};
i2c1_pins_default: i2c1-default {
mux {
function = "i2c";
groups = "i2c1_0";
};
};
};
&snfi {
@ -242,3 +250,13 @@
&u3phy {
status = "okay";
};
&soft_i2c {
status = "disabled";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_default>;
status = "okay";
};

25
arch/arm/dts/mt7622.dtsi
View file

@ -175,6 +175,7 @@
status = "disabled";
assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
mediatek,force-highspeed;
};
mmc0: mmc@11230000 {
@ -423,4 +424,28 @@
status = "disabled";
};
soft_i2c: soft_i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "i2c-gpio";
gpios = <&gpio 56 GPIO_ACTIVE_HIGH>, /* SDA */
<&gpio 55 GPIO_ACTIVE_HIGH>; /* CLK */
i2c-gpio,delay-us = <5>;
status = "disabled";
};
i2c1: i2c@11008000 {
compatible = "mediatek,mt7622-i2c";
reg = <0x11008000 0x90>,
<0x11000180 0x80>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
clock-div = <16>;
clocks = <&pericfg CLK_PERI_I2C1_PD>,
<&pericfg CLK_PERI_AP_DMA_PD>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};

139
arch/arm/dts/mt7981-emmc-rfb.dts Normal file
View file

@ -0,0 +1,139 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Sam Shih <sam.shih@mediatek.com>
*/
/dts-v1/;
#include "mt7981.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "mt7981-rfb";
compatible = "mediatek,mt7981", "mediatek,mt7981-rfb";
chosen {
stdout-path = &uart0;
tick-timer = &timer0;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
&uart0 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "disabled";
};
&eth {
status = "okay";
mediatek,gmac-id = <0>;
phy-mode = "sgmii";
mediatek,switch = "mt7531";
reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&pinctrl {
spic_pins: spi1-pins-func-1 {
mux {
function = "spi";
groups = "spi1_1";
};
};
uart1_pins: spi1-pins-func-3 {
mux {
function = "uart";
groups = "uart1_2";
};
};
/* pin15 as pwm0 */
one_pwm_pins: one-pwm-pins {
mux {
function = "pwm";
groups = "pwm0_1";
};
};
/* pin15 as pwm0 and pin14 as pwm1 */
two_pwm_pins: two-pwm-pins {
mux {
function = "pwm";
groups = "pwm0_1", "pwm1_0";
};
};
/* pin15 as pwm0, pin14 as pwm1, pin7 as pwm2 */
three_pwm_pins: three-pwm-pins {
mux {
function = "pwm";
groups = "pwm0_1", "pwm1_0", "pwm2";
};
};
mmc0_pins_default: mmc0default {
mux {
function = "flash";
groups = "emmc_45";
};
conf-cmd-dat {
pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
"SPI0_CS", "SPI0_HOLD", "SPI0_WP",
"SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
input-enable;
drive-strength = <MTK_DRIVE_4mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
conf-clk {
pins = "SPI1_CS";
drive-strength = <MTK_DRIVE_6mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
conf-rst {
pins = "PWM0";
drive-strength = <MTK_DRIVE_4mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&two_pwm_pins>;
status = "okay";
};
&watchdog {
status = "disabled";
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_default>;
bus-width = <8>;
max-frequency = <52000000>;
cap-mmc-highspeed;
cap-mmc-hw-reset;
vmmc-supply = <&reg_3p3v>;
non-removable;
status = "okay";
};

173
arch/arm/dts/mt7981-rfb.dts Normal file
View file

@ -0,0 +1,173 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Sam Shih <sam.shih@mediatek.com>
*/
/dts-v1/;
#include "mt7981.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "mt7981-rfb";
compatible = "mediatek,mt7981", "mediatek,mt7981-rfb";
chosen {
stdout-path = &uart0;
tick-timer = &timer0;
};
};
&uart0 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "disabled";
};
&eth {
status = "okay";
mediatek,gmac-id = <0>;
phy-mode = "sgmii";
mediatek,switch = "mt7531";
reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&pinctrl {
spi_flash_pins: spi0-pins-func-1 {
mux {
function = "flash";
groups = "spi0", "spi0_wp_hold";
};
conf-pu {
pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
};
conf-pd {
pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
};
};
spi2_flash_pins: spi2-spi2-pins {
mux {
function = "spi";
groups = "spi2", "spi2_wp_hold";
};
conf-pu {
pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
};
conf-pd {
pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
};
};
spic_pins: spi1-pins-func-1 {
mux {
function = "spi";
groups = "spi1_1";
};
};
uart1_pins: spi1-pins-func-3 {
mux {
function = "uart";
groups = "uart1_2";
};
};
/* pin15 as pwm0 */
one_pwm_pins: one-pwm-pins {
mux {
function = "pwm";
groups = "pwm0_1";
};
};
/* pin15 as pwm0 and pin14 as pwm1 */
two_pwm_pins: two-pwm-pins {
mux {
function = "pwm";
groups = "pwm0_1", "pwm1_0";
};
};
/* pin15 as pwm0, pin14 as pwm1, pin7 as pwm2 */
three_pwm_pins: three-pwm-pins {
mux {
function = "pwm";
groups = "pwm0_1", "pwm1_0", "pwm2";
};
};
};
&spi0 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&spi_flash_pins>;
status = "okay";
must_tx;
enhance_timing;
dma_ext;
ipm_design;
support_quad;
tick_dly = <2>;
sample_sel = <0>;
spi_nand@0 {
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <52000000>;
};
};
&spi2 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&spi2_flash_pins>;
status = "okay";
must_tx;
enhance_timing;
dma_ext;
ipm_design;
support_quad;
tick_dly = <2>;
sample_sel = <0>;
spi_nor@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <52000000>;
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&two_pwm_pins>;
status = "okay";
};
&watchdog {
status = "disabled";
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Sam Shih <sam.shih@mediatek.com>
*/
/dts-v1/;
#include "mt7981.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "mt7981-rfb";
compatible = "mediatek,mt7981", "mediatek,mt7981-sd-rfb";
chosen {
stdout-path = &uart0;
tick-timer = &timer0;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
&uart0 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "disabled";
};
&eth {
status = "okay";
mediatek,gmac-id = <0>;
phy-mode = "sgmii";
mediatek,switch = "mt7531";
reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&pinctrl {
spic_pins: spi1-pins-func-1 {
mux {
function = "spi";
groups = "spi1_1";
};
};
uart1_pins: spi1-pins-func-3 {
mux {
function = "uart";
groups = "uart1_2";
};
};
/* pin15 as pwm0 */
one_pwm_pins: one-pwm-pins {
mux {
function = "pwm";
groups = "pwm0_1";
};
};
/* pin15 as pwm0 and pin14 as pwm1 */
two_pwm_pins: two-pwm-pins {
mux {
function = "pwm";
groups = "pwm0_1", "pwm1_0";
};
};
/* pin15 as pwm0, pin14 as pwm1, pin7 as pwm2 */
three_pwm_pins: three-pwm-pins {
mux {
function = "pwm";
groups = "pwm0_1", "pwm1_0", "pwm2";
};
};
mmc0_pins_default: mmc0default {
mux {
function = "flash";
groups = "emmc_45";
};
conf-cmd-dat {
pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
"SPI0_CS", "SPI0_HOLD", "SPI0_WP",
"SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
input-enable;
drive-strength = <MTK_DRIVE_4mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
conf-clk {
pins = "SPI1_CS";
drive-strength = <MTK_DRIVE_6mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
conf-rst {
pins = "PWM0";
drive-strength = <MTK_DRIVE_4mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&two_pwm_pins>;
status = "okay";
};
&watchdog {
status = "disabled";
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_default>;
bus-width = <4>;
max-frequency = <52000000>;
cap-sd-highspeed;
r_smpl = <0>;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_3p3v>;
status = "okay";
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Sam Shih <sam.shih@mediatek.com>
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt7981-clk.h>
#include <dt-bindings/reset/mt7629-reset.h>
#include <dt-bindings/pinctrl/mt65xx.h>
/ {
compatible = "mediatek,mt7981";
interrupt-parent = <&gic>;
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
mediatek,hwver = <&hwver>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
mediatek,hwver = <&hwver>;
};
};
gpt_clk: gpt_dummy20m {
compatible = "fixed-clock";
clock-frequency = <13000000>;
#clock-cells = <0>;
u-boot,dm-pre-reloc;
};
hwver: hwver {
compatible = "mediatek,hwver", "syscon";
reg = <0x8000000 0x1000>;
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
clock-frequency = <13000000>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
arm,cpu-registers-not-fw-configured;
};
timer0: timer@10008000 {
compatible = "mediatek,mt7986-timer";
reg = <0x10008000 0x1000>;
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gpt_clk>;
clock-names = "gpt-clk";
u-boot,dm-pre-reloc;
};
watchdog: watchdog@1001c000 {
compatible = "mediatek,mt7986-wdt";
reg = <0x1001c000 0x1000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;
status = "disabled";
};
gic: interrupt-controller@c000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
interrupt-controller;
reg = <0x0c000000 0x40000>, /* GICD */
<0x0c080000 0x200000>; /* GICR */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
fixed_plls: apmixedsys@1001e000 {
compatible = "mediatek,mt7981-fixed-plls";
reg = <0x1001e000 0x1000>;
#clock-cells = <1>;
u-boot,dm-pre-reloc;
};
topckgen: topckgen@1001b000 {
compatible = "mediatek,mt7981-topckgen";
reg = <0x1001b000 0x1000>;
clock-parent = <&fixed_plls>;
#clock-cells = <1>;
u-boot,dm-pre-reloc;
};
infracfg_ao: infracfg_ao@10001000 {
compatible = "mediatek,mt7981-infracfg_ao";
reg = <0x10001000 0x80>;
clock-parent = <&infracfg>;
#clock-cells = <1>;
u-boot,dm-pre-reloc;
};
infracfg: infracfg@10001000 {
compatible = "mediatek,mt7981-infracfg";
reg = <0x10001000 0x30>;
clock-parent = <&topckgen>;
#clock-cells = <1>;
u-boot,dm-pre-reloc;
};
pinctrl: pinctrl@11d00000 {
compatible = "mediatek,mt7981-pinctrl";
reg = <0x11d00000 0x1000>,
<0x11c00000 0x1000>,
<0x11c10000 0x1000>,
<0x11d20000 0x1000>,
<0x11e00000 0x1000>,
<0x11e20000 0x1000>,
<0x11f00000 0x1000>,
<0x11f10000 0x1000>,
<0x1000b000 0x1000>;
reg-names = "gpio_base", "iocfg_rt_base", "iocfg_rm_base",
"iocfg_rb_base", "iocfg_lb_base", "iocfg_bl_base",
"iocfg_tm_base", "iocfg_tl_base", "eint";
gpio: gpio-controller {
gpio-controller;
#gpio-cells = <2>;
};
};
pwm: pwm@10048000 {
compatible = "mediatek,mt7981-pwm";
reg = <0x10048000 0x1000>;
#clock-cells = <1>;
#pwm-cells = <2>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CK_INFRA_PWM>,
<&infracfg_ao CK_INFRA_PWM_BSEL>,
<&infracfg_ao CK_INFRA_PWM1_CK>,
<&infracfg_ao CK_INFRA_PWM2_CK>,
/* FIXME */
<&infracfg_ao CK_INFRA_PWM2_CK>;
assigned-clocks = <&topckgen CK_TOP_PWM_SEL>;
assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>;
clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
status = "disabled";
};
uart0: serial@11002000 {
compatible = "mediatek,hsuart";
reg = <0x11002000 0x400>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg_ao CK_INFRA_UART0_CK>;
assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
<&infracfg_ao CK_INFRA_UART0_SEL>;
assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
<&infracfg CK_INFRA_UART>;
mediatek,force-highspeed;
status = "disabled";
u-boot,dm-pre-reloc;
};
uart1: serial@11003000 {
compatible = "mediatek,hsuart";
reg = <0x11003000 0x400>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg_ao CK_INFRA_UART1_CK>;
assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
<&infracfg_ao CK_INFRA_UART1_SEL>;
assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
<&infracfg CK_INFRA_UART>;
mediatek,force-highspeed;
status = "disabled";
};
uart2: serial@11004000 {
compatible = "mediatek,hsuart";
reg = <0x11004000 0x400>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg_ao CK_INFRA_UART2_CK>;
assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
<&infracfg_ao CK_INFRA_UART2_SEL>;
assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
<&infracfg CK_INFRA_UART>;
mediatek,force-highspeed;
status = "disabled";
};
snand: snand@11005000 {
compatible = "mediatek,mt7986-snand";
reg = <0x11005000 0x1000>,
<0x11006000 0x1000>;
reg-names = "nfi", "ecc";
clocks = <&infracfg_ao CK_INFRA_SPINFI1_CK>,
<&infracfg_ao CK_INFRA_NFI1_CK>,
<&infracfg_ao CK_INFRA_NFI_HCK_CK>;
clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
<&topckgen CK_TOP_NFI1X_SEL>;
assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>,
<&topckgen CK_TOP_CB_M_D8>;
status = "disabled";
};
ethsys: syscon@15000000 {
compatible = "mediatek,mt7981-ethsys", "syscon";
reg = <0x15000000 0x1000>;
clock-parent = <&topckgen>;
#clock-cells = <1>;
#reset-cells = <1>;
};
eth: ethernet@15100000 {
compatible = "mediatek,mt7981-eth", "syscon";
reg = <0x15100000 0x20000>;
resets = <&ethsys ETHSYS_FE_RST>;
reset-names = "fe";
mediatek,ethsys = <&ethsys>;
mediatek,sgmiisys = <&sgmiisys0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
sgmiisys0: syscon@10060000 {
compatible = "mediatek,mt7986-sgmiisys", "syscon";
reg = <0x10060000 0x1000>;
pn_swap;
#clock-cells = <1>;
};
sgmiisys1: syscon@10070000 {
compatible = "mediatek,mt7986-sgmiisys", "syscon";
reg = <0x10070000 0x1000>;
#clock-cells = <1>;
};
spi0: spi@1100a000 {
compatible = "mediatek,ipm-spi";
reg = <0x1100a000 0x100>;
clocks = <&infracfg_ao CK_INFRA_SPI0_CK>,
<&topckgen CK_TOP_SPI_SEL>;
assigned-clocks = <&topckgen CK_TOP_SPI_SEL>,
<&infracfg CK_INFRA_SPI0_SEL>;
assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>,
<&topckgen CK_INFRA_ISPI0>;
clock-names = "sel-clk", "spi-clk";
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
spi1: spi@1100b000 {
compatible = "mediatek,ipm-spi";
reg = <0x1100b000 0x100>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
spi2: spi@11009000 {
compatible = "mediatek,ipm-spi";
reg = <0x11009000 0x100>;
clocks = <&infracfg_ao CK_INFRA_SPI0_CK>,
<&topckgen CK_TOP_SPI_SEL>;
assigned-clocks = <&topckgen CK_TOP_SPI_SEL>,
<&infracfg CK_INFRA_SPI0_SEL>;
assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>,
<&topckgen CK_INFRA_ISPI0>;
clock-names = "sel-clk", "spi-clk";
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
mmc0: mmc@11230000 {
compatible = "mediatek,mt7981-mmc";
reg = <0x11230000 0x1000>,
<0x11C20000 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CK_TOP_EMMC_400M>,
<&topckgen CK_TOP_EMMC_208M>,
<&infracfg_ao CK_INFRA_MSDC_CK>;
assigned-clocks = <&topckgen CK_TOP_EMMC_400M_SEL>,
<&topckgen CK_TOP_EMMC_208M_SEL>;
assigned-clock-parents = <&topckgen CK_TOP_CB_NET2_D2>,
<&topckgen CK_TOP_CB_M_D2>;
clock-names = "source", "hclk", "source_cg";
status = "disabled";
};
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Sam Shih <sam.shih@mediatek.com>
*/
&topckgen {
u-boot,dm-pre-reloc;
};
&pericfg {
u-boot,dm-pre-reloc;
};
&apmixedsys {
u-boot,dm-pre-reloc;
};
&timer0 {
u-boot,dm-pre-reloc;
};
&uart0 {
u-boot,dm-pre-reloc;
};
&snand {
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Sam Shih <sam.shih@mediatek.com>
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/clock/mt7986-clk.h>
#include <dt-bindings/reset/mt7629-reset.h>
#include <dt-bindings/pinctrl/mt65xx.h>
/ {
compatible = "mediatek,mt7986";
interrupt-parent = <&gic>;
#address-cells = <1>;
#size-cells = <1>;
config {
u-boot,mmc-env-partition = "u-boot-env";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
mediatek,hwver = <&hwver>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
mediatek,hwver = <&hwver>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
mediatek,hwver = <&hwver>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
mediatek,hwver = <&hwver>;
};
};
dummy_clk: dummy12m {
compatible = "fixed-clock";
clock-frequency = <12000000>;
#clock-cells = <0>;
/* must need this line, or uart uanable to get dummy_clk */
u-boot,dm-pre-reloc;
};
hwver: hwver {
compatible = "mediatek,hwver", "syscon";
reg = <0x8000000 0x1000>;
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
clock-frequency = <13000000>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
arm,cpu-registers-not-fw-configured;
};
timer0: timer@10008000 {
compatible = "mediatek,mt7986-timer";
reg = <0x10008000 0x1000>;
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CK_INFRA_CK_F26M>;
clock-names = "gpt-clk";
u-boot,dm-pre-reloc;
};
watchdog: watchdog@1001c000 {
compatible = "mediatek,mt7986-wdt";
reg = <0x1001c000 0x1000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;
status = "disabled";
};
gic: interrupt-controller@c000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
interrupt-controller;
reg = <0x0c000000 0x40000>, /* GICD */
<0x0c080000 0x200000>; /* GICR */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
fixed_plls: apmixedsys@1001E000 {
compatible = "mediatek,mt7986-fixed-plls";
reg = <0x1001E000 0x1000>;
#clock-cells = <1>;
};
topckgen: topckgen@1001B000 {
compatible = "mediatek,mt7986-topckgen";
reg = <0x1001B000 0x1000>;
clock-parent = <&fixed_plls>;
#clock-cells = <1>;
};
infracfg_ao: infracfg_ao@10001000 {
compatible = "mediatek,mt7986-infracfg_ao";
reg = <0x10001000 0x68>;
clock-parent = <&infracfg>;
#clock-cells = <1>;
};
infracfg: infracfg@10001040 {
compatible = "mediatek,mt7986-infracfg";
reg = <0x10001000 0x1000>;
clock-parent = <&topckgen>;
#clock-cells = <1>;
};
pinctrl: pinctrl@1001f000 {
compatible = "mediatek,mt7986-pinctrl";
reg = <0x1001f000 0x1000>,
<0x11c30000 0x1000>,
<0x11c40000 0x1000>,
<0x11e20000 0x1000>,
<0x11e30000 0x1000>,
<0x11f00000 0x1000>,
<0x11f10000 0x1000>,
<0x1000b000 0x1000>;
reg-names = "gpio_base", "iocfg_rt_base", "iocfg_rb_base",
"iocfg_lt_base", "iocfg_lb_base", "iocfg_tr_base",
"iocfg_tl_base", "eint";
gpio: gpio-controller {
gpio-controller;
#gpio-cells = <2>;
};
};
pwm: pwm@10048000 {
compatible = "mediatek,mt7986-pwm";
reg = <0x10048000 0x1000>;
#clock-cells = <1>;
#pwm-cells = <2>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CK_INFRA_PWM>,
<&infracfg_ao CK_INFRA_PWM_BSEL>,
<&infracfg_ao CK_INFRA_PWM1_CK>,
<&infracfg_ao CK_INFRA_PWM2_CK>;
assigned-clocks = <&topckgen CK_TOP_PWM_SEL>,
<&infracfg CK_INFRA_PWM_BSEL>,
<&infracfg CK_INFRA_PWM1_SEL>,
<&infracfg CK_INFRA_PWM2_SEL>;
assigned-clock-parents = <&topckgen CK_TOP_CB_M_D4>,
<&infracfg CK_INFRA_PWM>,
<&infracfg CK_INFRA_PWM>,
<&infracfg CK_INFRA_PWM>;
clock-names = "top", "main", "pwm1", "pwm2";
status = "disabled";
u-boot,dm-pre-reloc;
};
uart0: serial@11002000 {
compatible = "mediatek,hsuart";
reg = <0x11002000 0x400>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg_ao CK_INFRA_UART0_CK>;
assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
<&infracfg_ao CK_INFRA_UART0_SEL>;
assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
<&infracfg CK_INFRA_UART>;
mediatek,force-highspeed;
status = "disabled";
u-boot,dm-pre-reloc;
};
uart1: serial@11003000 {
compatible = "mediatek,hsuart";
reg = <0x11003000 0x400>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg_ao CK_INFRA_UART1_CK>;
assigned-clocks = <&infracfg CK_INFRA_UART1_SEL>;
assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>;
mediatek,force-highspeed;
status = "disabled";
};
uart2: serial@11004000 {
compatible = "mediatek,hsuart";
reg = <0x11004000 0x400>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg_ao CK_INFRA_UART2_CK>;
assigned-clocks = <&infracfg CK_INFRA_UART2_SEL>;
assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>;
mediatek,force-highspeed;
status = "disabled";
};
snand: snand@11005000 {
compatible = "mediatek,mt7986-snand";
reg = <0x11005000 0x1000>,
<0x11006000 0x1000>;
reg-names = "nfi", "ecc";
clocks = <&infracfg_ao CK_INFRA_SPINFI1_CK>,
<&infracfg_ao CK_INFRA_NFI1_CK>,
<&infracfg_ao CK_INFRA_NFI_HCK_CK>;
clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
<&topckgen CK_TOP_NFI1X_SEL>;
assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>,
<&topckgen CK_TOP_CB_M_D8>;
status = "disabled";
};
ethsys: syscon@15000000 {
compatible = "mediatek,mt7986-ethsys", "syscon";
reg = <0x15000000 0x1000>;
clock-parent = <&topckgen>;
#clock-cells = <1>;
#reset-cells = <1>;
};
eth: ethernet@15100000 {
compatible = "mediatek,mt7986-eth", "syscon";
reg = <0x15100000 0x20000>;
resets = <&ethsys ETHSYS_FE_RST>;
reset-names = "fe";
mediatek,ethsys = <&ethsys>;
mediatek,sgmiisys = <&sgmiisys0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
sgmiisys0: syscon@10060000 {
compatible = "mediatek,mt7986-sgmiisys", "syscon";
reg = <0x10060000 0x1000>;
#clock-cells = <1>;
};
sgmiisys1: syscon@10070000 {
compatible = "mediatek,mt7986-sgmiisys", "syscon";
reg = <0x10070000 0x1000>;
#clock-cells = <1>;
};
spi0: spi@1100a000 {
compatible = "mediatek,ipm-spi";
reg = <0x1100a000 0x100>;
clocks = <&infracfg_ao CK_INFRA_SPI0_CK>,
<&topckgen CK_TOP_SPI_SEL>;
assigned-clocks = <&topckgen CK_TOP_SPI_SEL>,
<&infracfg CK_INFRA_SPI0_SEL>;
assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>,
<&topckgen CK_INFRA_ISPI0>;
clock-names = "sel-clk", "spi-clk";
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
spi1: spi@1100b000 {
compatible = "mediatek,ipm-spi";
reg = <0x1100b000 0x100>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
mmc0: mmc@11230000 {
compatible = "mediatek,mt7986-mmc";
reg = <0x11230000 0x1000>,
<0x11C20000 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CK_TOP_EMMC_416M>,
<&topckgen CK_TOP_EMMC_250M>,
<&infracfg_ao CK_INFRA_MSDC_CK>;
assigned-clocks = <&topckgen CK_TOP_EMMC_416M_SEL>,
<&topckgen CK_TOP_EMMC_250M_SEL>;
assigned-clock-parents = <&topckgen CK_TOP_CB_M_416M>,
<&topckgen CK_TOP_NET1_D5_D2>;
clock-names = "source", "hclk", "source_cg";
status = "disabled";
};
xhci: xhci@11200000 {
compatible = "mediatek,mt7986-xhci",
"mediatek,mtk-xhci";
reg = <0x11200000 0x2e00>,
<0x11203e00 0x0100>;
reg-names = "mac", "ippc";
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
phys = <&u2port0 PHY_TYPE_USB2>,
<&u3port0 PHY_TYPE_USB3>,
<&u2port1 PHY_TYPE_USB2>;
clocks = <&dummy_clk>,
<&dummy_clk>,
<&dummy_clk>,
<&dummy_clk>,
<&dummy_clk>;
clock-names = "sys_ck",
"xhci_ck",
"ref_ck",
"mcu_ck",
"dma_ck";
tpl-support;
status = "okay";
};
usbtphy: usb-phy@11e10000 {
compatible = "mediatek,mt7986",
"mediatek,generic-tphy-v2";
#address-cells = <1>;
#size-cells = <1>;
status = "okay";
u2port0: usb-phy@11e10000 {
reg = <0x11e10000 0x700>;
clocks = <&dummy_clk>;
clock-names = "ref";
#phy-cells = <1>;
status = "okay";
};
u3port0: usb-phy@11e10700 {
reg = <0x11e10700 0x900>;
clocks = <&dummy_clk>;
clock-names = "ref";
#phy-cells = <1>;
status = "okay";
};
u2port1: usb-phy@11e11000 {
reg = <0x11e11000 0x700>;
clocks = <&dummy_clk>;
clock-names = "ref";
#phy-cells = <1>;
status = "okay";
};
};
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Sam Shih <sam.shih@mediatek.com>
*/
/dts-v1/;
#include "mt7986a-rfb.dts"
/ {
compatible = "mediatek,mt7986", "mediatek,mt7986-rfb",
"mediatek,mt7986-emmc-rfb";
bl2_verify {
bl2_compatible = "emmc";
};
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Sam Shih <sam.shih@mediatek.com>
*/
/dts-v1/;
#include "mt7986.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "mt7986-rfb";
compatible = "mediatek,mt7986", "mediatek,mt7986-rfb";
chosen {
stdout-path = &uart0;
tick-timer = &timer0;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
&uart0 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "disabled";
};
&eth {
status = "okay";
mediatek,gmac-id = <0>;
phy-mode = "sgmii";
mediatek,switch = "mt7531";
reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&pinctrl {
spi_flash_pins: spi0-pins-func-1 {
mux {
function = "flash";
groups = "spi0", "spi0_wp_hold";
};
conf-pu {
pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
};
conf-pd {
pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
};
};
snfi_pins: snfi-pins-func-1 {
mux {
function = "flash";
groups = "snfi";
};
clk {
pins = "SPI0_CLK";
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
};
conf-pu {
pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
drive-strength = <MTK_DRIVE_6mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_00>;
};
conf-pd {
pins = "SPI0_MOSI", "SPI0_MISO";
drive-strength = <MTK_DRIVE_6mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
};
};
spic_pins: spi1-pins-func-1 {
mux {
function = "spi";
groups = "spi1_2";
};
};
uart1_pins: spi1-pins-func-3 {
mux {
function = "uart";
groups = "uart1_2";
};
};
pwm_pins: pwm0-pins-func-1 {
mux {
function = "pwm";
groups = "pwm0";
};
};
mmc0_pins_default: mmc0default {
mux {
function = "flash";
groups = "emmc_51";
};
conf-cmd-dat {
pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
input-enable;
drive-strength = <MTK_DRIVE_4mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
conf-clk {
pins = "EMMC_CK";
drive-strength = <MTK_DRIVE_6mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
conf-dsl {
pins = "EMMC_DSL";
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
conf-rst {
pins = "EMMC_RSTB";
drive-strength = <MTK_DRIVE_4mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
};
&snand {
pinctrl-names = "default";
pinctrl-0 = <&snfi_pins>;
status = "okay";
quad-spi;
};
&spi0 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&spi_flash_pins>;
status = "okay";
must_tx;
enhance_timing;
dma_ext;
ipm_design;
support_quad;
tick_dly = <2>;
sample_sel = <0>;
spi_nor@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <52000000>;
};
spi_nand@1 {
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <52000000>;
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm_pins>;
status = "okay";
};
&watchdog {
status = "disabled";
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_default>;
bus-width = <8>;
max-frequency = <52000000>;
cap-mmc-highspeed;
cap-mmc-hw-reset;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
non-removable;
status = "okay";
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Sam Shih <sam.shih@mediatek.com>
*/
/dts-v1/;
#include "mt7986.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "mt7986-rfb";
compatible = "mediatek,mt7986", "mediatek,mt7986-rfb",
"mediatek,mt7986-sd-rfb";
chosen {
stdout-path = &uart0;
tick-timer = &timer0;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
&uart0 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "disabled";
};
&eth {
status = "okay";
mediatek,gmac-id = <0>;
phy-mode = "sgmii";
mediatek,switch = "mt7531";
reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&pinctrl {
spi_flash_pins: spi0-pins-func-1 {
mux {
function = "flash";
groups = "spi0", "spi0_wp_hold";
};
conf-pu {
pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
};
conf-pd {
pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
};
};
spic_pins: spi1-pins-func-1 {
mux {
function = "spi";
groups = "spi1_2";
};
};
uart1_pins: spi1-pins-func-3 {
mux {
function = "uart";
groups = "uart1_2";
};
};
pwm_pins: pwm0-pins-func-1 {
mux {
function = "pwm";
groups = "pwm0";
};
};
mmc0_pins_default: mmc0default {
mux {
function = "flash";
groups = "emmc_51";
};
conf-cmd-dat {
pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
input-enable;
drive-strength = <MTK_DRIVE_4mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
conf-clk {
pins = "EMMC_CK";
drive-strength = <MTK_DRIVE_6mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
conf-dsl {
pins = "EMMC_DSL";
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
conf-rst {
pins = "EMMC_RSTB";
drive-strength = <MTK_DRIVE_4mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
};
&spi0 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&spi_flash_pins>;
status = "okay";
must_tx;
enhance_timing;
dma_ext;
ipm_design;
support_quad;
tick_dly = <2>;
sample_sel = <0>;
spi_nor@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <52000000>;
};
spi_nand@1 {
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <52000000>;
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm_pins>;
status = "okay";
};
&watchdog {
status = "disabled";
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_default>;
bus-width = <4>;
max-frequency = <52000000>;
cap-sd-highspeed;
r_smpl = <1>;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_3p3v>;
status = "okay";
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Sam Shih <sam.shih@mediatek.com>
*/
/dts-v1/;
#include "mt7986a-rfb.dts"
/ {
compatible = "mediatek,mt7986", "mediatek,mt7986-rfb",
"mediatek,mt7986-emmc-rfb";
bl2_verify {
bl2_compatible = "emmc";
};
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Sam Shih <sam.shih@mediatek.com>
*/
/dts-v1/;
#include "mt7986.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "mt7986-rfb";
compatible = "mediatek,mt7986", "mediatek,mt7986-rfb";
chosen {
stdout-path = &uart0;
tick-timer = &timer0;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
&uart0 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "disabled";
};
&eth {
status = "okay";
mediatek,gmac-id = <0>;
phy-mode = "sgmii";
mediatek,switch = "mt7531";
reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&pinctrl {
spi_flash_pins: spi0-pins-func-1 {
mux {
function = "flash";
groups = "spi0", "spi0_wp_hold";
};
conf-pu {
pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
};
conf-pd {
pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
};
};
snfi_pins: snfi-pins-func-1 {
mux {
function = "flash";
groups = "snfi";
};
clk {
pins = "SPI0_CLK";
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
};
conf-pu {
pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
drive-strength = <MTK_DRIVE_6mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_00>;
};
conf-pd {
pins = "SPI0_MOSI", "SPI0_MISO";
drive-strength = <MTK_DRIVE_6mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
};
};
spic_pins: spi1-pins-func-1 {
mux {
function = "spi";
groups = "spi1_2";
};
};
uart1_pins: spi1-pins-func-3 {
mux {
function = "uart";
groups = "uart1_2";
};
};
pwm_pins: pwm0-pins-func-1 {
mux {
function = "pwm";
groups = "pwm0";
};
};
mmc0_pins_default: mmc0default {
mux {
function = "flash";
groups = "emmc_45";
input-schmitt-enable;
};
conf-cmd-dat {
pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
"SPI0_CS", "SPI0_HOLD", "SPI0_WP",
"SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
input-enable;
drive-strength = <MTK_DRIVE_4mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
conf-clk {
pins = "SPI1_CS";
drive-strength = <MTK_DRIVE_6mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
conf-rst {
pins = "PWM1";
drive-strength = <MTK_DRIVE_4mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
};
&snand {
pinctrl-names = "default";
pinctrl-0 = <&snfi_pins>;
status = "okay";
quad-spi;
};
&spi0 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&spi_flash_pins>;
status = "okay";
must_tx;
enhance_timing;
dma_ext;
ipm_design;
support_quad;
tick_dly = <2>;
sample_sel = <0>;
spi_nor@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <52000000>;
};
spi_nand@1 {
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <52000000>;
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm_pins>;
status = "okay";
};
&watchdog {
status = "disabled";
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_default>;
bus-width = <8>;
max-frequency = <52000000>;
cap-mmc-highspeed;
cap-mmc-hw-reset;
vmmc-supply = <&reg_3p3v>;
non-removable;
status = "okay";
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Sam Shih <sam.shih@mediatek.com>
*/
/dts-v1/;
#include "mt7986.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "mt7986-rfb";
compatible = "mediatek,mt7986", "mediatek,mt7986-rfb",
"mediatek,mt7986-sd-rfb";
chosen {
stdout-path = &uart0;
tick-timer = &timer0;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
&uart0 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "disabled";
};
&eth {
status = "okay";
mediatek,gmac-id = <0>;
phy-mode = "sgmii";
mediatek,switch = "mt7531";
reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&pinctrl {
spi_flash_pins: spi0-pins-func-1 {
mux {
function = "flash";
groups = "spi0", "spi0_wp_hold";
};
conf-pu {
pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
};
conf-pd {
pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
};
};
spic_pins: spi1-pins-func-1 {
mux {
function = "spi";
groups = "spi1_2";
};
};
uart1_pins: spi1-pins-func-3 {
mux {
function = "uart";
groups = "uart1_2";
};
};
pwm_pins: pwm0-pins-func-1 {
mux {
function = "pwm";
groups = "pwm0";
};
};
mmc0_pins_default: mmc0default {
mux {
function = "flash";
groups = "emmc_45";
input-schmitt-enable;
};
conf-cmd-dat {
pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
"SPI0_CS", "SPI0_HOLD", "SPI0_WP",
"SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
input-enable;
drive-strength = <MTK_DRIVE_4mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
conf-clk {
pins = "SPI1_CS";
drive-strength = <MTK_DRIVE_6mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
conf-rst {
pins = "PWM1";
drive-strength = <MTK_DRIVE_4mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
};
&spi0 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&spi_flash_pins>;
status = "okay";
must_tx;
enhance_timing;
dma_ext;
ipm_design;
support_quad;
tick_dly = <2>;
sample_sel = <0>;
spi_nor@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <52000000>;
};
spi_nand@1 {
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <52000000>;
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm_pins>;
status = "okay";
};
&watchdog {
status = "disabled";
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_default>;
bus-width = <4>;
max-frequency = <52000000>;
cap-sd-highspeed;
r_smpl = <1>;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_3p3v>;
status = "okay";
};

11
arch/arm/dts/mvebu-u-boot.dtsi
View file

@ -15,6 +15,17 @@
u-boot,dm-pre-reloc;
};
#ifdef CONFIG_ARMADA_375
/* Armada 375 has multiple timers, use timer1 here */
&timer1 {
u-boot,dm-pre-reloc;
};
#else
&timer {
u-boot,dm-pre-reloc;
};
#endif
#ifdef CONFIG_SPL_SPI
&spi0 {
u-boot,dm-pre-reloc;

18
arch/arm/dts/qcom-ipq4019.dtsi
View file

@ -75,9 +75,13 @@
u-boot,dm-pre-reloc;
};
pinctrl: qcom,tlmm@1000000 {
compatible = "qcom,tlmm-ipq4019";
soc_gpios: pinctrl@1000000 {
compatible = "qcom,ipq4019-pinctrl";
reg = <0x1000000 0x300000>;
gpio-controller;
gpio-count = <100>;
gpio-bank-name="soc";
#gpio-cells = <2>;
u-boot,dm-pre-reloc;
};
@ -90,16 +94,6 @@
u-boot,dm-pre-reloc;
};
soc_gpios: pinctrl@1000000 {
compatible = "qcom,ipq4019-pinctrl";
reg = <0x1000000 0x300000>;
gpio-controller;
gpio-count = <100>;
gpio-bank-name="soc";
#gpio-cells = <2>;
u-boot,dm-pre-reloc;
};
blsp1_spi1: spi@78b5000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x78b5000 0x600>;

6
arch/arm/dts/qcs404-evb-uboot.dtsi
View file

@ -22,3 +22,9 @@
};
};
};
&pms405_gpios {
usb_vbus_boost_pin {
gpios = <&pms405_gpios 2 0>;
};
};

120
arch/arm/dts/qcs404-evb.dts
View file

@ -38,7 +38,7 @@
compatible = "simple-bus";
pinctrl_north@1300000 {
compatible = "qcom,tlmm-qcs404";
compatible = "qcom,qcs404-pinctrl";
reg = <0x1300000 0x200000>;
blsp1_uart2: uart {
@ -52,6 +52,13 @@
reg = <0x1800000 0x80000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
#clock-cells = <1>;
};
reset: gcc-reset@1800000 {
compatible = "qcom,gcc-reset-qcs404";
reg = <0x1800000 0x80000>;
#reset-cells = <1>;
};
debug_uart: serial@78b1000 {
@ -75,6 +82,117 @@
mmc-ddr-1_8v;
mmc-hs400-1_8v;
};
usb3_phy: phy@78000 {
compatible = "qcom,usb-ss-28nm-phy";
#phy-cells = <0>;
reg = <0x78000 0x400>;
clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
<&gcc GCC_USB3_PHY_PIPE_CLK>;
clock-names = "ahb", "pipe";
resets = <&reset GCC_USB3_PHY_BCR>,
<&reset GCC_USB3PHY_PHY_BCR>;
reset-names = "com", "phy";
};
usb2_phy_prim: phy@7a000 {
compatible = "qcom,usb-hs-28nm-femtophy";
#phy-cells = <0>;
reg = <0x7a000 0x200>;
clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
<&gcc GCC_USB2A_PHY_SLEEP_CLK>;
clock-names = "ahb", "sleep";
resets = <&reset GCC_USB_HS_PHY_CFG_AHB_BCR>,
<&reset GCC_USB2A_PHY_BCR>;
reset-names = "phy", "por";
};
usb2_phy_sec: phy@7c000 {
compatible = "qcom,usb-hs-28nm-femtophy";
#phy-cells = <0>;
reg = <0x7c000 0x200>;
clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
<&gcc GCC_USB2A_PHY_SLEEP_CLK>;
clock-names = "ahb", "sleep";
resets = <&reset GCC_QUSB2_PHY_BCR>,
<&reset GCC_USB2_HS_PHY_ONLY_BCR>;
reset-names = "phy", "por";
};
usb3: usb@7678800 {
compatible = "qcom,dwc3";
reg = <0x7678800 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&gcc GCC_USB30_MASTER_CLK>,
<&gcc GCC_SYS_NOC_USB3_CLK>,
<&gcc GCC_USB30_SLEEP_CLK>,
<&gcc GCC_USB30_MOCK_UTMI_CLK>;
clock-names = "core", "iface", "sleep", "mock_utmi";
dwc3@7580000 {
compatible = "snps,dwc3";
reg = <0x7580000 0xcd00>;
phys = <&usb2_phy_prim>, <&usb3_phy>;
phy-names = "usb2-phy", "usb3-phy";
dr_mode = "host";
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x10>;
snps,usb3_lpm_capable;
maximum-speed = "super-speed";
};
};
usb2: usb@79b8800 {
compatible = "qcom,dwc3";
reg = <0x79b8800 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>,
<&gcc GCC_PCNOC_USB2_CLK>,
<&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>,
<&gcc GCC_USB20_MOCK_UTMI_CLK>;
clock-names = "core", "iface", "sleep", "mock_utmi";
dwc3@78c0000 {
compatible = "snps,dwc3";
reg = <0x78c0000 0xcc00>;
phys = <&usb2_phy_sec>;
phy-names = "usb2-phy";
dr_mode = "peripheral";
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x10>;
snps,usb3_lpm_capable;
maximum-speed = "high-speed";
};
};
spmi@200f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x200f000 0x1000
0x2400000 0x400000
0x2c00000 0x400000>;
#address-cells = <0x1>;
#size-cells = <0x1>;
pms405_0: pms405@0 {
compatible = "qcom,spmi-pmic";
reg = <0x0 0x1>;
#address-cells = <0x1>;
#size-cells = <0x1>;
pms405_gpios: pms405_gpios@c000 {
compatible = "qcom,pms405-gpio";
reg = <0xc000 0x400>;
gpio-controller;
gpio-count = <12>;
#gpio-cells = <2>;
gpio-bank-name="pmic";
};
};
};
};
};

9
arch/arm/dts/sama5d2.dtsi
View file

@ -799,18 +799,13 @@
status = "disabled";
};
pioA: gpio@fc038000 {
compatible = "atmel,sama5d2-gpio";
pioA: pinctrl@fc038000 {
compatible = "atmel,sama5d2-pinctrl";
reg = <0xfc038000 0x600>;
clocks = <&pioA_clk>;
gpio-controller;
#gpio-cells = <2>;
u-boot,dm-pre-reloc;
pinctrl {
compatible = "atmel,sama5d2-pinctrl";
u-boot,dm-pre-reloc;
};
};
};
};

84
arch/arm/dts/sama5d27_som1.dtsi
View file

@ -103,54 +103,52 @@
status = "okay";
};
pioA: gpio@fc038000 {
pinctrl {
pinctrl_i2c0_default: i2c0_default {
pinmux = <PIN_PD21__TWD0>,
<PIN_PD22__TWCK0>;
bias-disable;
};
pioA: pinctrl@fc038000 {
pinctrl_i2c0_default: i2c0_default {
pinmux = <PIN_PD21__TWD0>,
<PIN_PD22__TWCK0>;
bias-disable;
};
pinctrl_i2c1_default: i2c1_default {
pinmux = <PIN_PD4__TWD1>,
<PIN_PD5__TWCK1>;
bias-disable;
};
pinctrl_i2c1_default: i2c1_default {
pinmux = <PIN_PD4__TWD1>,
<PIN_PD5__TWCK1>;
bias-disable;
};
pinctrl_macb0_phy_irq: macb0_phy_irq {
pinmux = <PIN_PD31__GPIO>;
bias-disable;
};
pinctrl_macb0_phy_irq: macb0_phy_irq {
pinmux = <PIN_PD31__GPIO>;
bias-disable;
};
pinctrl_macb0_rmii: macb0_rmii {
pinmux = <PIN_PD9__GTXCK>,
<PIN_PD10__GTXEN>,
<PIN_PD11__GRXDV>,
<PIN_PD12__GRXER>,
<PIN_PD13__GRX0>,
<PIN_PD14__GRX1>,
<PIN_PD15__GTX0>,
<PIN_PD16__GTX1>,
<PIN_PD17__GMDC>,
<PIN_PD18__GMDIO>;
bias-disable;
};
pinctrl_macb0_rmii: macb0_rmii {
pinmux = <PIN_PD9__GTXCK>,
<PIN_PD10__GTXEN>,
<PIN_PD11__GRXDV>,
<PIN_PD12__GRXER>,
<PIN_PD13__GRX0>,
<PIN_PD14__GRX1>,
<PIN_PD15__GTX0>,
<PIN_PD16__GTX1>,
<PIN_PD17__GMDC>,
<PIN_PD18__GMDIO>;
bias-disable;
};
pinctrl_qspi1_sck_cs_default: qspi1_sck_cs_default {
pinmux = <PIN_PB5__QSPI1_SCK>,
<PIN_PB6__QSPI1_CS>;
bias-disable;
u-boot,dm-pre-reloc;
};
pinctrl_qspi1_sck_cs_default: qspi1_sck_cs_default {
pinmux = <PIN_PB5__QSPI1_SCK>,
<PIN_PB6__QSPI1_CS>;
bias-disable;
u-boot,dm-pre-reloc;
};
pinctrl_qspi1_dat_default: qspi1_dat_default {
pinmux = <PIN_PB7__QSPI1_IO0>,
<PIN_PB8__QSPI1_IO1>,
<PIN_PB9__QSPI1_IO2>,
<PIN_PB10__QSPI1_IO3>;
bias-pull-up;
u-boot,dm-pre-reloc;
};
pinctrl_qspi1_dat_default: qspi1_dat_default {
pinmux = <PIN_PB7__QSPI1_IO0>,
<PIN_PB8__QSPI1_IO1>,
<PIN_PB9__QSPI1_IO2>,
<PIN_PB10__QSPI1_IO3>;
bias-pull-up;
u-boot,dm-pre-reloc;
};
};
};

54
arch/arm/dts/sama5d27_wlsom1.dtsi
View file

@ -41,36 +41,34 @@
};
};
pioA: gpio@fc038000 {
pinctrl {
pinctrl_macb0_phy_irq: macb0_phy_irq {
pinmux = <PIN_PB24__GPIO>;
bias-disable;
};
pioA: pinctrl@fc038000 {
pinctrl_macb0_phy_irq: macb0_phy_irq {
pinmux = <PIN_PB24__GPIO>;
bias-disable;
};
pinctrl_macb0_rmii: macb0_rmii {
pinmux = <PIN_PB14__GTXCK>,
<PIN_PB15__GTXEN>,
<PIN_PB16__GRXDV>,
<PIN_PB17__GRXER>,
<PIN_PB18__GRX0>,
<PIN_PB19__GRX1>,
<PIN_PB20__GTX0>,
<PIN_PB21__GTX1>,
<PIN_PB22__GMDC>,
<PIN_PB23__GMDIO>;
bias-disable;
};
pinctrl_macb0_rmii: macb0_rmii {
pinmux = <PIN_PB14__GTXCK>,
<PIN_PB15__GTXEN>,
<PIN_PB16__GRXDV>,
<PIN_PB17__GRXER>,
<PIN_PB18__GRX0>,
<PIN_PB19__GRX1>,
<PIN_PB20__GTX0>,
<PIN_PB21__GTX1>,
<PIN_PB22__GMDC>,
<PIN_PB23__GMDIO>;
bias-disable;
};
pinctrl_qspi1_default: qspi1_default {
pinmux = <PIN_PB5__QSPI1_SCK>,
<PIN_PB6__QSPI1_CS>,
<PIN_PB7__QSPI1_IO0>,
<PIN_PB8__QSPI1_IO1>,
<PIN_PB9__QSPI1_IO2>,
<PIN_PB10__QSPI1_IO3>;
bias-pull-up;
};
pinctrl_qspi1_default: qspi1_default {
pinmux = <PIN_PB5__QSPI1_SCK>,
<PIN_PB6__QSPI1_CS>,
<PIN_PB7__QSPI1_IO0>,
<PIN_PB8__QSPI1_IO1>,
<PIN_PB9__QSPI1_IO2>,
<PIN_PB10__QSPI1_IO3>;
bias-pull-up;
};
};
};

16
arch/arm/dts/sama7g5.dtsi
View file

@ -187,8 +187,8 @@
reg = <0xe0008000 0x20>;
};
pinctrl: pinctrl@e0014000 {
compatible = "microchip,sama7g5-gpio";
pioA: pinctrl@e0014000 {
compatible = "microchip,sama7g5-pinctrl";
reg = <0xe0014000 0x800>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
@ -196,14 +196,10 @@
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
pioA: pinctrl_default {
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
compatible = "microchip,sama7g5-pinctrl";
};
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
};
pmc: pmc@e0018000 {

2
arch/arm/dts/sdm845.dtsi
View file

@ -37,7 +37,7 @@
};
tlmm_north: pinctrl_north@3900000 {
compatible = "qcom,tlmm-sdm845";
compatible = "qcom,sdm845-pinctrl";
reg = <0x3900000 0x400000>;
gpio-count = <150>;
gpio-controller;

2
arch/arm/dts/stm32429i-eval-u-boot.dtsi
View file

@ -218,6 +218,6 @@
};
};
&timer5 {
&timers5 {
u-boot,dm-pre-reloc;
};

18
arch/arm/dts/stm32746g-eval.dts
View file

@ -45,12 +45,10 @@
};
};
gpio_keys {
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
button@0 {
button-0 {
label = "Wake up";
linux,code = <KEY_WAKEUP>;
gpios = <&gpioc 13 0>;
@ -160,6 +158,18 @@
bus-width = <4>;
};
&timers5 {
/* Override timer5 to act as clockevent */
compatible = "st,stm32-timer";
interrupts = <50>;
status = "okay";
/delete-property/#address-cells;
/delete-property/#size-cells;
/delete-property/clock-names;
/delete-node/pwm;
/delete-node/timer@4;
};
&usart1 {
pinctrl-0 = <&usart1_pins_a>;
pinctrl-names = "default";

2
arch/arm/dts/stm32f4-pinctrl.dtsi
View file

@ -9,7 +9,7 @@
/ {
soc {
pinctrl: pin-controller {
pinctrl: pinctrl@40020000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x40020000 0x3000>;

8
arch/arm/dts/stm32f429-disco-u-boot.dtsi
View file

@ -27,10 +27,6 @@
soc {
u-boot,dm-pre-reloc;
pin-controller {
u-boot,dm-pre-reloc;
};
fmc: fmc@A0000000 {
compatible = "st,stm32-fmc";
reg = <0xa0000000 0x1000>;
@ -123,6 +119,8 @@
};
&pinctrl {
u-boot,dm-pre-reloc;
usart1_pins_a: usart1-0 {
u-boot,dm-pre-reloc;
pins1 {
@ -193,6 +191,6 @@
u-boot,dm-pre-reloc;
};
&timer5 {
&timers5 {
u-boot,dm-pre-reloc;
};

20
arch/arm/dts/stm32f429-disco.dts
View file

@ -39,12 +39,10 @@
};
};
gpio_keys {
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
button@0 {
button-0 {
label = "User";
linux,code = <KEY_HOME>;
gpios = <&gpioa 0 0>;
@ -152,7 +150,7 @@
display: display@1{
/* Connect panel-ilitek-9341 to ltdc */
compatible = "st,sf-tc240t-9370-t";
compatible = "st,sf-tc240t-9370-t", "ilitek,ili9341";
reg = <1>;
spi-3wire;
spi-max-frequency = <10000000>;
@ -165,6 +163,18 @@
};
};
&timers5 {
/* Override timer5 to act as clockevent */
compatible = "st,stm32-timer";
interrupts = <50>;
status = "okay";
/delete-property/#address-cells;
/delete-property/#size-cells;
/delete-property/clock-names;
/delete-node/pwm;
/delete-node/timer@4;
};
&usart1 {
pinctrl-0 = <&usart1_pins_a>;
pinctrl-names = "default";

72
arch/arm/dts/stm32f429-pinctrl.dtsi
View file

@ -6,54 +6,50 @@
#include "stm32f4-pinctrl.dtsi"
/ {
soc {
pinctrl: pin-controller {
compatible = "st,stm32f429-pinctrl";
&pinctrl {
compatible = "st,stm32f429-pinctrl";
gpioa: gpio@40020000 {
gpio-ranges = <&pinctrl 0 0 16>;
};
gpioa: gpio@40020000 {
gpio-ranges = <&pinctrl 0 0 16>;
};
gpiob: gpio@40020400 {
gpio-ranges = <&pinctrl 0 16 16>;
};
gpiob: gpio@40020400 {
gpio-ranges = <&pinctrl 0 16 16>;
};
gpioc: gpio@40020800 {
gpio-ranges = <&pinctrl 0 32 16>;
};
gpioc: gpio@40020800 {
gpio-ranges = <&pinctrl 0 32 16>;
};
gpiod: gpio@40020c00 {
gpio-ranges = <&pinctrl 0 48 16>;
};
gpiod: gpio@40020c00 {
gpio-ranges = <&pinctrl 0 48 16>;
};
gpioe: gpio@40021000 {
gpio-ranges = <&pinctrl 0 64 16>;
};
gpioe: gpio@40021000 {
gpio-ranges = <&pinctrl 0 64 16>;
};
gpiof: gpio@40021400 {
gpio-ranges = <&pinctrl 0 80 16>;
};
gpiof: gpio@40021400 {
gpio-ranges = <&pinctrl 0 80 16>;
};
gpiog: gpio@40021800 {
gpio-ranges = <&pinctrl 0 96 16>;
};
gpiog: gpio@40021800 {
gpio-ranges = <&pinctrl 0 96 16>;
};
gpioh: gpio@40021c00 {
gpio-ranges = <&pinctrl 0 112 16>;
};
gpioh: gpio@40021c00 {
gpio-ranges = <&pinctrl 0 112 16>;
};
gpioi: gpio@40022000 {
gpio-ranges = <&pinctrl 0 128 16>;
};
gpioi: gpio@40022000 {
gpio-ranges = <&pinctrl 0 128 16>;
};
gpioj: gpio@40022400 {
gpio-ranges = <&pinctrl 0 144 16>;
};
gpioj: gpio@40022400 {
gpio-ranges = <&pinctrl 0 144 16>;
};
gpiok: gpio@40022800 {
gpio-ranges = <&pinctrl 0 160 8>;
};
};
gpiok: gpio@40022800 {
gpio-ranges = <&pinctrl 0 160 8>;
};
};

69
arch/arm/dts/stm32f429.dtsi
View file

@ -52,14 +52,6 @@
};
};
timer2: timer@40000000 {
compatible = "st,stm32-timer";
reg = <0x40000000 0x400>;
interrupts = <28>;
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
status = "disabled";
};
timers2: timers@40000000 {
#address-cells = <1>;
#size-cells = <0>;
@ -82,14 +74,6 @@
};
};
timer3: timer@40000400 {
compatible = "st,stm32-timer";
reg = <0x40000400 0x400>;
interrupts = <29>;
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
status = "disabled";
};
timers3: timers@40000400 {
#address-cells = <1>;
#size-cells = <0>;
@ -112,14 +96,6 @@
};
};
timer4: timer@40000800 {
compatible = "st,stm32-timer";
reg = <0x40000800 0x400>;
interrupts = <30>;
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
status = "disabled";
};
timers4: timers@40000800 {
#address-cells = <1>;
#size-cells = <0>;
@ -142,13 +118,6 @@
};
};
timer5: timer@40000c00 {
compatible = "st,stm32-timer";
reg = <0x40000c00 0x400>;
interrupts = <50>;
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
};
timers5: timers@40000c00 {
#address-cells = <1>;
#size-cells = <0>;
@ -171,14 +140,6 @@
};
};
timer6: timer@40001000 {
compatible = "st,stm32-timer";
reg = <0x40001000 0x400>;
interrupts = <54>;
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
status = "disabled";
};
timers6: timers@40001000 {
#address-cells = <1>;
#size-cells = <0>;
@ -195,14 +156,6 @@
};
};
timer7: timer@40001400 {
compatible = "st,stm32-timer";
reg = <0x40001400 0x400>;
interrupts = <55>;
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
status = "disabled";
};
timers7: timers@40001400 {
#address-cells = <1>;
#size-cells = <0>;
@ -242,8 +195,6 @@
};
timers13: timers@40001c00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40001C00 0x400>;
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
@ -258,8 +209,6 @@
};
timers14: timers@40002000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40002000 0x400>;
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
@ -525,7 +474,7 @@
};
};
sdio: sdio@40012c00 {
sdio: mmc@40012c00 {
compatible = "arm,pl180", "arm,primecell";
arm,primecell-periphid = <0x00880180>;
reg = <0x40012c00 0x400>;
@ -592,8 +541,6 @@
};
timers10: timers@40014400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40014400 0x400>;
clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
@ -608,8 +555,6 @@
};
timers11: timers@40014800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40014800 0x400>;
clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
@ -668,7 +613,7 @@
status = "disabled";
};
rcc: rcc@40023810 {
rcc: rcc@40023800 {
#reset-cells = <1>;
#clock-cells = <2>;
compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
@ -726,6 +671,16 @@
status = "disabled";
};
dma2d: dma2d@4002b000 {
compatible = "st,stm32-dma2d";
reg = <0x4002b000 0xc00>;
interrupts = <90>;
resets = <&rcc STM32F4_AHB1_RESET(DMA2D)>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2D)>;
clock-names = "dma2d";
status = "disabled";
};
usbotg_hs: usb@40040000 {
compatible = "snps,dwc2";
reg = <0x40040000 0x40000>;

7
arch/arm/dts/stm32f469-disco-u-boot.dtsi
View file

@ -28,9 +28,6 @@
soc {
u-boot,dm-pre-reloc;
pin-controller {
u-boot,dm-pre-reloc;
};
fmc: fmc@A0000000 {
compatible = "st,stm32-fmc";
@ -138,6 +135,8 @@
};
&pinctrl {
u-boot,dm-pre-reloc;
fmc_pins_d32: fmc_d32@0 {
u-boot,dm-pre-reloc;
pins
@ -256,6 +255,6 @@
u-boot,dm-pre-reloc;
};
&timer5 {
&timers5 {
u-boot,dm-pre-reloc;
};

24
arch/arm/dts/stm32f469-disco.dts
View file

@ -19,7 +19,7 @@
stdout-path = "serial0:115200n8";
};
memory@00000000 {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x1000000>;
};
@ -63,12 +63,10 @@
};
};
gpio_keys {
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
button@0 {
button-0 {
label = "User";
linux,code = <KEY_WAKEUP>;
gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
@ -93,6 +91,10 @@
clock-frequency = <8000000>;
};
&dma2d {
status = "okay";
};
&dsi {
#address-cells = <1>;
#size-cells = <0>;
@ -185,6 +187,18 @@
bus-width = <4>;
};
&timers5 {
/* Override timer5 to act as clockevent */
compatible = "st,stm32-timer";
interrupts = <50>;
status = "okay";
/delete-property/#address-cells;
/delete-property/#size-cells;
/delete-property/clock-names;
/delete-node/pwm;
/delete-node/timer@4;
};
&usart3 {
pinctrl-0 = <&usart3_pins_a>;
pinctrl-names = "default";

74
arch/arm/dts/stm32f469-pinctrl.dtsi
View file

@ -5,55 +5,51 @@
#include "stm32f4-pinctrl.dtsi"
/ {
soc {
pinctrl: pin-controller {
compatible = "st,stm32f469-pinctrl";
&pinctrl {
compatible = "st,stm32f469-pinctrl";
gpioa: gpio@40020000 {
gpio-ranges = <&pinctrl 0 0 16>;
};
gpioa: gpio@40020000 {
gpio-ranges = <&pinctrl 0 0 16>;
};
gpiob: gpio@40020400 {
gpio-ranges = <&pinctrl 0 16 16>;
};
gpiob: gpio@40020400 {
gpio-ranges = <&pinctrl 0 16 16>;
};
gpioc: gpio@40020800 {
gpio-ranges = <&pinctrl 0 32 16>;
};
gpioc: gpio@40020800 {
gpio-ranges = <&pinctrl 0 32 16>;
};
gpiod: gpio@40020c00 {
gpio-ranges = <&pinctrl 0 48 16>;
};
gpiod: gpio@40020c00 {
gpio-ranges = <&pinctrl 0 48 16>;
};
gpioe: gpio@40021000 {
gpio-ranges = <&pinctrl 0 64 16>;
};
gpioe: gpio@40021000 {
gpio-ranges = <&pinctrl 0 64 16>;
};
gpiof: gpio@40021400 {
gpio-ranges = <&pinctrl 0 80 16>;
};
gpiof: gpio@40021400 {
gpio-ranges = <&pinctrl 0 80 16>;
};
gpiog: gpio@40021800 {
gpio-ranges = <&pinctrl 0 96 16>;
};
gpiog: gpio@40021800 {
gpio-ranges = <&pinctrl 0 96 16>;
};
gpioh: gpio@40021c00 {
gpio-ranges = <&pinctrl 0 112 16>;
};
gpioh: gpio@40021c00 {
gpio-ranges = <&pinctrl 0 112 16>;
};
gpioi: gpio@40022000 {
gpio-ranges = <&pinctrl 0 128 16>;
};
gpioi: gpio@40022000 {
gpio-ranges = <&pinctrl 0 128 16>;
};
gpioj: gpio@40022400 {
gpio-ranges = <&pinctrl 0 144 6>,
<&pinctrl 12 156 4>;
};
gpioj: gpio@40022400 {
gpio-ranges = <&pinctrl 0 144 6>,
<&pinctrl 12 156 4>;
};
gpiok: gpio@40022800 {
gpio-ranges = <&pinctrl 3 163 5>;
};
};
gpiok: gpio@40022800 {
gpio-ranges = <&pinctrl 3 163 5>;
};
};

2
arch/arm/dts/stm32f7-pinctrl.dtsi
View file

@ -9,7 +9,7 @@
/ {
soc {
pinctrl: pin-controller {
pinctrl: pinctrl@40020000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x40020000 0x3000>;

2
arch/arm/dts/stm32f7-u-boot.dtsi
View file

@ -119,7 +119,7 @@
u-boot,dm-pre-reloc;
};
&timer5 {
&timers5 {
u-boot,dm-pre-reloc;
};

12
arch/arm/dts/stm32f746-disco.dts
View file

@ -73,6 +73,18 @@
bus-width = <4>;
};
&timers5 {
/* Override timer5 to act as clockevent */
compatible = "st,stm32-timer";
interrupts = <50>;
status = "okay";
/delete-property/#address-cells;
/delete-property/#size-cells;
/delete-property/clock-names;
/delete-node/pwm;
/delete-node/timer@4;
};
&usart1 {
pinctrl-0 = <&usart1_pins_b>;
pinctrl-names = "default";

67
arch/arm/dts/stm32f746.dtsi
View file

@ -39,14 +39,6 @@
};
soc {
timer2: timer@40000000 {
compatible = "st,stm32-timer";
reg = <0x40000000 0x400>;
interrupts = <28>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
status = "disabled";
};
timers2: timers@40000000 {
#address-cells = <1>;
#size-cells = <0>;
@ -69,14 +61,6 @@
};
};
timer3: timer@40000400 {
compatible = "st,stm32-timer";
reg = <0x40000400 0x400>;
interrupts = <29>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
status = "disabled";
};
timers3: timers@40000400 {
#address-cells = <1>;
#size-cells = <0>;
@ -99,14 +83,6 @@
};
};
timer4: timer@40000800 {
compatible = "st,stm32-timer";
reg = <0x40000800 0x400>;
interrupts = <30>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
status = "disabled";
};
timers4: timers@40000800 {
#address-cells = <1>;
#size-cells = <0>;
@ -129,13 +105,6 @@
};
};
timer5: timer@40000c00 {
compatible = "st,stm32-timer";
reg = <0x40000c00 0x400>;
interrupts = <50>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
};
timers5: timers@40000c00 {
#address-cells = <1>;
#size-cells = <0>;
@ -158,14 +127,6 @@
};
};
timer6: timer@40001000 {
compatible = "st,stm32-timer";
reg = <0x40001000 0x400>;
interrupts = <54>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
status = "disabled";
};
timers6: timers@40001000 {
#address-cells = <1>;
#size-cells = <0>;
@ -182,14 +143,6 @@
};
};
timer7: timer@40001400 {
compatible = "st,stm32-timer";
reg = <0x40001400 0x400>;
interrupts = <55>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
status = "disabled";
};
timers7: timers@40001400 {
#address-cells = <1>;
#size-cells = <0>;
@ -229,8 +182,6 @@
};
timers13: timers@40001c00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40001C00 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
@ -245,8 +196,6 @@
};
timers14: timers@40002000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40002000 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
@ -313,7 +262,6 @@
clocks = <&rcc 1 CLK_I2C1>;
#address-cells = <1>;
#size-cells = <0>;
i2c-analog-filter;
status = "disabled";
};
@ -326,20 +274,18 @@
clocks = <&rcc 1 CLK_I2C2>;
#address-cells = <1>;
#size-cells = <0>;
i2c-analog-filter;
status = "disabled";
};
i2c3: i2c@40005C00 {
i2c3: i2c@40005c00 {
compatible = "st,stm32f7-i2c";
reg = <0x40005C00 0x400>;
reg = <0x40005c00 0x400>;
interrupts = <72>,
<73>;
resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
clocks = <&rcc 1 CLK_I2C3>;
#address-cells = <1>;
#size-cells = <0>;
i2c-analog-filter;
status = "disabled";
};
@ -352,7 +298,6 @@
clocks = <&rcc 1 CLK_I2C4>;
#address-cells = <1>;
#size-cells = <0>;
i2c-analog-filter;
status = "disabled";
};
@ -441,7 +386,7 @@
status = "disabled";
};
sdio2: sdio2@40011c00 {
sdio2: mmc@40011c00 {
compatible = "arm,pl180", "arm,primecell";
arm,primecell-periphid = <0x00880180>;
reg = <0x40011c00 0x400>;
@ -452,7 +397,7 @@
status = "disabled";
};
sdio1: sdio1@40012c00 {
sdio1: mmc@40012c00 {
compatible = "arm,pl180", "arm,primecell";
arm,primecell-periphid = <0x00880180>;
reg = <0x40012c00 0x400>;
@ -499,8 +444,6 @@
};
timers10: timers@40014400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40014400 0x400>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
@ -515,8 +458,6 @@
};
timers11: timers@40014800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40014800 0x400>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;

18
arch/arm/dts/stm32f769-disco.dts
View file

@ -39,12 +39,10 @@
};
};
gpio_keys {
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
button@0 {
button-0 {
label = "User";
linux,code = <KEY_HOME>;
gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
@ -103,6 +101,18 @@
bus-width = <4>;
};
&timers5 {
/* Override timer5 to act as clockevent */
compatible = "st,stm32-timer";
interrupts = <50>;
status = "okay";
/delete-property/#address-cells;
/delete-property/#size-cells;
/delete-property/clock-names;
/delete-node/pwm;
/delete-node/timer@4;
};
&usart1 {
pinctrl-0 = <&usart1_pins_a>;
pinctrl-names = "default";

19
arch/arm/dts/stm32h743.dtsi
View file

@ -124,7 +124,6 @@
<32>;
resets = <&rcc STM32H7_APB1L_RESET(I2C1)>;
clocks = <&rcc I2C1_CK>;
i2c-analog-filter;
status = "disabled";
};
@ -137,7 +136,6 @@
<34>;
resets = <&rcc STM32H7_APB1L_RESET(I2C2)>;
clocks = <&rcc I2C2_CK>;
i2c-analog-filter;
status = "disabled";
};
@ -150,7 +148,6 @@
<73>;
resets = <&rcc STM32H7_APB1L_RESET(I2C3)>;
clocks = <&rcc I2C3_CK>;
i2c-analog-filter;
status = "disabled";
};
@ -337,12 +334,12 @@
dma-requests = <32>;
};
sdmmc1: sdmmc@52007000 {
sdmmc1: mmc@52007000 {
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x10153180>;
reg = <0x52007000 0x1000>;
interrupts = <49>;
interrupt-names = "cmd_irq";
interrupt-names = "cmd_irq";
clocks = <&rcc SDMMC1_CK>;
clock-names = "apb_pclk";
resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
@ -351,18 +348,19 @@
max-frequency = <120000000>;
};
sdmmc2: sdmmc@48022400 {
sdmmc2: mmc@48022400 {
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x10153180>;
reg = <0x48022400 0x400>;
interrupts = <124>;
interrupt-names = "cmd_irq";
interrupt-names = "cmd_irq";
clocks = <&rcc SDMMC2_CK>;
clock-names = "apb_pclk";
resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <120000000>;
status = "disabled";
};
exti: interrupt-controller@58000000 {
@ -398,7 +396,6 @@
<96>;
resets = <&rcc STM32H7_APB4_RESET(I2C4)>;
clocks = <&rcc I2C4_CK>;
i2c-analog-filter;
status = "disabled";
};
@ -452,8 +449,6 @@
};
lptimer4: timer@58002c00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x58002c00 0x400>;
clocks = <&rcc LPTIM4_CK>;
@ -468,8 +463,6 @@
};
lptimer5: timer@58003000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x58003000 0x400>;
clocks = <&rcc LPTIM5_CK>;
@ -554,7 +547,7 @@
status = "disabled";
};
pinctrl: pin-controller@58020000 {
pinctrl: pinctrl@58020000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32h743-pinctrl";

8
arch/arm/dts/stm32h743i-disco.dts
View file

@ -41,10 +41,10 @@
&mac {
status = "disabled";
pinctrl-0 = <&ethernet_rmii>;
pinctrl-names = "default";
phy-mode = "rmii";
phy-handle = <&phy0>;
pinctrl-0 = <&ethernet_rmii>;
pinctrl-names = "default";
phy-mode = "rmii";
phy-handle = <&phy0>;
mdio0 {
#address-cells = <1>;

8
arch/arm/dts/stm32h743i-eval.dts
View file

@ -115,10 +115,10 @@
&mac {
status = "disabled";
pinctrl-0 = <&ethernet_rmii>;
pinctrl-names = "default";
phy-mode = "rmii";
phy-handle = <&phy0>;
pinctrl-0 = <&ethernet_rmii>;
pinctrl-names = "default";
phy-mode = "rmii";
phy-handle = <&phy0>;
mdio0 {
#address-cells = <1>;

8
arch/arm/dts/stm32h750i-art-pi.dts
View file

@ -87,10 +87,10 @@
&mac {
status = "disabled";
pinctrl-0 = <&ethernet_rmii>;
pinctrl-names = "default";
phy-mode = "rmii";
phy-handle = <&phy0>;
pinctrl-0 = <&ethernet_rmii>;
pinctrl-names = "default";
phy-mode = "rmii";
phy-handle = <&phy0>;
mdio0 {
#address-cells = <1>;

10
arch/arm/dts/stm32mp13-u-boot.dtsi
View file

@ -17,6 +17,12 @@
pinctrl0 = &pinctrl;
};
firmware {
optee {
u-boot,dm-pre-reloc;
};
};
/* need PSCI for sysreset during board_f */
psci {
u-boot,dm-pre-proper;
@ -82,10 +88,6 @@
u-boot,dm-pre-reloc;
};
&optee {
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};

28
arch/arm/dts/stm32mp131.dtsi
View file

@ -27,21 +27,8 @@
interrupt-parent = <&intc>;
};
scmi_sram: sram@2ffff000 {
compatible = "mmio-sram";
reg = <0x2ffff000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2ffff000 0x1000>;
scmi_shm: scmi_shm@0 {
compatible = "arm,scmi-shmem";
reg = <0 0x80>;
};
};
firmware {
optee: optee {
optee {
method = "smc";
compatible = "linaro,optee-tz";
};
@ -151,6 +138,19 @@
interrupt-parent = <&intc>;
ranges;
scmi_sram: sram@2ffff000 {
compatible = "mmio-sram";
reg = <0x2ffff000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2ffff000 0x1000>;
scmi_shm: scmi-sram@0 {
compatible = "arm,scmi-shmem";
reg = <0 0x80>;
};
};
uart4: serial@40010000 {
compatible = "st,stm32h7-uart";
reg = <0x40010000 0x400>;

4
arch/arm/dts/stm32mp135f-dk.dts
View file

@ -31,8 +31,8 @@
#size-cells = <1>;
ranges;
optee@de000000 {
reg = <0xde000000 0x2000000>;
optee@dd000000 {
reg = <0xdd000000 0x3000000>;
no-map;
};
};

16
arch/arm/dts/stm32mp15-ddr.dtsi
View file

@ -4,7 +4,22 @@
*/
#include <linux/stringify.h>
#ifdef CONFIG_SPL
&ddr {
clocks = <&rcc AXIDCG>,
<&rcc DDRC1>,
<&rcc DDRC2>,
<&rcc DDRPHYC>,
<&rcc DDRCAPB>,
<&rcc DDRPHYCAPB>;
clock-names = "axidcg",
"ddrc1",
"ddrc2",
"ddrphyc",
"ddrcapb",
"ddrphycapb";
config-DDR_MEM_COMPATIBLE {
u-boot,dm-pre-reloc;
@ -119,6 +134,7 @@
status = "okay";
};
};
#endif
#undef DDR_MEM_COMPATIBLE
#undef DDR_MEM_NAME

64
arch/arm/dts/stm32mp15-pinctrl.dtsi
View file

@ -151,6 +151,43 @@
};
};
dcmi_pins_c: dcmi-2 {
pins {
pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */
<STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
<STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
<STM32_PINMUX('A', 9, AF13)>,/* DCMI_D0 */
<STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
<STM32_PINMUX('E', 0, AF13)>,/* DCMI_D2 */
<STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */
<STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */
<STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */
<STM32_PINMUX('I', 6, AF13)>,/* DCMI_D6 */
<STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */
<STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
<STM32_PINMUX('H', 7, AF13)>;/* DCMI_D9 */
bias-pull-up;
};
};
dcmi_sleep_pins_c: dcmi-sleep-2 {
pins {
pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */
<STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
<STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
<STM32_PINMUX('A', 9, ANALOG)>,/* DCMI_D0 */
<STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
<STM32_PINMUX('E', 0, ANALOG)>,/* DCMI_D2 */
<STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */
<STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */
<STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */
<STM32_PINMUX('I', 6, ANALOG)>,/* DCMI_D6 */
<STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */
<STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */
<STM32_PINMUX('H', 7, ANALOG)>;/* DCMI_D9 */
};
};
ethernet0_rgmii_pins_a: rgmii-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
@ -923,6 +960,21 @@
};
};
mco1_pins_a: mco1-0 {
pins {
pinmux = <STM32_PINMUX('A', 13, AF2)>; /* MCO1 */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
};
mco1_sleep_pins_a: mco1-sleep-0 {
pins {
pinmux = <STM32_PINMUX('A', 13, ANALOG)>; /* MCO1 */
};
};
mco2_pins_a: mco2-0 {
pins {
pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */
@ -1814,30 +1866,30 @@
spi2_pins_a: spi2-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI1_SCK */
<STM32_PINMUX('I', 3, AF5)>; /* SPI1_MOSI */
pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */
<STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI1_MISO */
pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */
bias-disable;
};
};
spi2_pins_b: spi2-1 {
pins1 {
pinmux = <STM32_PINMUX('I', 1, AF5)>, /* SPI1_SCK */
<STM32_PINMUX('I', 3, AF5)>; /* SPI1_MOSI */
pinmux = <STM32_PINMUX('I', 1, AF5)>, /* SPI2_SCK */
<STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI1_MISO */
pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */
bias-disable;
};
};

14
arch/arm/dts/stm32mp15-u-boot.dtsi
View file

@ -53,20 +53,6 @@
reg = <0x5a003000 0x550
0x5a004000 0x234>;
clocks = <&rcc AXIDCG>,
<&rcc DDRC1>,
<&rcc DDRC2>,
<&rcc DDRPHYC>,
<&rcc DDRCAPB>,
<&rcc DDRPHYCAPB>;
clock-names = "axidcg",
"ddrc1",
"ddrc2",
"ddrphyc",
"ddrcapb",
"ddrphycapb";
status = "okay";
};
};

7
arch/arm/dts/stm32mp151.dtsi
View file

@ -1143,10 +1143,9 @@
reg = <0x4c001000 0x400>;
st,proc-id = <0>;
interrupts-extended =
<&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<&exti 61 1>;
interrupt-names = "rx", "tx", "wakeup";
<&exti 61 1>,
<&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "rx", "tx";
clocks = <&rcc IPCC>;
wakeup-source;
status = "disabled";

1
arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
View file

@ -5,7 +5,6 @@
#include <dt-bindings/clock/stm32mp1-clksrc.h>
#include "stm32mp15-scmi-u-boot.dtsi"
#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
/ {
aliases {

1
arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi
View file

@ -5,7 +5,6 @@
#include <dt-bindings/clock/stm32mp1-clksrc.h>
#include "stm32mp15-scmi-u-boot.dtsi"
#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
/ {
aliases {

8
arch/arm/dts/stm32mp15xx-dkx.dtsi
View file

@ -685,6 +685,14 @@
&usbh_ehci {
phys = <&usbphyc_port0>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
/* onboard HUB */
hub@1 {
compatible = "usb424,2514";
reg = <1>;
vdd-supply = <&v3v3>;
};
};
&usbotg_hs {

4
arch/arm/dts/total_compute.dts
View file

@ -45,4 +45,8 @@
clock-frequency = <24000000>;
clock-output-names = "bp:clock24mhz";
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
};

67
arch/arm/dts/versal-net-mini.dts Normal file
View file

@ -0,0 +1,67 @@
// SPDX-License-Identifier: GPL-2.0
/*
* dts file for Xilinx Versal NET
*
* Copyright (C) 2021 - 2022, Xilinx, Inc.
* Copyright (C) 2022, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "xlnx,versal-net-mini";
model = "Xilinx Versal NET MINI";
#address-cells = <2>;
#size-cells = <2>;
memory: memory@0 {
reg = <0 0xBBF00000 0 0x100000>, <0 0 0 0x80000000>;
device_type = "memory";
};
aliases {
/* serial0 = &serial0; */
serial0 = &dcc;
};
chosen {
stdout-path = "serial0:115200";
};
clk1: clk1 {
u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000>;
};
dcc: dcc {
compatible = "arm,dcc";
status = "okay";
u-boot,dm-pre-reloc;
};
amba: axi {
compatible = "simple-bus";
u-boot,dm-pre-reloc;
#address-cells = <2>;
#size-cells = <2>;
ranges;
serial0: serial@f1920000 {
u-boot,dm-pre-reloc;
compatible = "arm,pl011", "arm,primecell";
reg = <0 0xf1920000 0 0x1000>;
reg-io-width = <4>;
clock-names = "uartclk", "apb_pclk";
clocks = <&clk1>, <&clk1>;
clock = <1000000>;
current-speed = <115200>;
skip-init;
};
};
};

11
arch/arm/dts/xilinx-versal-net-virt.dts Normal file
View file

@ -0,0 +1,11 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Empty device tree for versal-net-virt board
*
* Copyright (C) 2022, Advanced Micro Devices, Inc.
*/
/dts-v1/;
/ {
};

26
arch/arm/dts/zynq-7000.dtsi
View file

@ -192,6 +192,17 @@
reg = <0xf8006000 0x1000>;
};
ocm: sram@fffc0000 {
compatible = "mmio-sram";
reg = <0xfffc0000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xfffc0000 0x10000>;
ocm-sram@0 {
reg = <0x0 0x10000>;
};
};
uart0: serial@e0000000 {
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
status = "disabled";
@ -235,19 +246,19 @@
};
qspi: spi@e000d000 {
clock-names = "ref_clk", "pclk";
clocks = <&clkc 10>, <&clkc 43>;
compatible = "xlnx,zynq-qspi-1.0";
status = "disabled";
reg = <0xe000d000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <0 19 4>;
reg = <0xe000d000 0x1000>;
clocks = <&clkc 10>, <&clkc 43>;
clock-names = "ref_clk", "pclk";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
gem0: ethernet@e000b000 {
compatible = "cdns,zynq-gem", "cdns,gem";
compatible = "xlnx,zynq-gem", "cdns,zynq-gem", "cdns,gem";
reg = <0xe000b000 0x1000>;
status = "disabled";
interrupts = <0 22 4>;
@ -258,7 +269,7 @@
};
gem1: ethernet@e000c000 {
compatible = "cdns,zynq-gem", "cdns,gem";
compatible = "xlnx,zynq-gem", "cdns,zynq-gem", "cdns,gem";
reg = <0xe000c000 0x1000>;
status = "disabled";
interrupts = <0 45 4>;
@ -378,9 +389,9 @@
devcfg: devcfg@f8007000 {
compatible = "xlnx,zynq-devcfg-1.0";
reg = <0xf8007000 0x100>;
interrupt-parent = <&intc>;
interrupts = <0 8 4>;
reg = <0xf8007000 0x100>;
clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
syscon = <&slcr>;
@ -416,6 +427,7 @@
};
scutimer: timer@f8f00600 {
u-boot,dm-pre-reloc;
interrupt-parent = <&intc>;
interrupts = <1 13 0x301>;
compatible = "arm,cortex-a9-twd-timer";

13
arch/arm/dts/zynq-zc702.dts
View file

@ -64,19 +64,6 @@
};
};
&amba {
ocm: sram@fffc0000 {
compatible = "mmio-sram";
reg = <0xfffc0000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xfffc0000 0x10000>;
ocm-sram@0 {
reg = <0x0 0x10000>;
};
};
};
&can0 {
status = "okay";
pinctrl-names = "default";

8
arch/arm/dts/zynqmp-clk-ccf.dtsi
View file

@ -260,11 +260,19 @@
assigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
};
&dwc3_0 {
clocks = <&zynqmp_clk USB3_DUAL_REF>;
};
&usb1 {
clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
assigned-clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
};
&dwc3_1 {
clocks = <&zynqmp_clk USB3_DUAL_REF>;
};
&watchdog0 {
clocks = <&zynqmp_clk WDT>;
};

20
arch/arm/dts/zynqmp-e-a2197-00-revA.dts
View file

@ -155,8 +155,12 @@
phy-handle = <&phy0>;
phy-mode = "sgmii";
is-internal-pcspma;
phy0: ethernet-phy@0 { /* u131 M88E1512 */
reg = <0>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 { /* u131 M88E1512 */
reg = <0>;
};
};
};
@ -203,6 +207,18 @@
&i2c0 { /* MIO 34-35 - can't stay here */
status = "okay";
clock-frequency = <400000>;
tca6416_u233: gpio@20 { /* u233 */
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller; /* interrupt not connected */
#gpio-cells = <2>;
gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "", "", /* 0 - 3 */
"PMBUS2_INA226_ALERT", "", "", "MAX6643_FULLSPD", /* 4 - 7 */
"FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 10 - 13 */
"VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
};
i2c-mux@74 { /* u33 */
compatible = "nxp,pca9548";
#address-cells = <1>;

10
arch/arm/dts/zynqmp-sm-k26-revA.dts
View file

@ -214,13 +214,17 @@
};
partition@2240000 {
label = "SHA256";
reg = <0x2240000 0x10000>; /* 256B but 64KB sector */
reg = <0x2240000 0x40000>; /* 256B but 256KB sector */
read-only;
lock;
};
partition@2250000 {
partition@2280000 {
label = "Secure OS Storage";
reg = <0x2280000 0x20000>; /* 128KB */
};
partition@22A0000 {
label = "User";
reg = <0x2250000 0x1db0000>; /* 29.5 MB */
reg = <0x22A0000 0x1db0000>; /* 29.5 MB */
};
};
};

20
arch/arm/dts/zynqmp-zcu102-revA.dts
View file

@ -200,13 +200,19 @@
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
phy0: ethernet-phy@21 {
reg = <21>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
ti,dp83867-rxctrl-strap-quirk;
/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@21 {
#phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <21>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
ti,dp83867-rxctrl-strap-quirk;
reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
};
};
};

19
arch/arm/dts/zynqmp-zcu104-revA.dts
View file

@ -109,12 +109,19 @@
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
phy0: ethernet-phy@c {
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
ti,dp83867-rxctrl-strap-quirk;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@c {
#phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
ti,dp83867-rxctrl-strap-quirk;
reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
};
};
};

19
arch/arm/dts/zynqmp-zcu104-revC.dts
View file

@ -114,12 +114,19 @@
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
phy0: ethernet-phy@c {
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
ti,dp83867-rxctrl-strap-quirk;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@c {
#phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
ti,dp83867-rxctrl-strap-quirk;
reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
};
};
};

19
arch/arm/dts/zynqmp-zcu111-revA.dts
View file

@ -172,12 +172,19 @@
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
phy0: ethernet-phy@c {
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
ti,dp83867-rxctrl-strap-quirk;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@c {
#phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
ti,dp83867-rxctrl-strap-quirk;
reset-gpios = <&tca6416_u22 6 GPIO_ACTIVE_LOW>;
};
};
};

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