Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-09-20 14:41:58 +00:00
Code Issues Projects Releases Packages Wiki Activity

arm: dts: stm32mp15: alignment with v5.18

Browse source 
Device tree alignment with Linux kernel v5.18-rc2:
- ARM: dts: stm32: Add support for the emtrion emSBC-Argon
  (only the pincontrol part)
- ARM: dts: stm32: Drop duplicate status okay from DHCOM gpioc node
- ARM: dts: stm32: add st,stm32-sdmmc2 compatible on stm32mp151
- ARM: dts: stm32: fix AV96 board SAI2 pin muxing on stm32mp15
- ARM: dts: stm32: use exti 19 as main interrupt to support RTC wakeup on
  stm32mp157
- ARM: dts: stm32: add DMA configuration to UART nodes on stm32mp151
- ARM: dts: stm32: keep uart4 behavior on *
- ARM: dts: stm32: Correct masks for GIC PPI interrupts on stm32mp15

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
This commit is contained in:
Patrick Delaunay 2022-04-26 15:38:05 +02:00 committed by Patrice Chotard
parent 655af9aa9c
commit 189ec2fee6
16 changed files with 168 additions and 21 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

92
arch/arm/dts/stm32mp15-pinctrl.dtsi
View file

@ -338,6 +338,47 @@
};
};
ethernet0_rmii_pins_b: rmii-1 {
pins1 {
pinmux = <STM32_PINMUX('B', 5, AF0)>, /* ETH1_CLK */
<STM32_PINMUX('C', 1, AF11)>, /* ETH1_MDC */
<STM32_PINMUX('G', 13, AF11)>, /* ETH1_TXD0 */
<STM32_PINMUX('G', 14, AF11)>; /* ETH1_TXD1 */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH1_MDIO */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins3 {
pinmux = <STM32_PINMUX('A', 7, AF11)>, /* ETH1_CRS_DV */
<STM32_PINMUX('C', 4, AF11)>, /* ETH1_RXD0 */
<STM32_PINMUX('C', 5, AF11)>; /* ETH1_RXD1 */
bias-disable;
};
pins4 {
pinmux = <STM32_PINMUX('B', 11, AF11)>; /* ETH1_TX_EN */
};
};
ethernet0_rmii_sleep_pins_b: rmii-sleep-1 {
pins1 {
pinmux = <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
<STM32_PINMUX('A', 7, ANALOG)>, /* ETH1_CRS_DV */
<STM32_PINMUX('B', 5, ANALOG)>, /* ETH1_CLK */
<STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_TX_EN */
<STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
<STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RXD0 */
<STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RXD1 */
<STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_TXD0 */
<STM32_PINMUX('G', 14, ANALOG)>; /* ETH1_TXD1 */
};
};
fmc_pins_a: fmc-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
@ -927,6 +968,21 @@
};
};
pwm1_pins_b: pwm1-1 {
pins {
pinmux = <STM32_PINMUX('E', 9, AF1)>; /* TIM1_CH1 */
bias-pull-down;
drive-push-pull;
slew-rate = <0>;
};
};
pwm1_sleep_pins_b: pwm1-sleep-1 {
pins {
pinmux = <STM32_PINMUX('E', 9, ANALOG)>; /* TIM1_CH1 */
};
};
pwm2_pins_a: pwm2-0 {
pins {
pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
@ -2042,6 +2098,42 @@
};
};
usart3_pins_d: usart3-3 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
<STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('D', 9, AF7)>, /* USART3_RX */
<STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */
bias-disable;
};
};
usart3_idle_pins_d: usart3-idle-3 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
<STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
<STM32_PINMUX('D', 11, ANALOG)>; /* USART3_CTS_NSS */
};
pins2 {
pinmux = <STM32_PINMUX('D', 9, AF7)>; /* USART3_RX */
bias-disable;
};
};
usart3_sleep_pins_d: usart3-sleep-3 {
pins {
pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
<STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
<STM32_PINMUX('D', 11, ANALOG)>, /* USART3_CTS_NSS */
<STM32_PINMUX('D', 9, ANALOG)>; /* USART3_RX */
};
};
usbotg_hs_pins_a: usbotg-hs-0 {
pins {
pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */

12
arch/arm/dts/stm32mp15-u-boot.dtsi
View file

@ -188,18 +188,6 @@
#size-cells = <0>;
};
&sdmmc1 {
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
};
&sdmmc2 {
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
};
&sdmmc3 {
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
};
&usart1 {
resets = <&rcc USART1_R>;
};

37
arch/arm/dts/stm32mp151.dtsi
View file

@ -63,10 +63,10 @@
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-parent = <&intc>;
};
@ -473,6 +473,9 @@
interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART2_K>;
wakeup-source;
dmas = <&dmamux1 43 0x400 0x15>,
<&dmamux1 44 0x400 0x11>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -482,6 +485,9 @@
interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART3_K>;
wakeup-source;
dmas = <&dmamux1 45 0x400 0x15>,
<&dmamux1 46 0x400 0x11>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -491,6 +497,9 @@
interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART4_K>;
wakeup-source;
dmas = <&dmamux1 63 0x400 0x15>,
<&dmamux1 64 0x400 0x11>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -500,6 +509,9 @@
interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART5_K>;
wakeup-source;
dmas = <&dmamux1 65 0x400 0x15>,
<&dmamux1 66 0x400 0x11>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -606,6 +618,9 @@
interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART7_K>;
wakeup-source;
dmas = <&dmamux1 79 0x400 0x15>,
<&dmamux1 80 0x400 0x11>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -615,6 +630,9 @@
interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART8_K>;
wakeup-source;
dmas = <&dmamux1 81 0x400 0x15>,
<&dmamux1 82 0x400 0x11>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -696,6 +714,9 @@
interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART6_K>;
wakeup-source;
dmas = <&dmamux1 71 0x400 0x15>,
<&dmamux1 72 0x400 0x11>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -1077,7 +1098,7 @@
};
sdmmc3: mmc@48004000 {
compatible = "arm,pl18x", "arm,primecell";
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00253180>;
reg = <0x48004000 0x400>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
@ -1411,7 +1432,7 @@
};
sdmmc1: mmc@58005000 {
compatible = "arm,pl18x", "arm,primecell";
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00253180>;
reg = <0x58005000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
@ -1426,7 +1447,7 @@
};
sdmmc2: mmc@58007000 {
compatible = "arm,pl18x", "arm,primecell";
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00253180>;
reg = <0x58007000 0x1000>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
@ -1590,7 +1611,7 @@
reg = <0x5c004000 0x400>;
clocks = <&rcc RTCAPB>, <&rcc RTC>;
clock-names = "pclk", "rtc_ck";
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};

7
arch/arm/dts/stm32mp153.dtsi
View file

@ -22,6 +22,13 @@
interrupt-affinity = <&cpu0>, <&cpu1>;
};
timer {
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
soc {
m_can1: can@4400e000 {
compatible = "bosch,m_can";

2
arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts
View file

@ -43,5 +43,7 @@
pinctrl-0 = <&uart4_pins_a>;
pinctrl-1 = <&uart4_sleep_pins_a>;
pinctrl-2 = <&uart4_idle_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};

2
arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts
View file

@ -43,5 +43,7 @@
pinctrl-0 = <&uart4_pins_a>;
pinctrl-1 = <&uart4_sleep_pins_a>;
pinctrl-2 = <&uart4_idle_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};

4
arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
View file

@ -143,6 +143,8 @@
pinctrl-0 = <&uart4_pins_a>;
pinctrl-1 = <&uart4_sleep_pins_a>;
pinctrl-2 = <&uart4_idle_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
@ -150,5 +152,7 @@
&uart8 {
pinctrl-names = "default";
pinctrl-0 = <&uart8_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};

4
arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts
View file

@ -44,6 +44,8 @@
pinctrl-0 = <&uart4_pins_a>;
pinctrl-1 = <&uart4_sleep_pins_a>;
pinctrl-2 = <&uart4_idle_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
@ -51,5 +53,7 @@
&uart8 {
pinctrl-names = "default";
pinctrl-0 = <&uart8_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};

2
arch/arm/dts/stm32mp157c-ed1.dts
View file

@ -392,6 +392,8 @@
pinctrl-0 = <&uart4_pins_a>;
pinctrl-1 = <&uart4_sleep_pins_a>;
pinctrl-2 = <&uart4_idle_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};

2
arch/arm/dts/stm32mp157c-odyssey.dts
View file

@ -132,6 +132,8 @@
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};

4
arch/arm/dts/stm32mp15xx-dhcom-drc02.dtsi
View file

@ -131,6 +131,8 @@
&usart3 {
pinctrl-names = "default";
pinctrl-0 = <&usart3_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
@ -144,6 +146,8 @@
pinctrl-names = "default";
pinctrl-0 = <&uart8_pins_a>;
rts-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};

4
arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtsi
View file

@ -287,6 +287,8 @@
&usart3 {
pinctrl-names = "default";
pinctrl-0 = <&usart3_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
@ -294,6 +296,8 @@
pinctrl-names = "default";
pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>;
uart-has-rtscts;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};

4
arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtsi
View file

@ -105,12 +105,16 @@
&usart3 {
pinctrl-names = "default";
pinctrl-0 = <&usart3_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
&uart8 {
pinctrl-names = "default";
pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};

3
arch/arm/dts/stm32mp15xx-dhcom-som.dtsi
View file

@ -196,7 +196,6 @@
"", "", "DHCOM-E", "",
"", "", "", "",
"", "", "", "";
status = "okay";
};
&gpiod {
@ -521,5 +520,7 @@
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};

6
arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtsi
View file

@ -376,6 +376,8 @@
label = "LS-UART1";
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins_b>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
@ -385,6 +387,8 @@
pinctrl-names = "default";
pinctrl-0 = <&uart7_pins_a>;
uart-has-rtscts;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
@ -394,6 +398,8 @@
pinctrl-0 = <&usart2_pins_a>;
pinctrl-1 = <&usart2_sleep_pins_a>;
st,hw-flow-ctrl;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
bluetooth {

4
arch/arm/dts/stm32mp15xx-dkx.dtsi
View file

@ -658,6 +658,8 @@
pinctrl-0 = <&uart4_pins_a>;
pinctrl-1 = <&uart4_sleep_pins_a>;
pinctrl-2 = <&uart4_idle_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
@ -666,6 +668,8 @@
pinctrl-0 = <&uart7_pins_c>;
pinctrl-1 = <&uart7_sleep_pins_c>;
pinctrl-2 = <&uart7_idle_pins_c>;
/delete-property/dmas;
/delete-property/dma-names;
status = "disabled";
};