arm: nuvoton: Add support for Nuvoton NPCM845 BMC

Add basic support for the Nuvoton NPCM845 EVB (Arbel).

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
This commit is contained in:
Jim Liu 2022-09-27 16:45:15 +08:00 committed by Tom Rini
parent d0fc818259
commit 9ca71c9c19
21 changed files with 1112 additions and 0 deletions

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@ -1252,6 +1252,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt8518-ap1-emmc.dtb
dtb-$(CONFIG_ARCH_NPCM7xx) += nuvoton-npcm750-evb.dtb
dtb-$(CONFIG_ARCH_NPCM8XX) += nuvoton-npcm845-evb.dtb
dtb-$(CONFIG_XEN) += xenguest-arm64.dtb
dtb-$(CONFIG_ARCH_OCTEONTX) += octeontx.dtb

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@ -0,0 +1,170 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com
#include <dt-bindings/clock/nuvoton,npcm845-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges;
gcr: system-controller@f0800000 {
compatible = "nuvoton,npcm845-gcr", "syscon";
reg = <0x0 0xf0800000 0x0 0x1000>;
};
gic: interrupt-controller@dfff9000 {
compatible = "arm,gic-400";
reg = <0x0 0xdfff9000 0x0 0x1000>,
<0x0 0xdfffa000 0x0 0x2000>,
<0x0 0xdfffc000 0x0 0x2000>,
<0x0 0xdfffe000 0x0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
#interrupt-cells = <3>;
interrupt-controller;
#address-cells = <0>;
ppi-partitions {
ppi_cluster0: interrupt-partition-0 {
affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
};
};
};
};
ahb {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges;
rstc: reset-controller@f0801000 {
compatible = "nuvoton,npcm845-reset";
reg = <0x0 0xf0801000 0x0 0x78>;
#reset-cells = <2>;
nuvoton,sysgcr = <&gcr>;
};
clk: clock-controller@f0801000 {
compatible = "nuvoton,npcm845-clk";
#clock-cells = <1>;
reg = <0x0 0xf0801000 0x0 0x1000>;
};
apb {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges = <0x0 0x0 0xf0000000 0x00300000>,
<0xfff00000 0x0 0xfff00000 0x00016000>;
timer0: timer@8000 {
compatible = "nuvoton,npcm845-timer";
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x8000 0x1C>;
clocks = <&clk NPCM8XX_CLK_REFCLK>;
clock-names = "refclk";
};
serial0: serial@0 {
compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
reg = <0x0 0x1000>;
clocks = <&clk NPCM8XX_CLK_UART>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
status = "disabled";
};
serial1: serial@1000 {
compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
reg = <0x1000 0x1000>;
clocks = <&clk NPCM8XX_CLK_UART>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
status = "disabled";
};
serial2: serial@2000 {
compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
reg = <0x2000 0x1000>;
clocks = <&clk NPCM8XX_CLK_UART>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
status = "disabled";
};
serial3: serial@3000 {
compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
reg = <0x3000 0x1000>;
clocks = <&clk NPCM8XX_CLK_UART>;
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
status = "disabled";
};
serial4: serial@4000 {
compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
reg = <0x4000 0x1000>;
clocks = <&clk NPCM8XX_CLK_UART>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
status = "disabled";
};
serial5: serial@5000 {
compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
reg = <0x5000 0x1000>;
clocks = <&clk NPCM8XX_CLK_UART>;
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
status = "disabled";
};
serial6: serial@6000 {
compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
reg = <0x6000 0x1000>;
clocks = <&clk NPCM8XX_CLK_UART>;
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
status = "disabled";
};
watchdog0: watchdog@801c {
compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x801c 0x4>;
status = "disabled";
clocks = <&clk NPCM8XX_CLK_REFCLK>;
syscon = <&gcr>;
};
watchdog1: watchdog@901c {
compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x901c 0x4>;
status = "disabled";
clocks = <&clk NPCM8XX_CLK_REFCLK>;
syscon = <&gcr>;
};
watchdog2: watchdog@a01c {
compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xa01c 0x4>;
status = "disabled";
clocks = <&clk NPCM8XX_CLK_REFCLK>;
syscon = <&gcr>;
};
};
};
};

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@ -0,0 +1,30 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com
/dts-v1/;
#include "nuvoton-npcm845.dtsi"
/ {
model = "Nuvoton npcm845 Development Board (Device Tree)";
compatible = "nuvoton,npcm845-evb", "nuvoton,npcm845";
aliases {
serial0 = &serial0;
};
chosen {
stdout-path = &serial0;
};
memory {
reg = <0x0 0x0 0x0 0x40000000>;
};
};
&serial0 {
status = "okay";
};
&watchdog1 {
status = "okay";
};

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@ -0,0 +1,77 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com
#include "nuvoton-common-npcm8xx.dtsi"
#include "nuvoton-npcm8xx-u-boot.dtsi"
/ {
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a35";
clocks = <&clk NPCM8XX_CLK_CPU>;
reg = <0x0 0x0>;
next-level-cache = <&l2>;
enable-method = "psci";
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a35";
clocks = <&clk NPCM8XX_CLK_CPU>;
reg = <0x0 0x1>;
next-level-cache = <&l2>;
enable-method = "psci";
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a35";
clocks = <&clk NPCM8XX_CLK_CPU>;
reg = <0x0 0x2>;
next-level-cache = <&l2>;
enable-method = "psci";
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a35";
clocks = <&clk NPCM8XX_CLK_CPU>;
reg = <0x0 0x3>;
next-level-cache = <&l2>;
enable-method = "psci";
};
l2: l2-cache {
compatible = "cache";
};
};
arm-pmu {
compatible = "arm,cortex-a35-pmu";
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
};

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@ -0,0 +1,136 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/reset/nuvoton,npcm8xx-reset.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
/* external reference clock */
clk_refclk: clk-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
clock-output-names = "refclk";
};
ahb {
rstc: reset-controller@f0801000 {
compatible = "nuvoton,npcm845-reset", "syscon",
"simple-mfd";
reg = <0x0 0xf0801000 0x0 0xC4>;
rstc1: reset-controller1 {
compatible = "syscon-reset";
#reset-cells = <1>;
regmap = <&rstc>;
offset = <NPCM8XX_RESET_IPSRST1>;
mask = <0xFFFFFFFF>;
};
rstc2: reset-controller2 {
compatible = "syscon-reset";
#reset-cells = <1>;
regmap = <&rstc>;
offset = <NPCM8XX_RESET_IPSRST2>;
mask = <0xFFFFFFFF>;
};
rstc3: reset-controller3 {
compatible = "syscon-reset";
#reset-cells = <1>;
regmap = <&rstc>;
offset = <NPCM8XX_RESET_IPSRST3>;
mask = <0xFFFFFFFF>;
};
rstc4: reset-controller4 {
compatible = "syscon-reset";
#reset-cells = <1>;
regmap = <&rstc>;
offset = <NPCM8XX_RESET_IPSRST4>;
mask = <0xFFFFFFFF>;
};
};
clk: clock-controller@f0801000 {
compatible = "nuvoton,npcm845-clk", "syscon";
#clock-cells = <1>;
clock-controller;
reg = <0x0 0xf0801000 0x0 0x1000>;
clock-names = "refclk";
clocks = <&clk_refclk>;
};
apb {
serial0: serial@0 {
compatible = "nuvoton,npcm845-uart";
reg = <0x0 0x1000>;
clocks = <&clk NPCM8XX_CLK_UART>, <&clk NPCM8XX_CLK_PLL2DIV2>;
clock-frequency = <24000000>;
status = "disabled";
};
gpio0: gpio0@10000 {
compatible = "nuvoton,npcm-gpio";
reg = <0x10000 0xB0>;
#gpio-cells = <2>;
gpio-controller;
gpio-bank-name = "gpio0";
};
gpio1: gpio1@11000 {
compatible = "nuvoton,npcm-gpio";
reg = <0x11000 0xB0>;
#gpio-cells = <2>;
gpio-controller;
gpio-bank-name = "gpio1";
};
gpio2: gpio2@12000 {
compatible = "nuvoton,npcm-gpio";
reg = <0x12000 0xB0>;
#gpio-cells = <2>;
gpio-controller;
gpio-bank-name = "gpio2";
};
gpio3: gpio3@13000 {
compatible = "nuvoton,npcm-gpio";
reg = <0x13000 0xB0>;
#gpio-cells = <2>;
gpio-controller;
gpio-bank-name = "gpio3";
};
gpio4: gpio4@14000 {
compatible = "nuvoton,npcm-gpio";
reg = <0x14000 0xB0>;
#gpio-cells = <2>;
gpio-controller;
gpio-bank-name = "gpio4";
};
gpio5: gpio5@15000 {
compatible = "nuvoton,npcm-gpio";
reg = <0x15000 0xB0>;
#gpio-cells = <2>;
gpio-controller;
gpio-bank-name = "gpio5";
};
gpio6: gpio6@16000 {
compatible = "nuvoton,npcm-gpio";
reg = <0x16000 0xB0>;
#gpio-cells = <2>;
gpio-controller;
gpio-bank-name = "gpio6";
};
gpio7: gpio7@17000 {
compatible = "nuvoton,npcm-gpio";
reg = <0x17000 0xB0>;
#gpio-cells = <2>;
gpio-controller;
gpio-bank-name = "gpio7";
};
};
};
};

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@ -0,0 +1,140 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* System Global Control Register definitions
* Copyright (c) 2022 Nuvoton Technology Corp.
*/
#ifndef _NPCM_GCR_H_
#define _NPCM_GCR_H_
#define NPCM_GCR_BA 0xF0800000
/* On-Chip ARBEL NPCM8XX VERSIONS */
#define ARBEL_Z1 0x00A35850
#define ARBEL_A1 0x04a35850
#define ARBEL_NPCM845 0x00000000
#define ARBEL_NPCM830 0x00300395
#define ARBEL_NPCM810 0x00000220
#define MFSEL4_ESPISEL BIT(8)
#define MFSEL1_LPCSEL BIT(26)
#define INTCR2_WDC BIT(21)
struct npcm_gcr {
unsigned int pdid;
unsigned int pwron;
unsigned int swstrps;
unsigned int rsvd1[2];
unsigned int miscpe;
unsigned int spldcnt;
unsigned int rsvd2[1];
unsigned int flockr2;
unsigned int flockr3;
unsigned int rsvd3[3];
unsigned int a35_mode;
unsigned int spswc;
unsigned int intcr;
unsigned int intsr;
unsigned int obscr1;
unsigned int obsdr1;
unsigned int rsvd4[1];
unsigned int hifcr;
unsigned int rsvd5[3];
unsigned int intcr2;
unsigned int rsvd6[1];
unsigned int srcnt;
unsigned int ressr;
unsigned int rlockr1;
unsigned int flockr1;
unsigned int dscnt;
unsigned int mdlr;
unsigned int scrpad_c;
unsigned int scrpad_b;
unsigned int rsvd7[4];
unsigned int daclvlr;
unsigned int intcr3;
unsigned int pcirctl;
unsigned int rsvd8[2];
unsigned int vsintr;
unsigned int rsvd9[1];
unsigned int sd2sur1;
unsigned int sd2sur2;
unsigned int sd2irv3;
unsigned int intcr4;
unsigned int obscr2;
unsigned int obsdr2;
unsigned int rsvd10[5];
unsigned int i2csegsel;
unsigned int i2csegctl;
unsigned int vsrcr;
unsigned int mlockr;
unsigned int rsvd11[8];
unsigned int etsr;
unsigned int dft1r;
unsigned int dft2r;
unsigned int dft3r;
unsigned int edffsr;
unsigned int rsvd12[1];
unsigned int intcrpce3;
unsigned int intcrpce2;
unsigned int intcrpce0;
unsigned int intcrpce1;
unsigned int dactest;
unsigned int scrpad;
unsigned int usb1phyctl;
unsigned int usb2phyctl;
unsigned int usb3phyctl;
unsigned int intsr2;
unsigned int intcrpce2b;
unsigned int intcrpce0b;
unsigned int intcrpce1b;
unsigned int intcrpce3b;
unsigned int rsvd13[4];
unsigned int intcrpce2c;
unsigned int intcrpce0c;
unsigned int intcrpce1c;
unsigned int intcrpce3c;
unsigned int rsvd14[40];
unsigned int sd2irv4;
unsigned int sd2irv5;
unsigned int sd2irv6;
unsigned int sd2irv7;
unsigned int sd2irv8;
unsigned int sd2irv9;
unsigned int sd2irv10;
unsigned int sd2irv11;
unsigned int rsvd15[8];
unsigned int mfsel1;
unsigned int mfsel2;
unsigned int mfsel3;
unsigned int mfsel4;
unsigned int mfsel5;
unsigned int mfsel6;
unsigned int mfsel7;
unsigned int rsvd16[1];
unsigned int mfsel_lk1;
unsigned int mfsel_lk2;
unsigned int mfsel_lk3;
unsigned int mfsel_lk4;
unsigned int mfsel_lk5;
unsigned int mfsel_lk6;
unsigned int mfsel_lk7;
unsigned int rsvd17[1];
unsigned int mfsel_set1;
unsigned int mfsel_set2;
unsigned int mfsel_set3;
unsigned int mfsel_set4;
unsigned int mfsel_set5;
unsigned int mfsel_set6;
unsigned int mfsel_set7;
unsigned int rsvd18[1];
unsigned int mfsel_clr1;
unsigned int mfsel_clr2;
unsigned int mfsel_clr3;
unsigned int mfsel_clr4;
unsigned int mfsel_clr5;
unsigned int mfsel_clr6;
unsigned int mfsel_clr7;
};
#endif

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@ -0,0 +1,26 @@
/* SPDX-License-Identifier: GPL-2.0+ */
#ifndef _NPCM_RST_H_
#define _NPCM_RST_H_
/* Watchdog Timer Controller Register */
#define WTCR0_REG 0xF000801C
#define WTCR_WTR BIT(0)
#define WTCR_WTRE BIT(1)
#define WTCR_WTE BIT(7)
/* Reset status bits */
#define PORST BIT(31)
#define CORST BIT(30)
#define WD0RST BIT(29)
#define SW1RST BIT(28)
#define SW2RST BIT(27)
#define SW3RST BIT(26)
#define SW4RST BIT(25)
#define WD1RST BIT(24)
#define WD2RST BIT(23)
#define RST_STS_MASK GENMASK(31, 23)
int npcm_get_reset_status(void);
#endif

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@ -19,8 +19,16 @@ config ARCH_NPCM7xx
General support for NPCM7xx BMC (Poleg).
Nuvoton NPCM7xx BMC is based on the Cortex A9.
config ARCH_NPCM8XX
bool "Support Nuvoton NPCM8xx SoC"
select ARM64
help
General support for NPCM8xx BMC (Arbel).
Nuvoton NPCM8xx BMC is based on the Cortex A35.
endchoice
source "arch/arm/mach-npcm/npcm7xx/Kconfig"
source "arch/arm/mach-npcm/npcm8xx/Kconfig"
endif

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@ -1 +1,2 @@
obj-$(CONFIG_ARCH_NPCM7xx) += npcm7xx/
obj-$(CONFIG_ARCH_NPCM8XX) += npcm8xx/

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@ -0,0 +1,18 @@
if ARCH_NPCM8XX
config SYS_CPU
default "armv8"
config SYS_SOC
default "npcm8xx"
config TARGET_ARBEL_EVB
bool "Arbel Evaluation Board"
help
ARBEL_EVB is Nuvoton evaluation board for NPCM845 SoC,
supports general functions of Basebase Management Controller
(BMC).
source "board/nuvoton/arbel_evb/Kconfig"
endif

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@ -0,0 +1 @@
obj-y += cpu.o reset.o

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@ -0,0 +1,135 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2022 Nuvoton Technology Corp.
*/
#include <common.h>
#include <dm.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/arch/gcr.h>
#include <asm/armv8/mmu.h>
#define SYSCNT_CTRL_BASE_ADDR 0xF07FC000
#define SC_CNTCR_ENABLE BIT(0)
#define SC_CNTCR_HDBG BIT(1)
#define SC_CNTCR_FREQ0 BIT(8)
#define SC_CNTCR_FREQ1 BIT(9)
/* System Counter register map */
struct sctr_regs {
u32 cntcr;
u32 cntsr;
u32 cntcv1;
u32 cntcv2;
u32 resv1[4];
u32 cntfid0;
u32 cntfid1;
u32 cntfid2;
u32 resv2[1001];
u32 counterid[1];
};
DECLARE_GLOBAL_DATA_PTR;
int print_cpuinfo(void)
{
struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
unsigned int val;
unsigned long mpidr_val;
asm volatile("mrs %0, mpidr_el1" : "=r" (mpidr_val));
val = readl(&gcr->mdlr);
printf("CPU-%lu: ", mpidr_val & 0x3);
switch (val) {
case ARBEL_NPCM845:
printf("NPCM845 ");
break;
case ARBEL_NPCM830:
printf("NPCM830 ");
break;
case ARBEL_NPCM810:
printf("NPCM810 ");
break;
default:
printf("NPCM8XX ");
break;
}
val = readl(&gcr->pdid);
switch (val) {
case ARBEL_Z1:
printf("Z1 @ ");
break;
case ARBEL_A1:
printf("A1 @ ");
break;
default:
printf("Unknown\n");
break;
}
return 0;
}
int arch_cpu_init(void)
{
if (!IS_ENABLED(CONFIG_SYS_DCACHE_OFF)) {
/* Enable cache to speed up system running */
if (get_sctlr() & CR_M)
return 0;
icache_enable();
__asm_invalidate_dcache_all();
__asm_invalidate_tlb_all();
set_sctlr(get_sctlr() | CR_C);
}
return 0;
}
static struct mm_region npcm_mem_map[1 + CONFIG_NR_DRAM_BANKS + 1] = {
{
/* DRAM */
.phys = 0x0UL,
.virt = 0x0UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
},
{
.phys = 0x80000000UL,
.virt = 0x80000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
{
/* List terminator */
0,
}
};
struct mm_region *mem_map = npcm_mem_map;
int timer_init(void)
{
struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
u32 cntfrq_el0;
/* Enable system counter */
__asm__ __volatile__("mrs %0, CNTFRQ_EL0\n\t" : "=r" (cntfrq_el0) : : "memory");
writel(cntfrq_el0, &sctr->cntfid0);
clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
gd->arch.tbl = 0;
gd->arch.tbu = 0;
return 0;
}

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@ -0,0 +1,37 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2022 Nuvoton Technology Corp.
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/gcr.h>
#include <asm/arch/rst.h>
void reset_cpu(void)
{
/* Generate a watchdog0 reset */
writel(WTCR_WTR | WTCR_WTRE | WTCR_WTE, WTCR0_REG);
while (1)
;
}
void reset_misc(void)
{
struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
clrbits_le32(&gcr->intcr2, INTCR2_WDC);
}
int npcm_get_reset_status(void)
{
struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
u32 val;
val = readl(&gcr->ressr);
if (!val)
val = readl(&gcr->intcr2);
return val & RST_STS_MASK;
}

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@ -0,0 +1,18 @@
if TARGET_ARBEL_EVB
config SYS_BOARD
default "arbel_evb"
config SYS_VENDOR
default "nuvoton"
config SYS_CONFIG_NAME
default "arbel"
config SYS_MEM_TOP_HIDE
hex "Reserved TOP memory"
default 0xB000000
help
Reserve memory for ECC/GFX/VCD/ECE.
endif

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Arbel EVB
M: Stanley Chu <yschu@nuvoton.com>
M: Jim Liu <JJLIU0@nuvoton.com>
S: Maintained
F: board/nuvoton/arbel_evb/
F: include/configs/arbel.h
F: configs/arbel_evb_defconfig

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obj-y += arbel_evb.o

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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2022 Nuvoton Technology Corp.
*/
#include <common.h>
#include <dm.h>
#include <asm/io.h>
#include <asm/arch/gcr.h>
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
return 0;
}
int dram_init(void)
{
struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
/*
* Get dram size from bootblock.
* The value is stored in scrpad_02 register.
*/
gd->ram_size = readl(&gcr->scrpad_b);
return 0;
}

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CONFIG_ARM=y
CONFIG_ARCH_NPCM=y
CONFIG_SYS_MALLOC_LEN=0x240000
CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x1C0000
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="nuvoton-npcm845-evb"
CONFIG_SYS_PROMPT="U-Boot>"
# CONFIG_PSCI_RESET is not set
CONFIG_ARCH_NPCM8XX=y
CONFIG_TARGET_ARBEL_EVB=y
CONFIG_SYS_LOAD_ADDR=0x10000000
CONFIG_ENV_ADDR=0x801C0000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run common_bootargs; run romboot"
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_BOOTM_LEN=0x1400000
CONFIG_CMD_GPIO=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_UUID=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_NPCM_GPIO=y
# CONFIG_INPUT is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_PINCTRL_NPCM8XX=y
CONFIG_DM_RESET=y
CONFIG_RESET_SYSCON=y
CONFIG_DM_SERIAL=y
CONFIG_NPCM_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_NPCM_FIU_SPI=y
CONFIG_TIMER=y
CONFIG_NPCM_TIMER=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1
CONFIG_USB_STORAGE=y
# CONFIG_EFI_LOADER is not set

35
include/configs/arbel.h Normal file
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2022 Nuvoton Technology Corp.
*/
#ifndef __CONFIG_ARBEL_H
#define __CONFIG_ARBEL_H
#define CONFIG_SYS_SDRAM_BASE 0x0
#define CONFIG_SYS_BOOTMAPSZ (20 << 20)
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
/* Default environemnt variables */
#define CONFIG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80200000\0" \
"stdin=serial\0" \
"stdout=serial\0" \
"stderr=serial\0" \
"ethact=gmac1\0" \
"autostart=no\0" \
"ethaddr=00:00:F7:A0:00:FC\0" \
"eth1addr=00:00:F7:A0:00:FD\0" \
"eth2addr=00:00:F7:A0:00:FE\0" \
"eth3addr=00:00:F7:A0:00:FF\0" \
"serverip=192.168.0.1\0" \
"ipaddr=192.168.0.2\0" \
"romboot=echo Booting Kernel from flash at 0x${uimage_flash_addr}; " \
"echo Using bootargs: ${bootargs};bootm ${uimage_flash_addr}\0" \
"earlycon=uart8250,mmio32,0xf0000000\0" \
"console=ttyS0,115200n8\0" \
"common_bootargs=setenv bootargs earlycon=${earlycon} root=/dev/ram " \
"console=${console} ramdisk_size=48000\0" \
"\0"
#endif

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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2022 Nuvoton Technology Corp.
*
* Device Tree binding constants for NPCM8XX clock controller.
*/
#ifndef __DT_BINDINGS_CLOCK_NPCM8XX_H
#define __DT_BINDINGS_CLOCK_NPCM8XX_H
#define NPCM8XX_CLK_CPU 0
#define NPCM8XX_CLK_GFX_PIXEL 1
#define NPCM8XX_CLK_MC 2
#define NPCM8XX_CLK_ADC 3
#define NPCM8XX_CLK_AHB 4
#define NPCM8XX_CLK_TIMER 5
#define NPCM8XX_CLK_UART 6
#define NPCM8XX_CLK_UART2 7
#define NPCM8XX_CLK_MMC 8
#define NPCM8XX_CLK_SPI3 9
#define NPCM8XX_CLK_PCI 10
#define NPCM8XX_CLK_AXI 11
#define NPCM8XX_CLK_APB4 12
#define NPCM8XX_CLK_APB3 13
#define NPCM8XX_CLK_APB2 14
#define NPCM8XX_CLK_APB1 15
#define NPCM8XX_CLK_APB5 16
#define NPCM8XX_CLK_CLKOUT 17
#define NPCM8XX_CLK_GFX 18
#define NPCM8XX_CLK_SU 19
#define NPCM8XX_CLK_SU48 20
#define NPCM8XX_CLK_SDHC 21
#define NPCM8XX_CLK_SPI0 22
#define NPCM8XX_CLK_SPI1 23
#define NPCM8XX_CLK_SPIX 24
#define NPCM8XX_CLK_RG 25
#define NPCM8XX_CLK_RCP 26
#define NPCM8XX_CLK_PRE_ADC 27
#define NPCM8XX_CLK_ATB 28
#define NPCM8XX_CLK_PRE_CLK 29
#define NPCM8XX_CLK_TH 30
#define NPCM8XX_CLK_REFCLK 31
#define NPCM8XX_CLK_SYSBYPCK 32
#define NPCM8XX_CLK_MCBYPCK 33
#define NPCM8XX_CLK_PLL0 34
#define NPCM8XX_CLK_PLL1 35
#define NPCM8XX_CLK_PLL2 36
#define NPCM8XX_CLK_PLL2DIV2 37
#define NPCM8XX_NUM_CLOCKS (NPCM8XX_CLK_PLL2DIV2 + 1)
#endif

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/* SPDX-License-Identifier: GPL-2.0 */
// Copyright (c) 2020 Nuvoton Technology corporation.
#ifndef _DT_BINDINGS_NPCM8XX_RESET_H
#define _DT_BINDINGS_NPCM8XX_RESET_H
#define NPCM8XX_RESET_IPSRST1 0x20
#define NPCM8XX_RESET_IPSRST2 0x24
#define NPCM8XX_RESET_IPSRST3 0x34
#define NPCM8XX_RESET_IPSRST4 0x74
/* Reset lines on IP1 reset module (NPCM8XX_RESET_IPSRST1) */
#define NPCM8XX_RESET_GDMA0 3
#define NPCM8XX_RESET_UDC1 5
#define NPCM8XX_RESET_GMAC3 6
#define NPCM8XX_RESET_UART_2_3 7
#define NPCM8XX_RESET_UDC2 8
#define NPCM8XX_RESET_PECI 9
#define NPCM8XX_RESET_AES 10
#define NPCM8XX_RESET_UART_0_1 11
#define NPCM8XX_RESET_MC 12
#define NPCM8XX_RESET_SMB2 13
#define NPCM8XX_RESET_SMB3 14
#define NPCM8XX_RESET_SMB4 15
#define NPCM8XX_RESET_SMB5 16
#define NPCM8XX_RESET_PWM_M0 18
#define NPCM8XX_RESET_TIMER_0_4 19
#define NPCM8XX_RESET_TIMER_5_9 20
#define NPCM8XX_RESET_GMAC4 21
#define NPCM8XX_RESET_UDC4 22
#define NPCM8XX_RESET_UDC5 23
#define NPCM8XX_RESET_UDC6 24
#define NPCM8XX_RESET_UDC3 25
#define NPCM8XX_RESET_ADC 27
#define NPCM8XX_RESET_SMB6 28
#define NPCM8XX_RESET_SMB7 29
#define NPCM8XX_RESET_SMB0 30
#define NPCM8XX_RESET_SMB1 31
/* Reset lines on IP2 reset module (NPCM8XX_RESET_IPSRST2) */
#define NPCM8XX_RESET_MFT0 0
#define NPCM8XX_RESET_MFT1 1
#define NPCM8XX_RESET_MFT2 2
#define NPCM8XX_RESET_MFT3 3
#define NPCM8XX_RESET_MFT4 4
#define NPCM8XX_RESET_MFT5 5
#define NPCM8XX_RESET_MFT6 6
#define NPCM8XX_RESET_MFT7 7
#define NPCM8XX_RESET_MMC 8
#define NPCM8XX_RESET_GFX_SYS 10
#define NPCM8XX_RESET_AHB_PCIBRG 11
#define NPCM8XX_RESET_VDMA 12
#define NPCM8XX_RESET_ECE 13
#define NPCM8XX_RESET_VCD 14
#define NPCM8XX_RESET_VIRUART1 16
#define NPCM8XX_RESET_VIRUART2 17
#define NPCM8XX_RESET_SIOX1 18
#define NPCM8XX_RESET_SIOX2 19
#define NPCM8XX_RESET_BT 20
#define NPCM8XX_RESET_3DES 21
#define NPCM8XX_RESET_PSPI2 23
#define NPCM8XX_RESET_GMAC2 25
#define NPCM8XX_RESET_USBH1 26
#define NPCM8XX_RESET_GMAC1 28
#define NPCM8XX_RESET_CP1 31
/* Reset lines on IP3 reset module (NPCM8XX_RESET_IPSRST3) */
#define NPCM8XX_RESET_PWM_M1 0
#define NPCM8XX_RESET_SMB12 1
#define NPCM8XX_RESET_SPIX 2
#define NPCM8XX_RESET_SMB13 3
#define NPCM8XX_RESET_UDC0 4
#define NPCM8XX_RESET_UDC7 5
#define NPCM8XX_RESET_UDC8 6
#define NPCM8XX_RESET_UDC9 7
#define NPCM8XX_RESET_USBHUB 8
#define NPCM8XX_RESET_PCI_MAILBOX 9
#define NPCM8XX_RESET_GDMA1 10
#define NPCM8XX_RESET_GDMA2 11
#define NPCM8XX_RESET_SMB14 12
#define NPCM8XX_RESET_SHA 13
#define NPCM8XX_RESET_SEC_ECC 14
#define NPCM8XX_RESET_PCIE_RC 15
#define NPCM8XX_RESET_TIMER_10_14 16
#define NPCM8XX_RESET_RNG 17
#define NPCM8XX_RESET_SMB15 18
#define NPCM8XX_RESET_SMB8 19
#define NPCM8XX_RESET_SMB9 20
#define NPCM8XX_RESET_SMB10 21
#define NPCM8XX_RESET_SMB11 22
#define NPCM8XX_RESET_ESPI 23
#define NPCM8XX_RESET_USBPHY1 24
#define NPCM8XX_RESET_USBPHY2 25
/* Reset lines on IP4 reset module (NPCM8XX_RESET_IPSRST4) */
#define NPCM8XX_RESET_SMB16 0
#define NPCM8XX_RESET_SMB17 1
#define NPCM8XX_RESET_SMB18 2
#define NPCM8XX_RESET_SMB19 3
#define NPCM8XX_RESET_SMB20 4
#define NPCM8XX_RESET_SMB21 5
#define NPCM8XX_RESET_SMB22 6
#define NPCM8XX_RESET_SMB23 7
#define NPCM8XX_RESET_I3C0 8
#define NPCM8XX_RESET_I3C1 9
#define NPCM8XX_RESET_I3C2 10
#define NPCM8XX_RESET_I3C3 11
#define NPCM8XX_RESET_I3C4 12
#define NPCM8XX_RESET_I3C5 13
#define NPCM8XX_RESET_UART4 16
#define NPCM8XX_RESET_UART5 17
#define NPCM8XX_RESET_UART6 18
#define NPCM8XX_RESET_PCIMBX2 19
#define NPCM8XX_RESET_SMB24 22
#define NPCM8XX_RESET_SMB25 23
#define NPCM8XX_RESET_SMB26 24
#define NPCM8XX_RESET_USBPHY3 25
#define NPCM8XX_RESET_PCIRCPHY 27
#define NPCM8XX_RESET_PWM_M2 28
#define NPCM8XX_RESET_JTM1 29
#define NPCM8XX_RESET_JTM2 30
#define NPCM8XX_RESET_USBH2 31
#endif