mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-28 07:31:15 +00:00
arm: nuvoton: Add support for Nuvoton NPCM750 BMC
Add basic support for the Nuvoton NPCM750 EVB (Poleg). Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
This commit is contained in:
Jim Liu
Tom Rini
parent
1739a6db54
commit
84335544ea
22 changed files with 2291 additions and 0 deletions
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@ -1004,6 +1004,12 @@ config ARCH_NEXELL
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select DM
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select GPIO_EXTRA_HEADER
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config ARCH_NPCM
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bool "Support Nuvoton SoCs"
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select DM
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select OF_CONTROL
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imply CMD_DM
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config ARCH_APPLE
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bool "Apple SoCs"
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select ARM64
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@ -2279,6 +2285,8 @@ source "arch/arm/mach-imx/Kconfig"
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source "arch/arm/mach-nexell/Kconfig"
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source "arch/arm/mach-npcm/Kconfig"
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source "board/armltd/total_compute/Kconfig"
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source "board/bosch/shc/Kconfig"
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@ -72,6 +72,7 @@ machine-$(CONFIG_ARCH_MEDIATEK) += mediatek
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machine-$(CONFIG_ARCH_MESON) += meson
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machine-$(CONFIG_ARCH_MVEBU) += mvebu
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machine-$(CONFIG_ARCH_NEXELL) += nexell
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machine-$(CONFIG_ARCH_NPCM) += npcm
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machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2
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machine-$(CONFIG_ARCH_ORION5X) += orion5x
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machine-$(CONFIG_ARCH_OWL) += owl
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@ -1184,6 +1184,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
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mt8516-pumpkin.dtb \
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mt8518-ap1-emmc.dtb
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dtb-$(CONFIG_ARCH_NPCM7xx) += nuvoton-npcm750-evb.dtb
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dtb-$(CONFIG_XEN) += xenguest-arm64.dtb
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dtb-$(CONFIG_ARCH_OCTEONTX) += octeontx.dtb
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1120
arch/arm/dts/nuvoton-common-npcm7xx.dtsi
Normal file
1120
arch/arm/dts/nuvoton-common-npcm7xx.dtsi
Normal file
File diff suppressed because it is too large
Load diff
405
arch/arm/dts/nuvoton-npcm750-evb.dts
Normal file
405
arch/arm/dts/nuvoton-npcm750-evb.dts
Normal file
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@ -0,0 +1,405 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com
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// Copyright 2018 Google, Inc.
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/dts-v1/;
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#include "nuvoton-npcm750.dtsi"
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#include "dt-bindings/gpio/gpio.h"
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#include "nuvoton-npcm750-pincfg-evb.dtsi"
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/ {
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model = "Nuvoton npcm750 Development Board (Device Tree)";
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compatible = "nuvoton,npcm750-evb", "nuvoton,npcm750";
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aliases {
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ethernet2 = &gmac0;
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ethernet3 = &gmac1;
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serial0 = &serial0;
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serial1 = &serial1;
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serial2 = &serial2;
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serial3 = &serial3;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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i2c6 = &i2c6;
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i2c7 = &i2c7;
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i2c8 = &i2c8;
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i2c9 = &i2c9;
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i2c10 = &i2c10;
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i2c11 = &i2c11;
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i2c12 = &i2c12;
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i2c13 = &i2c13;
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i2c14 = &i2c14;
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i2c15 = &i2c15;
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spi0 = &spi0;
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spi1 = &spi1;
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fiu0 = &fiu0;
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fiu1 = &fiu3;
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fiu2 = &fiux;
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};
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chosen {
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stdout-path = &serial0;
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x20000000>;
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};
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};
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&gmac0 {
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phy-mode = "rgmii-id";
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status = "okay";
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};
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&gmac1 {
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phy-mode = "rgmii-id";
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status = "okay";
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};
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&ehci1 {
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status = "okay";
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};
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&fiu0 {
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status = "okay";
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spi-nor@0 {
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compatible = "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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spi-rx-bus-width = <2>;
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reg = <0>;
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spi-max-frequency = <5000000>;
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partitions@80000000 {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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bbuboot1@0 {
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label = "bb-uboot-1";
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reg = <0x0000000 0x80000>;
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read-only;
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};
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bbuboot2@80000 {
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label = "bb-uboot-2";
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reg = <0x0080000 0x80000>;
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read-only;
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};
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envparam@100000 {
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label = "env-param";
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reg = <0x0100000 0x40000>;
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read-only;
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};
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spare@140000 {
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label = "spare";
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reg = <0x0140000 0xC0000>;
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};
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kernel@200000 {
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label = "kernel";
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reg = <0x0200000 0x400000>;
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};
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rootfs@600000 {
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label = "rootfs";
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reg = <0x0600000 0x700000>;
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};
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spare1@d00000 {
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label = "spare1";
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reg = <0x0D00000 0x200000>;
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};
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spare2@f00000 {
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label = "spare2";
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reg = <0x0F00000 0x200000>;
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};
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spare3@1100000 {
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label = "spare3";
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reg = <0x1100000 0x200000>;
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};
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spare4@1300000 {
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label = "spare4";
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reg = <0x1300000 0x0>;
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};
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};
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};
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};
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&fiu3 {
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pinctrl-0 = <&spi3_pins>, <&spi3quad_pins>;
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status = "okay";
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spi-nor@0 {
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compatible = "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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spi-rx-bus-width = <2>;
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reg = <0>;
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spi-max-frequency = <5000000>;
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partitions@A0000000 {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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system1@0 {
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label = "spi3-system1";
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reg = <0x0 0x0>;
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};
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};
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};
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};
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&fiux {
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spix-mode;
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};
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&watchdog1 {
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status = "okay";
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};
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&rng {
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status = "okay";
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};
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&serial0 {
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status = "okay";
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clock-frequency = <24000000>;
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};
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&serial1 {
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status = "okay";
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};
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&serial2 {
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status = "okay";
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};
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&serial3 {
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status = "okay";
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};
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&adc {
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status = "okay";
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};
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&lpc_kcs {
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kcs1: kcs1@0 {
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status = "okay";
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};
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kcs2: kcs2@0 {
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status = "okay";
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};
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kcs3: kcs3@0 {
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status = "okay";
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};
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};
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/* lm75 on SVB */
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&i2c0 {
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clock-frequency = <100000>;
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status = "okay";
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lm75@48 {
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compatible = "lm75";
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reg = <0x48>;
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status = "okay";
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};
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};
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/* lm75 on EB */
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&i2c1 {
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clock-frequency = <100000>;
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status = "okay";
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lm75@48 {
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compatible = "lm75";
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reg = <0x48>;
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status = "okay";
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};
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};
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/* tmp100 on EB */
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&i2c2 {
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clock-frequency = <100000>;
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status = "okay";
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tmp100@48 {
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compatible = "tmp100";
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reg = <0x48>;
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status = "okay";
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};
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};
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&i2c3 {
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clock-frequency = <100000>;
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status = "okay";
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};
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&i2c5 {
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clock-frequency = <100000>;
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status = "okay";
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};
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/* tmp100 on SVB */
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&i2c6 {
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clock-frequency = <100000>;
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status = "okay";
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tmp100@48 {
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compatible = "tmp100";
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reg = <0x48>;
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status = "okay";
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};
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};
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&i2c7 {
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clock-frequency = <100000>;
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status = "okay";
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};
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&i2c8 {
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clock-frequency = <100000>;
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status = "okay";
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};
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&i2c9 {
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clock-frequency = <100000>;
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status = "okay";
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};
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&i2c10 {
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clock-frequency = <100000>;
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status = "okay";
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};
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&i2c11 {
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clock-frequency = <100000>;
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status = "okay";
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};
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&i2c14 {
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clock-frequency = <100000>;
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status = "okay";
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};
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&pwm_fan {
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status = "okay";
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fan@0 {
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reg = <0x00>;
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fan-tach-ch = /bits/ 8 <0x00 0x01>;
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cooling-levels = <127 255>;
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};
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fan@1 {
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reg = <0x01>;
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fan-tach-ch = /bits/ 8 <0x02 0x03>;
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cooling-levels = /bits/ 8 <127 255>;
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};
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fan@2 {
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reg = <0x02>;
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fan-tach-ch = /bits/ 8 <0x04 0x05>;
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cooling-levels = /bits/ 8 <127 255>;
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};
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fan@3 {
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reg = <0x03>;
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fan-tach-ch = /bits/ 8 <0x06 0x07>;
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cooling-levels = /bits/ 8 <127 255>;
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};
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fan@4 {
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reg = <0x04>;
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fan-tach-ch = /bits/ 8 <0x08 0x09>;
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cooling-levels = /bits/ 8 <127 255>;
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};
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fan@5 {
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reg = <0x05>;
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fan-tach-ch = /bits/ 8 <0x0A 0x0B>;
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cooling-levels = /bits/ 8 <127 255>;
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};
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fan@6 {
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reg = <0x06>;
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fan-tach-ch = /bits/ 8 <0x0C 0x0D>;
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cooling-levels = /bits/ 8 <127 255>;
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};
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fan@7 {
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reg = <0x07>;
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fan-tach-ch = /bits/ 8 <0x0E 0x0F>;
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cooling-levels = /bits/ 8 <127 255>;
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};
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};
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&spi0 {
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cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
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status = "okay";
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Flash@0 {
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compatible = "winbond,w25q128",
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"jedec,spi-nor";
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reg = <0x0>;
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <5000000>;
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partition@0 {
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label = "spi0_spare1";
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reg = <0x0000000 0x800000>;
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};
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partition@1 {
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label = "spi0_spare2";
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reg = <0x800000 0x0>;
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};
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};
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};
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&spi1 {
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cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
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status = "okay";
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Flash@0 {
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compatible = "winbond,w25q128fw",
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"jedec,spi-nor";
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reg = <0x0>;
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <5000000>;
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partition@0 {
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label = "spi1_spare1";
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reg = <0x0000000 0x800000>;
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};
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partition@1 {
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label = "spi1_spare2";
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reg = <0x800000 0x0>;
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};
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};
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};
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&pinctrl {
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pinctrl-names = "default";
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pinctrl-0 = < &iox1_pins
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&pin8_input
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&pin9_output_high
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&pin10_input
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&pin11_output_high
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&pin16_input
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&pin24_output_high
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&pin25_output_low
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&pin32_output_high
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&jtag2_pins
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&pin61_output_high
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&pin62_output_high
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&pin63_output_high
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&lpc_pins
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&pin160_input
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&pin162_input
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&pin168_input
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&pin169_input
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&pin170_input
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&pin187_output_high
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&pin190_input
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&pin191_output_high
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&pin192_output_high
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&pin197_output_low
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&ddc_pins
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&pin218_input
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&pin219_output_low
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&pin220_output_low
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&pin221_output_high
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&pin222_input
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&pin223_output_low
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&spix_pins
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&pin228_output_low
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&pin231_output_high
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&pin255_input>;
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};
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157
arch/arm/dts/nuvoton-npcm750-pincfg-evb.dtsi
Normal file
157
arch/arm/dts/nuvoton-npcm750-pincfg-evb.dtsi
Normal file
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@ -0,0 +1,157 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2018 Nuvoton Technology
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/ {
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pinctrl: pinctrl@f0800000 {
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pin8_input: pin8-input {
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pins = "GPIO8/LKGPO1";
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bias-disable;
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input-enable;
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};
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pin9_output_high: pin9-output-high {
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pins = "GPIO9/LKGPO2";
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bias-disable;
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output-high;
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};
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pin10_input: pin10-input {
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pins = "GPIO10/IOXHLD";
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bias-disable;
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input-enable;
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};
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pin11_output_high: pin11-output-high {
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pins = "GPIO11/IOXHCK";
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bias-disable;
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output-high;
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};
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pin16_input: pin16-input {
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pins = "GPIO16/LKGPO0";
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bias-disable;
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input-enable;
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};
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pin24_output_high: pin24-output-high {
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pins = "GPIO24/IOXHDO";
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bias-disable;
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output-high;
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};
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pin25_output_low: pin25-output-low {
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pins = "GPIO25/IOXHDI";
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bias-disable;
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output-low;
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};
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pin32_output_high: pin32-output-high {
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pins = "GPIO32/nSPI0CS1";
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bias-disable;
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output-high;
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};
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pin61_output_high: pin61-output-high {
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pins = "GPO61/nDTR1_BOUT1/STRAP6";
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bias-disable;
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output-high;
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};
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pin62_output_high: pin62-output-high {
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pins = "GPO62/nRTST1/STRAP5";
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bias-disable;
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output-high;
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};
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pin63_output_high: pin63-output-high {
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pins = "GPO63/TXD1/STRAP4";
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bias-disable;
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output-high;
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};
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pin160_input: pin160-input {
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pins = "GPIO160/CLKOUT/RNGOSCOUT";
|
||||
bias-disable;
|
||||
input-enable;
|
||||
};
|
||||
pin162_input: pin162-input {
|
||||
pins = "GPIO162/SERIRQ";
|
||||
bias-disable;
|
||||
input-enable;
|
||||
};
|
||||
pin168_input: pin168-input {
|
||||
pins = "GPIO168/nCLKRUN/nESPIALERT";
|
||||
bias-disable;
|
||||
input-enable;
|
||||
};
|
||||
pin169_input: pin169-input {
|
||||
pins = "GPIO169/nSCIPME";
|
||||
bias-disable;
|
||||
input-enable;
|
||||
};
|
||||
pin170_input: pin170-input {
|
||||
pins = "GPIO170/nSMI";
|
||||
bias-disable;
|
||||
input-enable;
|
||||
};
|
||||
pin187_output_high: pin187-output-high {
|
||||
pins = "GPIO187/nSPI3CS1";
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
pin190_input: pin190-input {
|
||||
pins = "GPIO190/nPRD_SMI";
|
||||
bias-disable;
|
||||
input-enable;
|
||||
};
|
||||
pin191_output_high: pin191-output-high {
|
||||
pins = "GPIO191";
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
pin192_output_high: pin192-output-high {
|
||||
pins = "GPIO192";
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
pin197_output_low: pin197-output-low {
|
||||
pins = "GPIO197/SMB0DEN";
|
||||
bias-disable;
|
||||
output-low;
|
||||
};
|
||||
pin218_input: pin218-input {
|
||||
pins = "GPIO218/nWDO1";
|
||||
bias-disable;
|
||||
input-enable;
|
||||
};
|
||||
pin219_output_low: pin219-output-low {
|
||||
pins = "GPIO219/nWDO2";
|
||||
bias-disable;
|
||||
output-low;
|
||||
};
|
||||
pin220_output_low: pin220-output-low {
|
||||
pins = "GPIO220/SMB12SCL";
|
||||
bias-disable;
|
||||
output-low;
|
||||
};
|
||||
pin221_output_high: pin221-output-high {
|
||||
pins = "GPIO221/SMB12SDA";
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
pin222_input: pin222-input {
|
||||
pins = "GPIO222/SMB13SCL";
|
||||
bias-disable;
|
||||
input-enable;
|
||||
};
|
||||
pin223_output_low: pin223-output-low {
|
||||
pins = "GPIO223/SMB13SDA";
|
||||
bias-disable;
|
||||
output-low;
|
||||
};
|
||||
pin228_output_low: pin228-output-low {
|
||||
pins = "GPIO228/nSPIXCS1";
|
||||
bias-disable;
|
||||
output-low;
|
||||
};
|
||||
pin231_output_high: pin231-output-high {
|
||||
pins = "GPIO230/SPIXD3";
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
pin255_input: pin255-input {
|
||||
pins = "GPI255/DACOSEL";
|
||||
bias-disable;
|
||||
input-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
62
arch/arm/dts/nuvoton-npcm750.dtsi
Normal file
62
arch/arm/dts/nuvoton-npcm750.dtsi
Normal file
|
|
@ -0,0 +1,62 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com
|
||||
// Copyright 2018 Google, Inc.
|
||||
|
||||
#include "nuvoton-common-npcm7xx.dtsi"
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "nuvoton,npcm750-smp";
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
clocks = <&clk NPCM7XX_CLK_CPU>;
|
||||
clock-names = "clk_cpu";
|
||||
reg = <0>;
|
||||
next-level-cache = <&l2>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
clocks = <&clk NPCM7XX_CLK_CPU>;
|
||||
clock-names = "clk_cpu";
|
||||
reg = <1>;
|
||||
next-level-cache = <&l2>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
timer@3fe600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0x3fe600 0x20>;
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
|
||||
IRQ_TYPE_LEVEL_HIGH)>;
|
||||
clocks = <&clk NPCM7XX_CLK_AHB>;
|
||||
};
|
||||
};
|
||||
|
||||
ahb {
|
||||
gmac1: eth@f0804000 {
|
||||
device_type = "network";
|
||||
compatible = "snps,dwmac";
|
||||
reg = <0xf0804000 0x2000>;
|
||||
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq";
|
||||
ethernet = <1>;
|
||||
clocks = <&clk_rg2refck>, <&clk NPCM7XX_CLK_AHB>;
|
||||
clock-names = "stmmaceth", "clk_gmac";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rg2_pins
|
||||
&rg2mdio_pins>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
65
arch/arm/include/asm/arch-npcm7xx/gcr.h
Normal file
65
arch/arm/include/asm/arch-npcm7xx/gcr.h
Normal file
|
|
@ -0,0 +1,65 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
|
||||
#ifndef __NPCM750_GCR_H_
|
||||
#define __NPCM750_GCR_H_
|
||||
|
||||
/* On-Chip POLEG NPCM750 VERSIONS */
|
||||
#define POLEG_Z1 0x00A92750
|
||||
#define POLEG_A1 0x04A92750
|
||||
#define POLEG_NPCM750 0x00000000
|
||||
#define POLEG_NPCM730 0x00300395
|
||||
#define POLEG_NPCM710 0x00200380
|
||||
|
||||
#define PWRON_SECEN 7 /* STRAP8 */
|
||||
#define NPCM_GCR_BA 0xF0800000
|
||||
|
||||
struct npcm_gcr {
|
||||
unsigned int pdid;
|
||||
unsigned int pwron;
|
||||
unsigned char res1[0x4];
|
||||
unsigned int mfsel1;
|
||||
unsigned int mfsel2;
|
||||
unsigned int miscpe;
|
||||
unsigned char res2[0x20];
|
||||
unsigned int spswc;
|
||||
unsigned int intcr;
|
||||
unsigned int intsr;
|
||||
unsigned char res3[0xc];
|
||||
unsigned int hifcr;
|
||||
unsigned int sd1irv1;
|
||||
unsigned int sd1irv2;
|
||||
unsigned char res4[0x4];
|
||||
unsigned int intcr2;
|
||||
unsigned int mfsel3;
|
||||
unsigned int srcnt;
|
||||
unsigned int ressr;
|
||||
unsigned int rlockr1;
|
||||
unsigned int flockr1;
|
||||
unsigned int dscnt;
|
||||
unsigned int mdlr;
|
||||
unsigned char res5[0x18];
|
||||
unsigned int davclvlr;
|
||||
unsigned int intcr3;
|
||||
unsigned char res6[0xc];
|
||||
unsigned int vsintr;
|
||||
unsigned int mfsel4;
|
||||
unsigned int sd2irv1;
|
||||
unsigned int sd2irv2;
|
||||
unsigned char res7[0x8];
|
||||
unsigned int cpbpntr;
|
||||
unsigned char res8[0x8];
|
||||
unsigned int cpctl;
|
||||
unsigned int cp2bst;
|
||||
unsigned int b2cpnt;
|
||||
unsigned int cppctl;
|
||||
unsigned int i2csegsel;
|
||||
unsigned int i2csegctl;
|
||||
unsigned int vsrcr;
|
||||
unsigned int mlockr;
|
||||
unsigned char res9[0x4c];
|
||||
unsigned int scrpad;
|
||||
unsigned int usb1phyctl;
|
||||
unsigned int usb2phyctl;
|
||||
};
|
||||
|
||||
#endif
|
||||
26
arch/arm/mach-npcm/Kconfig
Normal file
26
arch/arm/mach-npcm/Kconfig
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
if ARCH_NPCM
|
||||
|
||||
config SYS_ARCH
|
||||
default "arm"
|
||||
|
||||
config SYS_TEXT_BASE
|
||||
default 0x8000
|
||||
|
||||
choice
|
||||
prompt "Nuvoton SoC select"
|
||||
default ARCH_NPCM7xx
|
||||
|
||||
config ARCH_NPCM7xx
|
||||
bool "Support Nuvoton NPCM7xx SoC"
|
||||
select CPU_V7A
|
||||
select OF_CONTROL
|
||||
select DM
|
||||
help
|
||||
General support for NPCM7xx BMC (Poleg).
|
||||
Nuvoton NPCM7xx BMC is based on the Cortex A9.
|
||||
|
||||
endchoice
|
||||
|
||||
source "arch/arm/mach-npcm/npcm7xx/Kconfig"
|
||||
|
||||
endif
|
||||
1
arch/arm/mach-npcm/Makefile
Normal file
1
arch/arm/mach-npcm/Makefile
Normal file
|
|
@ -0,0 +1 @@
|
|||
obj-$(CONFIG_ARCH_NPCM7xx) += npcm7xx/
|
||||
22
arch/arm/mach-npcm/npcm7xx/Kconfig
Normal file
22
arch/arm/mach-npcm/npcm7xx/Kconfig
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
if ARCH_NPCM7xx
|
||||
|
||||
config SYS_CPU
|
||||
default "armv7"
|
||||
|
||||
config SYS_SOC
|
||||
default "npcm7xx"
|
||||
|
||||
config TARGET_POLEG
|
||||
bool "NPCM POLEG board"
|
||||
help
|
||||
poleg EVB is Nuvoton evaluation board for NPCM750 SoC,
|
||||
supports general functions of Basebase Management
|
||||
Controller(BMC).
|
||||
|
||||
config SYS_MEM_TOP_HIDE
|
||||
hex "Reserved TOP memory"
|
||||
default 0x03000000
|
||||
|
||||
source "board/nuvoton/poleg_evb/Kconfig"
|
||||
|
||||
endif
|
||||
1
arch/arm/mach-npcm/npcm7xx/Makefile
Normal file
1
arch/arm/mach-npcm/npcm7xx/Makefile
Normal file
|
|
@ -0,0 +1 @@
|
|||
obj-$(CONFIG_TARGET_POLEG) += cpu.o l2_cache_pl310_init.o l2_cache_pl310.o
|
||||
66
arch/arm/mach-npcm/npcm7xx/cpu.c
Normal file
66
arch/arm/mach-npcm/npcm7xx/cpu.c
Normal file
|
|
@ -0,0 +1,66 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (c) 2021 Nuvoton Technology Corp.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <cpu_func.h>
|
||||
#include <asm/armv7.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/gcr.h>
|
||||
|
||||
int print_cpuinfo(void)
|
||||
{
|
||||
struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
|
||||
unsigned int id, mdlr;
|
||||
|
||||
mdlr = readl(&gcr->mdlr);
|
||||
|
||||
printf("CPU: ");
|
||||
|
||||
switch (mdlr) {
|
||||
case POLEG_NPCM750:
|
||||
printf("NPCM750 ");
|
||||
break;
|
||||
case POLEG_NPCM730:
|
||||
printf("NPCM730 ");
|
||||
break;
|
||||
case POLEG_NPCM710:
|
||||
printf("NPCM710 ");
|
||||
break;
|
||||
default:
|
||||
printf("NPCM7XX ");
|
||||
break;
|
||||
}
|
||||
|
||||
id = readl(&gcr->pdid);
|
||||
switch (id) {
|
||||
case POLEG_Z1:
|
||||
printf("Z1 is no supported! @ ");
|
||||
break;
|
||||
case POLEG_A1:
|
||||
printf("A1 @ ");
|
||||
break;
|
||||
default:
|
||||
printf("Unknown\n");
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void s_init(void)
|
||||
{
|
||||
/* Invalidate L2 cache in lowlevel_init */
|
||||
v7_outer_cache_inval_all();
|
||||
}
|
||||
|
||||
void enable_caches(void)
|
||||
{
|
||||
dcache_enable();
|
||||
}
|
||||
|
||||
void disable_caches(void)
|
||||
{
|
||||
dcache_disable();
|
||||
}
|
||||
29
arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c
Normal file
29
arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (c) 2021 Nuvoton Technology Corp.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/pl310.h>
|
||||
|
||||
void l2_pl310_init(void);
|
||||
|
||||
void set_pl310_ctrl(u32 enable)
|
||||
{
|
||||
struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
|
||||
|
||||
writel(enable, &pl310->pl310_ctrl);
|
||||
}
|
||||
|
||||
void v7_outer_cache_enable(void)
|
||||
{
|
||||
l2_pl310_init();
|
||||
|
||||
set_pl310_ctrl(1);
|
||||
}
|
||||
|
||||
void v7_outer_cache_disable(void)
|
||||
{
|
||||
set_pl310_ctrl(0);
|
||||
}
|
||||
71
arch/arm/mach-npcm/npcm7xx/l2_cache_pl310_init.S
Normal file
71
arch/arm/mach-npcm/npcm7xx/l2_cache_pl310_init.S
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2021 Nuvoton Technology Corp.
|
||||
*/
|
||||
|
||||
.align 5
|
||||
|
||||
#include <linux/linkage.h>
|
||||
|
||||
#ifndef CONFIG_SYS_L2CACHE_OFF
|
||||
|
||||
ENTRY(l2_pl310_init)
|
||||
|
||||
@------------------------------------------------------------------
|
||||
@ L2CC (PL310) Initialization
|
||||
@------------------------------------------------------------------
|
||||
@ In this example PL310 PA = VA. The memory was marked as Device memory
|
||||
@ in previous stages when defining CORE0 private address space
|
||||
LDR r0, =0xF03FC000 @ A9_BASE_ADDR
|
||||
|
||||
@ Disable L2 Cache controller just in case it is already on
|
||||
LDR r1, =0x0
|
||||
STR r1, [r0,#0x100]
|
||||
|
||||
@ Set aux cntrl
|
||||
@ Way size = 32KB
|
||||
@ Way = 16
|
||||
LDR r1, =0x02050000
|
||||
ORR r1, r1, #(1 << 29) @ Instruction prefetch enable
|
||||
ORR r1, r1, #(1 << 28) @ Data prefetch enable
|
||||
ORR r1, r1, #(1 << 22) @ cache replacement policy
|
||||
STR r1, [r0,#0x104] @ auxilary control reg at offset 0x104
|
||||
|
||||
@ Set tag RAM latency
|
||||
@ 1 cycle RAM write access latency
|
||||
@ 1 cycle RAM read access latency
|
||||
@ 1 cycle RAM setup latency
|
||||
LDR r1, =0x00000000
|
||||
STR r1, [r0,#0x108] @ tag ram control reg at offset 0x108
|
||||
|
||||
@ Set Data RAM latency
|
||||
@ 1 cycle RAM write access latency
|
||||
@ 2 cycles RAM read access latency
|
||||
@ 1 cycle RAM setup latency
|
||||
LDR r1, =0x00000000
|
||||
STR r1, [r0,#0x10C] @ data ram control reg at offset 0x108
|
||||
|
||||
@Cache maintenance - invalidate 16 ways (0xffff) - base offset 0x77C
|
||||
LDR r1, =0xFFFF
|
||||
STR r1, [r0,#0x77C] @ invalidate by way register at offset 0x77C
|
||||
poll_invalidate:
|
||||
LDR r1, [r0,#0x77C] @ invalidate by way register at offset 0x77C
|
||||
TST r1, #1
|
||||
BNE poll_invalidate
|
||||
|
||||
@ Ensure L2 remains disabled for the time being
|
||||
LDR r1, =0x0
|
||||
STR r1, [r0,#0x100]
|
||||
|
||||
MRC p15, 4, r0, c15, c0, 0 @ Read periph base address
|
||||
@ SCU offset from base of private peripheral space = 0x000
|
||||
|
||||
LDR r1, [r0, #0x0] @ Read the SCU Control Register
|
||||
ORR r1, r1, #0x1 @ Set bit 0 (The Enable bit)
|
||||
STR r1, [r0, #0x0] @ Write back modifed value
|
||||
|
||||
BX lr
|
||||
|
||||
ENDPROC(l2_pl310_init)
|
||||
|
||||
#endif
|
||||
25
board/nuvoton/poleg_evb/Kconfig
Normal file
25
board/nuvoton/poleg_evb/Kconfig
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
if TARGET_POLEG
|
||||
|
||||
config SYS_BOARD
|
||||
default "poleg_evb"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "nuvoton"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "poleg"
|
||||
|
||||
choice
|
||||
prompt "Target board select"
|
||||
default TARGET_POLEG_EVB
|
||||
|
||||
config TARGET_POLEG_EVB
|
||||
bool "Poleg EVB"
|
||||
help
|
||||
poleg EVB is Nuvoton evaluation board for NPCM750 SoC,
|
||||
supports general functions of Basebase Management
|
||||
Controller(BMC).
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
7
board/nuvoton/poleg_evb/MAINTAINERS
Normal file
7
board/nuvoton/poleg_evb/MAINTAINERS
Normal file
|
|
@ -0,0 +1,7 @@
|
|||
Poleg EVB
|
||||
M: Stanley Chu <yschu@nuvoton.com>
|
||||
M: Jim Liu <JJLIU0@nuvoton.com>
|
||||
S: Maintained
|
||||
F: board/nuvoton/poleg_evb/
|
||||
F: include/configs/poleg.h
|
||||
F: configs/poleg_evb_defconfig
|
||||
1
board/nuvoton/poleg_evb/Makefile
Normal file
1
board/nuvoton/poleg_evb/Makefile
Normal file
|
|
@ -0,0 +1 @@
|
|||
obj-y := poleg_evb.o
|
||||
48
board/nuvoton/poleg_evb/poleg_evb.c
Normal file
48
board/nuvoton/poleg_evb/poleg_evb.c
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
*
|
||||
* Copyright (c) 2021 Nuvoton Technology Corp.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/gcr.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
|
||||
|
||||
int ramsize = (readl(&gcr->intcr3) >> 8) & 0x7;
|
||||
|
||||
switch (ramsize) {
|
||||
case 0:
|
||||
gd->ram_size = 0x08000000; /* 128 MB. */
|
||||
break;
|
||||
case 1:
|
||||
gd->ram_size = 0x10000000; /* 256 MB. */
|
||||
break;
|
||||
case 2:
|
||||
gd->ram_size = 0x20000000; /* 512 MB. */
|
||||
break;
|
||||
case 3:
|
||||
gd->ram_size = 0x40000000; /* 1024 MB. */
|
||||
break;
|
||||
case 4:
|
||||
gd->ram_size = 0x80000000; /* 2048 MB. */
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
40
configs/poleg_evb_defconfig
Normal file
40
configs/poleg_evb_defconfig
Normal file
|
|
@ -0,0 +1,40 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_ARCH_NPCM=y
|
||||
CONFIG_SYS_TEXT_BASE=0x8200
|
||||
CONFIG_SYS_MALLOC_LEN=0x240000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x1000
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_ENV_SIZE=0x40000
|
||||
CONFIG_ENV_OFFSET=0x100000
|
||||
CONFIG_ENV_SECT_SIZE=0x4000
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="nuvoton-npcm750-evb"
|
||||
CONFIG_ARCH_NPCM7xx=y
|
||||
CONFIG_TARGET_POLEG=y
|
||||
CONFIG_SYS_LOAD_ADDR=0x10000000
|
||||
CONFIG_ENV_ADDR=0x80100000
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
CONFIG_BOOTCOMMAND="run common_bootargs; run romboot"
|
||||
CONFIG_SYS_PROMPT="U-Boot>"
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_SPI=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_UUID=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCONF=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_NPCM_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_SYSRESET_WATCHDOG=y
|
||||
CONFIG_TIMER=y
|
||||
CONFIG_NPCM_TIMER=y
|
||||
44
include/configs/poleg.h
Normal file
44
include/configs/poleg.h
Normal file
|
|
@ -0,0 +1,44 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2021 Nuvoton Technology Corp.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_POLEG_H
|
||||
#define __CONFIG_POLEG_H
|
||||
|
||||
#ifndef CONFIG_SYS_L2CACHE_OFF
|
||||
#define CONFIG_SYS_L2_PL310 1
|
||||
#define CONFIG_SYS_PL310_BASE 0xF03FC000 /* L2 - Cache Regs Base (4k Space)*/
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MAXARGS 32
|
||||
#define CONFIG_SYS_CBSIZE 256
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_BOOTMAPSZ (0x30 << 20)
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x0
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (0x00008000 - GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
/* Default environemnt variables */
|
||||
#define CONFIG_SERVERIP 192.168.0.1
|
||||
#define CONFIG_IPADDR 192.168.0.2
|
||||
#define CONFIG_NETMASK 255.255.255.0
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80200000\0" \
|
||||
"stdin=serial\0" \
|
||||
"stdout=serial\0" \
|
||||
"stderr=serial\0" \
|
||||
"ethact=eth${eth_num}\0" \
|
||||
"romboot=echo Booting from flash; echo +++ uimage at 0x${uimage_flash_addr}; " \
|
||||
"echo Using bootargs: ${bootargs};bootm ${uimage_flash_addr}\0" \
|
||||
"autostart=yes\0" \
|
||||
"eth_num=0\0" \
|
||||
"ethaddr=00:00:F7:A0:00:FC\0" \
|
||||
"eth1addr=00:00:F7:A0:00:FD\0" \
|
||||
"eth2addr=00:00:F7:A0:00:FE\0" \
|
||||
"eth3addr=00:00:F7:A0:00:FF\0" \
|
||||
"common_bootargs=setenv bootargs earlycon=${earlycon} root=/dev/ram " \
|
||||
"console=${console} mem=${mem} ramdisk_size=48000 basemac=${ethaddr}\0" \
|
||||
"sd_prog=fatload mmc 0 10000000 image-bmc; cp.b 10000000 80000000 ${filesize}\0" \
|
||||
"sd_run=fatload mmc 0 10000000 image-bmc; bootm 10200000\0" \
|
||||
"\0"
|
||||
|
||||
#endif
|
||||
91
include/dt-bindings/reset/nuvoton,npcm7xx-reset.h
Normal file
91
include/dt-bindings/reset/nuvoton,npcm7xx-reset.h
Normal file
|
|
@ -0,0 +1,91 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
// Copyright (c) 2020 Nuvoton Technology corporation.
|
||||
|
||||
#ifndef _DT_BINDINGS_NPCM7XX_RESET_H
|
||||
#define _DT_BINDINGS_NPCM7XX_RESET_H
|
||||
|
||||
#define NPCM7XX_RESET_IPSRST1 0x20
|
||||
#define NPCM7XX_RESET_IPSRST2 0x24
|
||||
#define NPCM7XX_RESET_IPSRST3 0x34
|
||||
|
||||
/* Reset lines on IP1 reset module (NPCM7XX_RESET_IPSRST1) */
|
||||
#define NPCM7XX_RESET_FIU3 1
|
||||
#define NPCM7XX_RESET_UDC1 5
|
||||
#define NPCM7XX_RESET_EMC1 6
|
||||
#define NPCM7XX_RESET_UART_2_3 7
|
||||
#define NPCM7XX_RESET_UDC2 8
|
||||
#define NPCM7XX_RESET_PECI 9
|
||||
#define NPCM7XX_RESET_AES 10
|
||||
#define NPCM7XX_RESET_UART_0_1 11
|
||||
#define NPCM7XX_RESET_MC 12
|
||||
#define NPCM7XX_RESET_SMB2 13
|
||||
#define NPCM7XX_RESET_SMB3 14
|
||||
#define NPCM7XX_RESET_SMB4 15
|
||||
#define NPCM7XX_RESET_SMB5 16
|
||||
#define NPCM7XX_RESET_PWM_M0 18
|
||||
#define NPCM7XX_RESET_TIMER_0_4 19
|
||||
#define NPCM7XX_RESET_TIMER_5_9 20
|
||||
#define NPCM7XX_RESET_EMC2 21
|
||||
#define NPCM7XX_RESET_UDC4 22
|
||||
#define NPCM7XX_RESET_UDC5 23
|
||||
#define NPCM7XX_RESET_UDC6 24
|
||||
#define NPCM7XX_RESET_UDC3 25
|
||||
#define NPCM7XX_RESET_ADC 27
|
||||
#define NPCM7XX_RESET_SMB6 28
|
||||
#define NPCM7XX_RESET_SMB7 29
|
||||
#define NPCM7XX_RESET_SMB0 30
|
||||
#define NPCM7XX_RESET_SMB1 31
|
||||
|
||||
/* Reset lines on IP2 reset module (NPCM7XX_RESET_IPSRST2) */
|
||||
#define NPCM7XX_RESET_MFT0 0
|
||||
#define NPCM7XX_RESET_MFT1 1
|
||||
#define NPCM7XX_RESET_MFT2 2
|
||||
#define NPCM7XX_RESET_MFT3 3
|
||||
#define NPCM7XX_RESET_MFT4 4
|
||||
#define NPCM7XX_RESET_MFT5 5
|
||||
#define NPCM7XX_RESET_MFT6 6
|
||||
#define NPCM7XX_RESET_MFT7 7
|
||||
#define NPCM7XX_RESET_MMC 8
|
||||
#define NPCM7XX_RESET_SDHC 9
|
||||
#define NPCM7XX_RESET_GFX_SYS 10
|
||||
#define NPCM7XX_RESET_AHB_PCIBRG 11
|
||||
#define NPCM7XX_RESET_VDMA 12
|
||||
#define NPCM7XX_RESET_ECE 13
|
||||
#define NPCM7XX_RESET_VCD 14
|
||||
#define NPCM7XX_RESET_OTP 16
|
||||
#define NPCM7XX_RESET_SIOX1 18
|
||||
#define NPCM7XX_RESET_SIOX2 19
|
||||
#define NPCM7XX_RESET_3DES 21
|
||||
#define NPCM7XX_RESET_PSPI1 22
|
||||
#define NPCM7XX_RESET_PSPI2 23
|
||||
#define NPCM7XX_RESET_GMAC2 25
|
||||
#define NPCM7XX_RESET_USB_HOST 26
|
||||
#define NPCM7XX_RESET_GMAC1 28
|
||||
#define NPCM7XX_RESET_CP 31
|
||||
|
||||
/* Reset lines on IP3 reset module (NPCM7XX_RESET_IPSRST3) */
|
||||
#define NPCM7XX_RESET_PWM_M1 0
|
||||
#define NPCM7XX_RESET_SMB12 1
|
||||
#define NPCM7XX_RESET_SPIX 2
|
||||
#define NPCM7XX_RESET_SMB13 3
|
||||
#define NPCM7XX_RESET_UDC0 4
|
||||
#define NPCM7XX_RESET_UDC7 5
|
||||
#define NPCM7XX_RESET_UDC8 6
|
||||
#define NPCM7XX_RESET_UDC9 7
|
||||
#define NPCM7XX_RESET_PCI_MAILBOX 9
|
||||
#define NPCM7XX_RESET_SMB14 12
|
||||
#define NPCM7XX_RESET_SHA 13
|
||||
#define NPCM7XX_RESET_SEC_ECC 14
|
||||
#define NPCM7XX_RESET_PCIE_RC 15
|
||||
#define NPCM7XX_RESET_TIMER_10_14 16
|
||||
#define NPCM7XX_RESET_RNG 17
|
||||
#define NPCM7XX_RESET_SMB15 18
|
||||
#define NPCM7XX_RESET_SMB8 19
|
||||
#define NPCM7XX_RESET_SMB9 20
|
||||
#define NPCM7XX_RESET_SMB10 21
|
||||
#define NPCM7XX_RESET_SMB11 22
|
||||
#define NPCM7XX_RESET_ESPI 23
|
||||
#define NPCM7XX_RESET_USB_PHY_1 24
|
||||
#define NPCM7XX_RESET_USB_PHY_2 25
|
||||
|
||||
#endif
|
||||
Loading…
Reference in a new issue