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https://github.com/AsahiLinux/u-boot
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imx: power-domain: Get rid of SMCCC dependency
This driver is the only SMCCC dependency in iMX8M U-Boot port. Rework the driver based on Linux GPCv2 driver to directly control the GPCv2 block instead of using SMCCC calls. This way, U-Boot can operate the i.MX8M power domains without depending on anything else. This is losely based on Linux GPCv2 driver. The GPU, VPU, MIPI power domains are not supported to save space, since they are not useful in the bootloader. The only domains kept are ones for HSIO, PCIe, USB. Tested-By: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice-defconfig Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Marek Vasut
Stefano Babic
parent
19842b6a20
commit
4eb82c2e56
2 changed files with 361 additions and 19 deletions
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@ -35,6 +35,7 @@ config IMX8_POWER_DOMAIN
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config IMX8M_POWER_DOMAIN
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bool "Enable i.MX8M power domain driver"
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depends on POWER_DOMAIN && ARCH_IMX8M
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select CLK
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help
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Enable support for manipulating NXP i.MX8M on-SoC power domains via
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requests to the ATF.
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@ -4,6 +4,7 @@
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <malloc.h>
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#include <power-domain-uclass.h>
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@ -12,52 +13,361 @@
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#include <asm/mach-imx/sys_proto.h>
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#include <dm/device-internal.h>
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#include <dm/device.h>
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#include <dm/device_compat.h>
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#include <imx_sip.h>
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#include <linux/arm-smccc.h>
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#include <linux/bitmap.h>
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#include <wait_bit.h>
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#include <dt-bindings/power/imx8mm-power.h>
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#include <dt-bindings/power/imx8mn-power.h>
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#include <dt-bindings/power/imx8mq-power.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define GPC_PGC_CPU_MAPPING 0x0ec
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#define IMX8M_PCIE2_A53_DOMAIN BIT(15)
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#define IMX8M_OTG2_A53_DOMAIN BIT(5)
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#define IMX8M_OTG1_A53_DOMAIN BIT(4)
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#define IMX8M_PCIE1_A53_DOMAIN BIT(3)
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#define IMX8MM_OTG2_A53_DOMAIN BIT(5)
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#define IMX8MM_OTG1_A53_DOMAIN BIT(4)
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#define IMX8MM_PCIE_A53_DOMAIN BIT(3)
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#define IMX8MN_OTG1_A53_DOMAIN BIT(4)
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#define IMX8MN_MIPI_A53_DOMAIN BIT(2)
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#define GPC_PU_PGC_SW_PUP_REQ 0x0f8
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#define GPC_PU_PGC_SW_PDN_REQ 0x104
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#define IMX8M_PCIE2_SW_Pxx_REQ BIT(13)
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#define IMX8M_OTG2_SW_Pxx_REQ BIT(3)
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#define IMX8M_OTG1_SW_Pxx_REQ BIT(2)
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#define IMX8M_PCIE1_SW_Pxx_REQ BIT(1)
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#define IMX8MM_OTG2_SW_Pxx_REQ BIT(3)
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#define IMX8MM_OTG1_SW_Pxx_REQ BIT(2)
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#define IMX8MM_PCIE_SW_Pxx_REQ BIT(1)
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#define IMX8MN_OTG1_SW_Pxx_REQ BIT(2)
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#define IMX8MN_MIPI_SW_Pxx_REQ BIT(0)
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#define GPC_M4_PU_PDN_FLG 0x1bc
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#define GPC_PU_PWRHSK 0x1fc
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#define IMX8MM_HSIO_HSK_PWRDNACKN (BIT(23) | BIT(24))
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#define IMX8MM_HSIO_HSK_PWRDNREQN (BIT(5) | BIT(6))
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#define IMX8MN_HSIO_HSK_PWRDNACKN BIT(23)
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#define IMX8MN_HSIO_HSK_PWRDNREQN BIT(5)
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/*
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* The PGC offset values in Reference Manual
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* (Rev. 1, 01/2018 and the older ones) GPC chapter's
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* GPC_PGC memory map are incorrect, below offset
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* values are from design RTL.
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*/
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#define IMX8M_PGC_PCIE1 17
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#define IMX8M_PGC_OTG1 18
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#define IMX8M_PGC_OTG2 19
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#define IMX8M_PGC_PCIE2 29
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#define IMX8MM_PGC_PCIE 17
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#define IMX8MM_PGC_OTG1 18
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#define IMX8MM_PGC_OTG2 19
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#define IMX8MN_PGC_OTG1 18
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#define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40)
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#define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc)
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#define GPC_PGC_CTRL_PCR BIT(0)
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struct imx_pgc_regs {
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u16 map;
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u16 pup;
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u16 pdn;
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u16 hsk;
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};
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struct imx_pgc_domain {
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unsigned long pgc;
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const struct {
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u32 pxx;
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u32 map;
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u32 hskreq;
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u32 hskack;
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} bits;
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const bool keep_clocks;
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};
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struct imx_pgc_domain_data {
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const struct imx_pgc_domain *domains;
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size_t domains_num;
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const struct imx_pgc_regs *pgc_regs;
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};
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struct imx8m_power_domain_plat {
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struct power_domain pd;
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const struct imx_pgc_domain *domain;
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const struct imx_pgc_regs *regs;
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struct clk_bulk clk;
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void __iomem *base;
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int resource_id;
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int has_pd;
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struct power_domain pd;
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};
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#if defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MQ)
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static const struct imx_pgc_regs imx7_pgc_regs = {
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.map = GPC_PGC_CPU_MAPPING,
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.pup = GPC_PU_PGC_SW_PUP_REQ,
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.pdn = GPC_PU_PGC_SW_PDN_REQ,
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.hsk = GPC_PU_PWRHSK,
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};
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#endif
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#ifdef CONFIG_IMX8MQ
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static const struct imx_pgc_domain imx8m_pgc_domains[] = {
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[IMX8M_POWER_DOMAIN_PCIE1] = {
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.bits = {
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.pxx = IMX8M_PCIE1_SW_Pxx_REQ,
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.map = IMX8M_PCIE1_A53_DOMAIN,
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},
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.pgc = BIT(IMX8M_PGC_PCIE1),
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},
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[IMX8M_POWER_DOMAIN_USB_OTG1] = {
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.bits = {
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.pxx = IMX8M_OTG1_SW_Pxx_REQ,
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.map = IMX8M_OTG1_A53_DOMAIN,
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},
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.pgc = BIT(IMX8M_PGC_OTG1),
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},
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[IMX8M_POWER_DOMAIN_USB_OTG2] = {
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.bits = {
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.pxx = IMX8M_OTG2_SW_Pxx_REQ,
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.map = IMX8M_OTG2_A53_DOMAIN,
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},
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.pgc = BIT(IMX8M_PGC_OTG2),
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},
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[IMX8M_POWER_DOMAIN_PCIE2] = {
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.bits = {
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.pxx = IMX8M_PCIE2_SW_Pxx_REQ,
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.map = IMX8M_PCIE2_A53_DOMAIN,
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},
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.pgc = BIT(IMX8M_PGC_PCIE2),
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},
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};
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static const struct imx_pgc_domain_data imx8m_pgc_domain_data = {
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.domains = imx8m_pgc_domains,
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.domains_num = ARRAY_SIZE(imx8m_pgc_domains),
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.pgc_regs = &imx7_pgc_regs,
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};
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#endif
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#ifdef CONFIG_IMX8MM
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static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
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[IMX8MM_POWER_DOMAIN_HSIOMIX] = {
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.bits = {
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.pxx = 0, /* no power sequence control */
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.map = 0, /* no power sequence control */
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.hskreq = IMX8MM_HSIO_HSK_PWRDNREQN,
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.hskack = IMX8MM_HSIO_HSK_PWRDNACKN,
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},
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.keep_clocks = true,
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},
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[IMX8MM_POWER_DOMAIN_PCIE] = {
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.bits = {
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.pxx = IMX8MM_PCIE_SW_Pxx_REQ,
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.map = IMX8MM_PCIE_A53_DOMAIN,
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},
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.pgc = BIT(IMX8MM_PGC_PCIE),
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},
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[IMX8MM_POWER_DOMAIN_OTG1] = {
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.bits = {
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.pxx = IMX8MM_OTG1_SW_Pxx_REQ,
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.map = IMX8MM_OTG1_A53_DOMAIN,
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},
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.pgc = BIT(IMX8MM_PGC_OTG1),
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},
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[IMX8MM_POWER_DOMAIN_OTG2] = {
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.bits = {
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.pxx = IMX8MM_OTG2_SW_Pxx_REQ,
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.map = IMX8MM_OTG2_A53_DOMAIN,
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},
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.pgc = BIT(IMX8MM_PGC_OTG2),
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},
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};
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static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = {
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.domains = imx8mm_pgc_domains,
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.domains_num = ARRAY_SIZE(imx8mm_pgc_domains),
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.pgc_regs = &imx7_pgc_regs,
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};
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#endif
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#ifdef CONFIG_IMX8MN
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static const struct imx_pgc_domain imx8mn_pgc_domains[] = {
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[IMX8MN_POWER_DOMAIN_HSIOMIX] = {
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.bits = {
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.pxx = 0, /* no power sequence control */
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.map = 0, /* no power sequence control */
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.hskreq = IMX8MN_HSIO_HSK_PWRDNREQN,
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.hskack = IMX8MN_HSIO_HSK_PWRDNACKN,
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},
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.keep_clocks = true,
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},
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[IMX8MN_POWER_DOMAIN_OTG1] = {
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.bits = {
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.pxx = IMX8MN_OTG1_SW_Pxx_REQ,
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.map = IMX8MN_OTG1_A53_DOMAIN,
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},
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.pgc = BIT(IMX8MN_PGC_OTG1),
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},
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};
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static const struct imx_pgc_domain_data imx8mn_pgc_domain_data = {
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.domains = imx8mn_pgc_domains,
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.domains_num = ARRAY_SIZE(imx8mn_pgc_domains),
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.pgc_regs = &imx7_pgc_regs,
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};
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#endif
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static int imx8m_power_domain_on(struct power_domain *power_domain)
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{
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struct udevice *dev = power_domain->dev;
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struct imx8m_power_domain_plat *pdata;
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struct imx8m_power_domain_plat *pdata = dev_get_plat(dev);
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const struct imx_pgc_domain *domain = pdata->domain;
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const struct imx_pgc_regs *regs = pdata->regs;
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void __iomem *base = pdata->base;
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u32 pgc;
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int ret;
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pdata = dev_get_plat(dev);
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if (pdata->clk.count) {
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ret = clk_enable_bulk(&pdata->clk);
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if (ret) {
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dev_err(dev, "failed to enable reset clocks\n");
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return ret;
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}
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}
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if (pdata->resource_id < 0)
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return -EINVAL;
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if (domain->bits.pxx) {
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/* request the domain to power up */
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setbits_le32(base + regs->pup, domain->bits.pxx);
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if (pdata->has_pd)
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power_domain_on(&pdata->pd);
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/*
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* As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
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* for PUP_REQ/PDN_REQ bit to be cleared
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*/
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ret = wait_for_bit_le32(base + regs->pup, domain->bits.pxx,
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false, 1000, false);
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if (ret) {
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dev_err(dev, "failed to command PGC\n");
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goto out_clk_disable;
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}
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arm_smccc_smc(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN,
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pdata->resource_id, 1, 0, 0, 0, 0, NULL);
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/* disable power control */
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for_each_set_bit(pgc, &domain->pgc, 32) {
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clrbits_le32(base + GPC_PGC_CTRL(pgc),
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GPC_PGC_CTRL_PCR);
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}
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}
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/* delay for reset to propagate */
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udelay(5);
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/* request the ADB400 to power up */
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if (domain->bits.hskreq)
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setbits_le32(base + regs->hsk, domain->bits.hskreq);
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/* Disable reset clocks for all devices in the domain */
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if (!domain->keep_clocks && pdata->clk.count)
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clk_disable_bulk(&pdata->clk);
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return 0;
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out_clk_disable:
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if (pdata->clk.count)
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clk_disable_bulk(&pdata->clk);
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return ret;
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}
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static int imx8m_power_domain_off(struct power_domain *power_domain)
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{
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struct udevice *dev = power_domain->dev;
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struct imx8m_power_domain_plat *pdata;
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pdata = dev_get_plat(dev);
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struct imx8m_power_domain_plat *pdata = dev_get_plat(dev);
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const struct imx_pgc_domain *domain = pdata->domain;
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const struct imx_pgc_regs *regs = pdata->regs;
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void __iomem *base = pdata->base;
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u32 pgc;
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int ret;
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if (pdata->resource_id < 0)
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return -EINVAL;
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/* Enable reset clocks for all devices in the domain */
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if (!domain->keep_clocks && pdata->clk.count) {
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ret = clk_enable_bulk(&pdata->clk);
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if (ret)
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return ret;
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}
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arm_smccc_smc(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN,
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pdata->resource_id, 0, 0, 0, 0, 0, NULL);
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/* request the ADB400 to power down */
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if (domain->bits.hskreq) {
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clrbits_le32(base + regs->hsk, domain->bits.hskreq);
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ret = wait_for_bit_le32(base + regs->hsk, domain->bits.hskack,
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false, 1000, false);
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if (ret) {
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dev_err(dev, "failed to power down ADB400\n");
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goto out_clk_disable;
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}
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}
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if (domain->bits.pxx) {
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/* enable power control */
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for_each_set_bit(pgc, &domain->pgc, 32) {
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setbits_le32(base + GPC_PGC_CTRL(pgc),
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GPC_PGC_CTRL_PCR);
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}
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/* request the domain to power down */
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setbits_le32(base + regs->pdn, domain->bits.pxx);
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/*
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* As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
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* for PUP_REQ/PDN_REQ bit to be cleared
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*/
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ret = wait_for_bit_le32(base + regs->pdn, domain->bits.pxx,
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false, 1000, false);
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if (ret) {
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dev_err(dev, "failed to command PGC\n");
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goto out_clk_disable;
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}
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}
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/* Disable reset clocks for all devices in the domain */
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if (pdata->clk.count)
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clk_disable_bulk(&pdata->clk);
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if (pdata->has_pd)
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power_domain_off(&pdata->pd);
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return 0;
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out_clk_disable:
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if (!domain->keep_clocks && pdata->clk.count)
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clk_disable_bulk(&pdata->clk);
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return ret;
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}
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static int imx8m_power_domain_of_xlate(struct power_domain *power_domain,
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@ -101,12 +411,36 @@ static int imx8m_power_domain_bind(struct udevice *dev)
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return 0;
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}
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static int imx8m_power_domain_probe(struct udevice *dev)
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{
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struct imx8m_power_domain_plat *pdata = dev_get_plat(dev);
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int ret;
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/* Nothing to do for non-"power-domain" driver instances. */
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if (!strstr(dev->name, "power-domain"))
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return 0;
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/* Grab optional power domain clock. */
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ret = clk_get_bulk(dev, &pdata->clk);
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if (ret && ret != -ENOENT) {
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dev_err(dev, "Failed to get domain clock (%d)\n", ret);
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return ret;
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}
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return 0;
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}
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static int imx8m_power_domain_of_to_plat(struct udevice *dev)
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{
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struct imx8m_power_domain_plat *pdata = dev_get_plat(dev);
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struct imx_pgc_domain_data *domain_data =
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(struct imx_pgc_domain_data *)dev_get_driver_data(dev);
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||||
pdata->resource_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
|
||||
"reg", -1);
|
||||
pdata->domain = &domain_data->domains[pdata->resource_id];
|
||||
pdata->regs = domain_data->pgc_regs;
|
||||
pdata->base = dev_read_addr_ptr(dev->parent);
|
||||
|
||||
if (!power_domain_get(dev, &pdata->pd))
|
||||
pdata->has_pd = 1;
|
||||
|
|
@ -115,9 +449,15 @@ static int imx8m_power_domain_of_to_plat(struct udevice *dev)
|
|||
}
|
||||
|
||||
static const struct udevice_id imx8m_power_domain_ids[] = {
|
||||
{ .compatible = "fsl,imx8mq-gpc" },
|
||||
{ .compatible = "fsl,imx8mm-gpc" },
|
||||
{ .compatible = "fsl,imx8mn-gpc" },
|
||||
#ifdef CONFIG_IMX8MQ
|
||||
{ .compatible = "fsl,imx8mq-gpc", .data = (long)&imx8m_pgc_domain_data },
|
||||
#endif
|
||||
#ifdef CONFIG_IMX8MM
|
||||
{ .compatible = "fsl,imx8mm-gpc", .data = (long)&imx8mm_pgc_domain_data },
|
||||
#endif
|
||||
#ifdef CONFIG_IMX8MN
|
||||
{ .compatible = "fsl,imx8mn-gpc", .data = (long)&imx8mn_pgc_domain_data },
|
||||
#endif
|
||||
{ }
|
||||
};
|
||||
|
||||
|
|
@ -132,6 +472,7 @@ U_BOOT_DRIVER(imx8m_power_domain) = {
|
|||
.id = UCLASS_POWER_DOMAIN,
|
||||
.of_match = imx8m_power_domain_ids,
|
||||
.bind = imx8m_power_domain_bind,
|
||||
.probe = imx8m_power_domain_probe,
|
||||
.of_to_plat = imx8m_power_domain_of_to_plat,
|
||||
.plat_auto = sizeof(struct imx8m_power_domain_plat),
|
||||
.ops = &imx8m_power_domain_ops,
|
||||
|
|
|
|||
Loading…
Reference in a new issue