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colibri-imx6ull/-emmc: synchronise device tree with linux

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Synchronise device tree with linux v5.19-rc5.

Please note that this also means that instead of the previous "generic"
U-Boot specific carrier board agnostic device trees we are now using the
regular ones for the Colibri Evaluation (carrier) board V3 (e.g.
imx6ull-colibri-eval-v3.dtb rather than the previous imx6ull-colibri.dtb
and imx6ull-colibri-emmc-eval-v3.dtb rather than the previous
imx6ull-colibri-emmc.dtb).

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
This commit is contained in:
Marcel Ziswiler 2022-07-21 15:27:31 +02:00 committed by Stefano Babic
parent 5d7a95f499
commit c21b61bff1
14 changed files with 875 additions and 303 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
arch/arm/dts/Makefile
View file

@ -884,8 +884,8 @@ dtb-$(CONFIG_MX6UL) += \
dtb-$(CONFIG_MX6ULL) += \
imx6ull-14x14-evk.dtb \
imx6ull-colibri.dtb \
imx6ull-colibri-emmc.dtb \
imx6ull-colibri-emmc-eval-v3.dtb \
imx6ull-colibri-eval-v3.dtb \
imx6ull-myir-mys-6ulx-eval.dtb \
imx6ull-seeed-npi-imx6ull-dev-board.dtb \
imx6ull-phytec-segin-ff-rdk-emmc.dtb \

1
arch/arm/dts/imx6ull-colibri-emmc-eval-v3-u-boot.dtsi Symbolic link
View file

@ -0,0 +1 @@
imx6ull-colibri-eval-v3-u-boot.dtsi

17
arch/arm/dts/imx6ull-colibri-emmc-eval-v3.dts Normal file
View file

@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright 2021 Toradex
*/
/dts-v1/;
#include "imx6ull-colibri-emmc-nonwifi.dtsi"
#include "imx6ull-colibri-eval-v3.dtsi"
/ {
model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Evaluation Board V3";
compatible = "toradex,colibri-imx6ull-emmc-eval",
"toradex,colibri-imx6ull-emmc",
"toradex,colibri-imx6ull",
"fsl,imx6ull";
};

187
arch/arm/dts/imx6ull-colibri-emmc-nonwifi.dtsi Normal file
View file

@ -0,0 +1,187 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2022 Toradex
*/
#include "imx6ull-colibri.dtsi"
/ {
aliases {
mmc0 = &usdhc2; /* eMMC */
mmc1 = &usdhc1; /* MMC 4-bit slot */
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
};
&gpio1 {
gpio-line-names = "SODIMM_8",
"SODIMM_6",
"SODIMM_129",
"SODIMM_89",
"SODIMM_19",
"SODIMM_21",
"UNUSABLE_SODIMM_180",
"UNUSABLE_SODIMM_184",
"SODIMM_4",
"SODIMM_2",
"SODIMM_106",
"SODIMM_71",
"SODIMM_23",
"SODIMM_31",
"SODIMM_99",
"SODIMM_102",
"SODIMM_33",
"SODIMM_35",
"SODIMM_25",
"SODIMM_27",
"SODIMM_36",
"SODIMM_38",
"SODIMM_32",
"SODIMM_34",
"SODIMM_135",
"SODIMM_77",
"SODIMM_100",
"SODIMM_186",
"SODIMM_196",
"SODIMM_194";
};
&gpio2 {
gpio-line-names = "SODIMM_55",
"SODIMM_63",
"SODIMM_178",
"SODIMM_188",
"SODIMM_73",
"SODIMM_30",
"SODIMM_67",
"SODIMM_104",
"",
"",
"",
"",
"",
"",
"",
"",
"SODIMM_190",
"SODIMM_47",
"SODIMM_192",
"SODIMM_49",
"SODIMM_51",
"SODIMM_53";
};
&gpio3 {
gpio-line-names = "SODIMM_56",
"SODIMM_44",
"SODIMM_68",
"SODIMM_82",
"",
"SODIMM_76",
"SODIMM_70",
"SODIMM_60",
"SODIMM_58",
"SODIMM_78",
"SODIMM_72",
"SODIMM_80",
"SODIMM_46",
"SODIMM_62",
"SODIMM_48",
"SODIMM_74",
"SODIMM_50",
"SODIMM_52",
"SODIMM_54",
"SODIMM_66",
"SODIMM_64",
"SODIMM_57",
"SODIMM_61",
"SODIMM_29",
"SODIMM_37",
"SODIMM_88",
"SODIMM_86",
"SODIMM_92",
"SODIMM_90";
};
&gpio4 {
gpio-line-names = "",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"SODIMM_140",
"SODIMM_59",
"SODIMM_142",
"SODIMM_144",
"SODIMM_133",
"SODIMM_146",
"SODIMM_28",
"SODIMM_75",
"SODIMM_96",
"SODIMM_81",
"SODIMM_94",
"SODIMM_101",
"SODIMM_103",
"SODIMM_79",
"SODIMM_97",
"SODIMM_69",
"SODIMM_98",
"SODIMM_85",
"SODIMM_65";
};
&gpio5 {
gpio-line-names = "SODIMM_43",
"SODIMM_45",
"SODIMM_137",
"SODIMM_95",
"SODIMM_107",
"SODIMM_131",
"SODIMM_93",
"",
"SODIMM_138",
"",
"SODIMM_105",
"SODIMM_127";
};
/* NAND */
&gpmi {
status = "disabled";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3
&pinctrl_gpio4 &pinctrl_gpio6 &pinctrl_gpio7
&pinctrl_gpmi_gpio>;
};
&iomuxc_snvs {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio3>;
};
/* eMMC */
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2emmc>;
assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
assigned-clock-rates = <0>, <198000000>;
bus-width = <8>;
keep-power-in-suspend;
no-1-8-v;
non-removable;
vmmc-supply = <&reg_module_3v3>;
status = "okay";
};

49
arch/arm/dts/imx6ull-colibri-emmc.dts
View file

@ -1,49 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2021 Toradex AG
*/
#include "imx6ull-colibri.dtsi"
#include "imx6ull-colibri-u-boot.dtsi"
/ {
model = "Toradex Colibri iMX6ULL 1GB (eMMC)";
compatible = "toradex,colibri-imx6ull-emmc", "toradex,colibri-imx6ull", "fsl,imx6ull";
aliases {
mmc0 = &usdhc2;
mmc1 = &usdhc1;
};
};
/* eMMC */
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2emmc>;
assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
assigned-clock-rates = <0>, <198000000>;
bus-width = <8>;
keep-power-in-suspend;
no-1-8-v;
non-removable;
vmmc-supply = <&reg_module_3v3>;
status = "okay";
};
&iomuxc {
pinctrl_usdhc2emmc: usdhc2emmcgrp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
>;
};
};

4
arch/arm/dts/imx6ull-colibri-u-boot.dtsi → arch/arm/dts/imx6ull-colibri-eval-v3-u-boot.dtsi
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2019 Toradex AG
* Copyright 2019-2022 Toradex
*/
/ {

14
arch/arm/dts/imx6ull-colibri-eval-v3.dts Normal file
View file

@ -0,0 +1,14 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2018-2022 Toradex
*/
/dts-v1/;
#include "imx6ull-colibri-nonwifi.dtsi"
#include "imx6ull-colibri-eval-v3.dtsi"
/ {
model = "Toradex Colibri iMX6ULL 256/512MB on Colibri Evaluation Board V3";
compatible = "toradex,colibri-imx6ull-eval", "fsl,imx6ull";
};

121
arch/arm/dts/imx6ull-colibri-eval-v3.dtsi Normal file
View file

@ -0,0 +1,121 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2017-2022 Toradex
*/
/ {
chosen {
stdout-path = "serial0:115200n8";
};
/* fixed crystal dedicated to mcp2515 */
clk16m: clk16m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <16000000>;
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_5v0: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_usbh_vbus: regulator-usbh-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh_reg>;
regulator-name = "VCC_USB[1-4]";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
vin-supply = <&reg_5v0>;
};
};
&adc1 {
status = "okay";
};
&ecspi1 {
status = "okay";
mcp2515: can@0 {
compatible = "microchip,mcp2515";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can_int>;
reg = <0>;
clocks = <&clk16m>;
interrupt-parent = <&gpio2>;
interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
spi-max-frequency = <10000000>;
vdd-supply = <&reg_3v3>;
xceiver-supply = <&reg_5v0>;
status = "okay";
};
};
&i2c1 {
status = "okay";
/* M41T0M6 real time clock on carrier board */
m41t0m6: rtc@68 {
compatible = "st,m41t0";
reg = <0x68>;
};
};
/* PWM <A> */
&pwm4 {
status = "okay";
};
/* PWM <B> */
&pwm5 {
status = "okay";
};
/* PWM <C> */
&pwm6 {
status = "okay";
};
/* PWM <D> */
&pwm7 {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&uart5 {
status = "okay";
};
&usbotg1 {
vbus-supply = <&reg_usbh_vbus>;
status = "okay";
};
&usbotg2 {
vbus-supply = <&reg_usbh_vbus>;
status = "okay";
};
&usdhc1 {
vmmc-supply = <&reg_3v3>;
status = "okay";
};

161
arch/arm/dts/imx6ull-colibri-nonwifi.dtsi Normal file
View file

@ -0,0 +1,161 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2018-2022 Toradex
*/
#include "imx6ull-colibri.dtsi"
/ {
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
};
&gpio1 {
gpio-line-names = "SODIMM_8",
"SODIMM_6",
"SODIMM_129",
"SODIMM_89",
"SODIMM_19",
"SODIMM_21",
"UNUSABLE_SODIMM_180",
"UNUSABLE_SODIMM_184",
"SODIMM_4",
"SODIMM_2",
"SODIMM_106",
"SODIMM_71",
"SODIMM_23",
"SODIMM_31",
"SODIMM_99",
"SODIMM_102",
"SODIMM_33",
"SODIMM_35",
"SODIMM_25",
"SODIMM_27",
"SODIMM_36",
"SODIMM_38",
"SODIMM_32",
"SODIMM_34",
"SODIMM_135",
"SODIMM_77",
"SODIMM_100",
"SODIMM_186",
"SODIMM_196",
"SODIMM_194";
};
&gpio2 {
gpio-line-names = "SODIMM_55",
"SODIMM_63",
"SODIMM_178",
"SODIMM_188",
"SODIMM_73",
"SODIMM_30",
"SODIMM_67",
"SODIMM_104",
"",
"",
"",
"",
"",
"",
"",
"",
"SODIMM_190",
"SODIMM_47",
"SODIMM_192",
"SODIMM_49",
"SODIMM_51",
"SODIMM_53";
};
&gpio3 {
gpio-line-names = "SODIMM_56",
"SODIMM_44",
"SODIMM_68",
"SODIMM_82",
"",
"SODIMM_76",
"SODIMM_70",
"SODIMM_60",
"SODIMM_58",
"SODIMM_78",
"SODIMM_72",
"SODIMM_80",
"SODIMM_46",
"SODIMM_62",
"SODIMM_48",
"SODIMM_74",
"SODIMM_50",
"SODIMM_52",
"SODIMM_54",
"SODIMM_66",
"SODIMM_64",
"SODIMM_57",
"SODIMM_61",
"SODIMM_29",
"SODIMM_37",
"SODIMM_88",
"SODIMM_86",
"SODIMM_92",
"SODIMM_90";
};
&gpio4 {
gpio-line-names = "",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"SODIMM_59",
"",
"",
"SODIMM_133",
"",
"SODIMM_28",
"SODIMM_75",
"SODIMM_96",
"SODIMM_81",
"SODIMM_94",
"SODIMM_101",
"SODIMM_103",
"SODIMM_79",
"SODIMM_97",
"SODIMM_69",
"SODIMM_98",
"SODIMM_85",
"SODIMM_65";
};
&gpio5 {
gpio-line-names = "SODIMM_43",
"SODIMM_45",
"SODIMM_137",
"SODIMM_95",
"SODIMM_107",
"SODIMM_131",
"SODIMM_93",
"",
"SODIMM_138",
"",
"SODIMM_105",
"SODIMM_127";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3
&pinctrl_gpio4 &pinctrl_gpio6 &pinctrl_gpio7>;
};
&iomuxc_snvs {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio3>;
};

45
arch/arm/dts/imx6ull-colibri.dts
View file

@ -1,45 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2018-2021 Toradex AG
*/
#include "imx6ull-colibri.dtsi"
#include "imx6ull-colibri-u-boot.dtsi"
/ {
model = "Toradex Colibri iMX6ULL";
compatible = "toradex,colibri-imx6ull", "fsl,imx6ull";
};
/* NAND */
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
fsl,use-minimum-ecc;
nand-on-flash-bbt;
nand-ecc-mode = "hw";
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
status = "okay";
};
&iomuxc {
pinctrl_gpmi_nand: gpmi-nand-grp {
fsl,pins = <
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9
MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9
MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x100a9
MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x100a9
MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x100a9
MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x100a9
MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x100a9
MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x100a9
MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x100a9
MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x100a9
MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x100a9
MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x100a9
MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x100a9
MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9
>;
};
};

564
arch/arm/dts/imx6ull-colibri.dtsi
View file

@ -1,10 +1,8 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2019-2021 Toradex AG
* Copyright 2018-2022 Toradex
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "imx6ull.dtsi"
/ {
@ -14,8 +12,43 @@
ethernet1 = &fec1;
};
chosen {
stdout-path = &uart1;
backlight: backlight {
compatible = "pwm-backlight";
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_bl_on>;
power-supply = <&reg_3v3>;
pwms = <&pwm4 0 5000000 1>;
status = "okay";
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_snvs_gpiokeys>;
wakeup {
debounce-interval = <10>;
gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */
label = "Wake-Up";
linux,code = <KEY_WAKEUP>;
wakeup-source;
};
};
panel_dpi: panel-dpi {
compatible = "edt,et057090dhu";
backlight = <&backlight>;
power-supply = <&reg_3v3>;
status = "okay";
port {
lcd_panel_in: endpoint {
remote-endpoint = <&lcdif_out>;
};
};
};
reg_module_3v3: regulator-module-3v3 {
@ -34,13 +67,6 @@
regulator-max-microvolt = <3300000>;
};
reg_5v0: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_sd1_vqmmc: regulator-sd1-vqmmc {
compatible = "regulator-gpio";
gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
@ -54,23 +80,12 @@
vin-supply = <&reg_module_3v3>;
};
reg_usbh_vbus: regulator-usbh-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh_reg>;
regulator-name = "VCC_USB[1-4]";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; /* USBH_PEN */
vin-supply = <&reg_5v0>;
};
reg_eth_phy: regulator-eth-phy {
compatible = "regulator-fixed-clock";
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "eth_phy";
regulator-name = "+V3.3_ETH";
regulator-type = "voltage";
vin-supply = <&reg_module_3v3>;
clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>;
@ -81,19 +96,34 @@
&adc1 {
num-channels = <10>;
vref-supply = <&reg_module_3v3_avdd>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc1>;
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "disabled";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
status = "disabled";
};
/* Colibri SPI */
&ecspi1 {
cs-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
};
/* Ethernet */
&fec2 {
pinctrl-names = "default";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_enet2>;
pinctrl-1 = <&pinctrl_enet2_sleep>;
phy-mode = "rmii";
phy-handle = <&ethphy1>;
phy-supply = <&reg_eth_phy>;
@ -111,9 +141,19 @@
};
};
/*
* I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
*/
/* NAND */
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
fsl,use-minimum-ecc;
nand-on-flash-bbt;
nand-ecc-mode = "hw";
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
status = "okay";
};
/* I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) */
&i2c1 {
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
@ -121,6 +161,18 @@
sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
/* Atmel maxtouch controller */
atmel_mxt_ts: touchscreen@4a {
compatible = "atmel,maxtouch";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_atmel_conn>;
reg = <0x4a>;
interrupt-parent = <&gpio5>;
interrupts = <4 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 / INT */
reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* SODIMM 106 / RST */
status = "disabled";
};
};
/*
@ -128,6 +180,8 @@
* touch screen controller
*/
&i2c2 {
/* Use low frequency to compensate for the high pull-up values. */
clock-frequency = <40000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
@ -135,7 +189,7 @@
scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
ad7879@2c {
ad7879_ts: touchscreen@2c {
compatible = "adi,ad7879-1";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_snvs_ad7879_int>;
@ -152,32 +206,40 @@
};
};
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif_dat
&pinctrl_lcdif_ctrl>;
port {
lcdif_out: endpoint {
remote-endpoint = <&lcd_panel_in>;
};
};
};
/* PWM <A> */
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
#pwm-cells = <3>;
};
/* PWM <B> */
&pwm5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm5>;
#pwm-cells = <3>;
};
/* PWM <C> */
&pwm6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm6>;
#pwm-cells = <3>;
};
/* PWM <D> */
&pwm7 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm7>;
#pwm-cells = <3>;
};
&sdma {
@ -194,7 +256,6 @@
pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>;
uart-has-rtscts;
fsl,dte-mode;
status = "okay";
};
/* Colibri UART_B */
@ -214,46 +275,73 @@
/* Colibri USBC */
&usbotg1 {
dr_mode = "host";
dr_mode = "otg";
srp-disable;
hnp-disable;
adp-disable;
status = "okay";
};
/* Colibri USBH */
&usbotg2 {
dr_mode = "host";
vbus-supply = <&reg_usbh_vbus>;
status = "okay";
};
/* Colibri MMC */
/* Colibri MMC/SD */
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>;
pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd_sleep>;
assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
assigned-clock-rates = <0>, <198000000>;
bus-width = <4>;
cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* MMC_CD */
disable-wp;
keep-power-in-suspend;
no-1-8-v;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
vqmmc-supply = <&reg_sd1_vqmmc>;
status = "okay";
wakeup-source;
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
};
&iomuxc {
pinctrl_can_int: canint-grp {
pinctrl_adc1: adc1grp {
fsl,pins = <
/* SODIMM 73 */
MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0X14
MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x3000 /* SODIMM 8 */
MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x3000 /* SODIMM 6 */
MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x3000 /* SODIMM 4 */
MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x3000 /* SODIMM 2 */
>;
};
pinctrl_enet2: enet2-grp {
pinctrl_atmel_adap: atmeladapgrp {
fsl,pins = <
MX6UL_PAD_NAND_DQS__GPIO4_IO16 0xb0a0 /* SODIMM 28 */
MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0xb0a0 /* SODIMM 30 */
>;
};
pinctrl_atmel_conn: atmelconngrp {
fsl,pins = <
MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0xb0a0 /* SODIMM 106 */
MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /* SODIMM 107 */
>;
};
pinctrl_can_int: canintgrp {
fsl,pins = <
MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x13010 /* SODIMM 73 */
>;
};
pinctrl_enet2: enet2grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
@ -268,224 +356,277 @@
>;
};
pinctrl_ecspi1_cs: ecspi1-cs-grp {
pinctrl_enet2_sleep: enet2-sleepgrp {
fsl,pins = <
MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x000a0
MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0
MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0
MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x0
MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x0
MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x0
MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0
MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x0
MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x0
>;
};
pinctrl_ecspi1: ecspi1-grp {
pinctrl_ecspi1_cs: ecspi1csgrp {
fsl,pins = <
MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0
MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0
MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100a0
MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x70a0 /* SODIMM 86 */
>;
};
pinctrl_flexcan2: flexcan2-grp {
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0 /* SODIMM 88 */
MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0 /* SODIMM 92 */
MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100a0 /* SODIMM 90 */
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020
MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020
MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020
>;
};
pinctrl_gpio_bl_on: gpio-bl-on-grp {
pinctrl_gpio_bl_on: gpioblongrp {
fsl,pins = <
MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x000a0
MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x30a0 /* SODIMM 71 */
>;
};
pinctrl_gpio1: gpio1-grp {
pinctrl_gpio1: gpio1grp {
fsl,pins = <
MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x74 /* SODIMM 55 */
MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x74 /* SODIMM 63 */
MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0X14 /* SODIMM 77 */
MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x14 /* SODIMM 99 */
MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x14 /* SODIMM 133 */
MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x14 /* SODIMM 135 */
MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x14 /* SODIMM 100 */
MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x14 /* SODIMM 102 */
MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x14 /* SODIMM 104 */
MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x14 /* SODIMM 186 */
MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x10b0 /* SODIMM 77 */
MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x70a0 /* SODIMM 99 */
MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x10b0 /* SODIMM 133 */
MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x10b0 /* SODIMM 135 */
MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x10b0 /* SODIMM 100 */
MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x70a0 /* SODIMM 102 */
MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x10b0 /* SODIMM 104 */
MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x10b0 /* SODIMM 186 */
>;
};
pinctrl_gpio2: gpio2-grp { /* Camera */
pinctrl_gpio2: gpio2grp { /* Camera */
fsl,pins = <
MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x74 /* SODIMM 69 */
MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x14 /* SODIMM 75 */
MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x14 /* SODIMM 85 */
MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x14 /* SODIMM 96 */
MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x14 /* SODIMM 98 */
MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x10b0 /* SODIMM 69 */
MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x10b0 /* SODIMM 75 */
MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x10b0 /* SODIMM 85 */
MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x10b0 /* SODIMM 96 */
MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x10b0 /* SODIMM 98 */
>;
};
pinctrl_gpio3: gpio3-grp { /* CAN2 */
pinctrl_gpio3: gpio3grp { /* CAN2 */
fsl,pins = <
MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x14 /* SODIMM 178 */
MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x14 /* SODIMM 188 */
MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x10b0 /* SODIMM 178 */
MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x10b0 /* SODIMM 188 */
>;
};
pinctrl_gpio4: gpio4-grp {
pinctrl_gpio4: gpio4grp {
fsl,pins = <
MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x74 /* SODIMM 65 */
MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x10b0 /* SODIMM 65 */
>;
};
pinctrl_gpio5: gpio5-grp { /* ATMEL MXT TOUCH */
pinctrl_gpio6: gpio6grp { /* Wifi pins */
fsl,pins = <
MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x74 /* SODIMM 106 */
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x10b0 /* SODIMM 89 */
MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x10b0 /* SODIMM 79 */
MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x10b0 /* SODIMM 81 */
MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x10b0 /* SODIMM 97 */
MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x10b0 /* SODIMM 101 */
MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0 /* SODIMM 103 */
MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x10b0 /* SODIMM 94 */
>;
};
pinctrl_gpio6: gpio6-grp { /* Wifi pins */
pinctrl_gpio7: gpio7grp { /* CAN1 */
fsl,pins = <
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x14 /* SODIMM 89 */
MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x14 /* SODIMM 79 */
MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x14 /* SODIMM 81 */
MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x14 /* SODIMM 97 */
MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x14 /* SODIMM 101 */
MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x14 /* SODIMM 103 */
MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x14 /* SODIMM 94 */
MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0xb0b0/* SODIMM 55 */
MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0xb0b0 /* SODIMM 63 */
>;
};
pinctrl_i2c1: i2c1-grp {
/*
* With an eMMC instead of a raw NAND device the following pins
* are available at SODIMM pins.
*/
pinctrl_gpmi_gpio: gpmigpiogrp {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x10b0 /* SODIMM 140 */
MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0x10b0 /* SODIMM 144 */
MX6UL_PAD_NAND_CLE__GPIO4_IO15 0x10b0 /* SODIMM 146 */
MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x10b0 /* SODIMM 142 */
>;
};
pinctrl_i2c1_gpio: i2c1-gpio-grp {
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0
MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9
MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9
MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x100a9
MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x100a9
MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x100a9
MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x100a9
MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x100a9
MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x100a9
MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x100a9
MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x100a9
MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x100a9
MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x100a9
MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x100a9
MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9
>;
};
pinctrl_i2c2: i2c2-grp {
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 /* SODIMM 196 */
MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 /* SODIMM 194 */
>;
};
pinctrl_i2c2_gpio: i2c2-gpio-grp {
pinctrl_i2c1_gpio: i2c1-gpiogrp {
fsl,pins = <
MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0
MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0
MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0 /* SODIMM 196 */
MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0 /* SODIMM 194 */
>;
};
pinctrl_lcdif_dat: lcdif-dat-grp {
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079
MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x00079
MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x00079
MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x00079
MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x00079
MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x00079
MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x00079
MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x00079
MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x00079
MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x00079
MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x00079
MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x00079
MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x00079
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x00079
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x00079
MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x00079
MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x00079
MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001f8b0
MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001f8b0
>;
};
pinctrl_lcdif_ctrl: lcdif-ctrl-grp {
pinctrl_i2c2_gpio: i2c2-gpiogrp {
fsl,pins = <
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x00079
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x00079
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x00079
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x00079
MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001f8b0
MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001f8b0
>;
};
pinctrl_pwm4: pwm4-grp {
pinctrl_lcdif_dat: lcdifdatgrp {
fsl,pins = <
MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x00079
MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079 /* SODIMM 76 */
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079 /* SODIMM 70 */
MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x00079 /* SODIMM 60 */
MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x00079 /* SODIMM 58 */
MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x00079 /* SODIMM 78 */
MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x00079 /* SODIMM 72 */
MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x00079 /* SODIMM 80 */
MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x00079 /* SODIMM 46 */
MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x00079 /* SODIMM 62 */
MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x00079 /* SODIMM 48 */
MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x00079 /* SODIMM 74 */
MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x00079 /* SODIMM 50 */
MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x00079 /* SODIMM 52 */
MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x00079 /* SODIMM 54 */
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x00079 /* SODIMM 66 */
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x00079 /* SODIMM 64 */
MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x00079 /* SODIMM 57 */
MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x00079 /* SODIMM 61 */
>;
};
pinctrl_pwm5: pwm5-grp {
pinctrl_lcdif_ctrl: lcdifctrlgrp {
fsl,pins = <
MX6UL_PAD_NAND_DQS__PWM5_OUT 0x00079
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x00079 /* SODIMM 56 */
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x00079 /* SODIMM 44 */
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x00079 /* SODIMM 68 */
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x00079 /* SODIMM 82 */
>;
};
pinctrl_pwm6: pwm6-grp {
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079
MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x00079 /* SODIMM 59 */
>;
};
pinctrl_pwm7: pwm7-grp {
pinctrl_pwm5: pwm5grp {
fsl,pins = <
MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00079
MX6UL_PAD_NAND_DQS__PWM5_OUT 0x00079 /* SODIMM 28 */
>;
};
pinctrl_uart1: uart1-grp {
pinctrl_pwm6: pwm6grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x1b0b1
MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x1b0b1
MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x1b0b1
MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079 /* SODIMM 30 */
>;
};
pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */
pinctrl_pwm7: pwm7grp {
fsl,pins = <
MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x1b0b1 /* DCD */
MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x1b0b1 /* DSR */
MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x1b0b1 /* DTR */
MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x1b0b1 /* RI */
MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00079 /* SODIMM 67 */
>;
};
pinctrl_uart2: uart2-grp {
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1
MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1
MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1
MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1
>;
};
pinctrl_uart5: uart5-grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1
MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1
MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x1b0b1 /* SODIMM 33 */
MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x1b0b1 /* SODIMM 35 */
MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x1b0b1 /* SODIMM 27 */
MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x1b0b1 /* SODIMM 25 */
>;
};
pinctrl_usbh_reg: gpio-usbh-reg {
pinctrl_uart1_ctrl1: uart1ctrl1grp { /* Additional DTR, DCD */
fsl,pins = <
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x1b0b1 /* SODIMM 129 USBH PEN */
MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x70a0 /* SODIMM 31 / DCD */
MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x10b0 /* SODIMM 29 / DSR */
MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x90b1 /* SODIMM 23 / DTR */
MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x10b0 /* SODIMM 37 / RI */
>;
};
pinctrl_usdhc1: usdhc1-grp {
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 /* SODIMM 36 */
MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 /* SODIMM 38 */
MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 /* SODIMM 32 */
MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 /* SODIMM 34 */
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1 /* SODIMM 19 */
MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1 /* SODIMM 21 */
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
pinctrl_usbh_reg: usbhreggrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /* SODIMM 129 / USBH_PEN */
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 /* SODIMM 47 */
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 /* SODIMM 190 */
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 /* SODIMM 192 */
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 /* SODIMM 49 */
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 /* SODIMM 51 */
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 /* SODIMM 53 */
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
@ -496,87 +637,108 @@
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
>;
};
pinctrl_usdhc2: usdhc2-grp {
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059
MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059
MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059
MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059
MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17059
MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17069
MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17069
MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17069
MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17069
MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17069
MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10069
MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x14
MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x10
>;
};
pinctrl_usdhc2emmc: usdhc2emmcgrp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
>;
};
};
&iomuxc_snvs {
pinctrl_snvs_gpio1: snvs-gpio1-grp {
pinctrl_snvs_gpio1: snvsgpio1grp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x14 /* SODIMM 93 */
MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x14 /* SODIMM 95 */
MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x74 /* SODIMM 105 */
MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x14 /* SODIMM 131 USBH OC */
MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x74 /* SODIMM 138 */
MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x110a0 /* SODIMM 93 */
MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x110a0 /* SODIMM 95 */
MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x1b0a0 /* SODIMM 105 */
MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0a0 /* SODIMM 131 / USBH_OC */
MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x110a0 /* SODIMM 138 */
>;
};
pinctrl_snvs_gpio2: snvs-gpio2-grp { /* ATMEL MXT TOUCH */
pinctrl_snvs_gpio3: snvsgpio3grp { /* Wifi pins */
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x74 /* SODIMM 107 */
MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 /* SODIMM 127 */
>;
};
pinctrl_snvs_gpio3: snvs-gpio3-grp { /* Wifi pins */
pinctrl_snvs_ad7879_int: snvsad7879intgrp { /* TOUCH Interrupt */
fsl,pins = <
MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x14 /* SODIMM 127 */
MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x100b0
>;
};
pinctrl_snvs_ad7879_int: snvs-ad7879-int-grp { /* TOUCH Interrupt */
pinctrl_snvs_reg_sd: snvsregsdgrp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0
MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x400100b0
>;
};
pinctrl_snvs_reg_sd: snvs-reg-sd-grp {
pinctrl_snvs_usbc_det: snvsusbcdetgrp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x4001b8b0
MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x130b0
>;
};
pinctrl_snvs_usbc_det: snvs-usbc-det-grp {
pinctrl_snvs_gpiokeys: snvsgpiokeysgrp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0
MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130a0 /* SODIMM 45 / WAKE_UP */
>;
};
pinctrl_snvs_gpiokeys: snvs-gpiokeys-grp {
pinctrl_snvs_usdhc1_cd: snvsusdhc1cdgrp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130b0
MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0a0 /* SODIMM 43 / MMC_CD */
>;
};
pinctrl_snvs_usdhc1_cd: snvs-usdhc1-cd-grp {
pinctrl_snvs_usdhc1_cd_sleep: snvsusdhc1cd-sleepgrp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* CD */
MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0
>;
};
pinctrl_snvs_wifi_pdn: snvs-wifi-pdn-grp {
pinctrl_snvs_wifi_pdn: snvswifipdngrp {
fsl,pins = <
MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x14
MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0
>;
};
};

7
board/toradex/colibri-imx6ull/MAINTAINERS
View file

@ -3,9 +3,12 @@ M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
W: http://developer.toradex.com/software/linux/linux-software
W: https://www.toradex.com/community
S: Maintained
F: arch/arm/dts/imx6ull-colibri.dts
F: arch/arm/dts/imx6ull-colibri.dtsi
F: arch/arm/dts/imx6ull-colibri-emmc.dts
F: arch/arm/dts/imx6ull-colibri-emmc-eval-v3.dts
F: arch/arm/dts/imx6ull-colibri-emmc-nonwifi.dtsi
F: arch/arm/dts/imx6ull-colibri-eval-v3.dts
F: arch/arm/dts/imx6ull-colibri-eval-v3.dtsi
F: arch/arm/dts/imx6ull-colibri-nonwifi.dtsi
F: arch/arm/dts/imx6ull-colibri-u-boot.dtsi
F: board/toradex/colibri-imx6ull/
F: configs/colibri-imx6ull_defconfig

2
configs/colibri-imx6ull-emmc_defconfig
View file

@ -8,7 +8,7 @@ CONFIG_MX6ULL=y
CONFIG_TARGET_COLIBRI_IMX6ULL=y
CONFIG_DM_GPIO=y
CONFIG_TARGET_COLIBRI_IMX6ULL_EMMC=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-colibri-emmc"
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-colibri-emmc-eval-v3"
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x88000000
CONFIG_DISTRO_DEFAULTS=y

2
configs/colibri-imx6ull_defconfig
View file

@ -9,7 +9,7 @@ CONFIG_MX6ULL=y
CONFIG_TARGET_COLIBRI_IMX6ULL=y
CONFIG_DM_GPIO=y
CONFIG_TARGET_COLIBRI_IMX6ULL_NAND=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-colibri"
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-colibri-eval-v3"
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x88000000
CONFIG_DISTRO_DEFAULTS=y