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arm: bcmbca: add bcm63138 SoC support
BCM63138 is an ARM A9 based DSL Broadband SoC. It is part of the BCA (Broadband Carrier Access origin) chipset family so it's added under ARCH_BCMBCA platform. This initial support includes a bare-bone implementation and dts with CPU subsystem, memory, ARM A9 global timer and Broadcom uart. This SoC is supported in the linux-next git repository so the dts and dtsi files are stripped down version of linux copies with mininum blocks needed by u-boot. The u-boot image can be loaded from flash or network to the entry point address in the memory and boot from there to the console. This patch applies on top of the my previous patch [1]. [1] https://lists.denx.de/pipermail/u-boot/2022-August/490570.html Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
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@ -218,6 +218,7 @@ F: arch/arm/mach-bcmbca/
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F: board/broadcom/bcmbca/
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N: bcmbca
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N: bcm[9]?47622
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N: bcm[9]?63138
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N: bcm[9]?63148
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N: bcm[9]?63178
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N: bcm[9]?6756
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@ -1182,6 +1182,8 @@ dtb-$(CONFIG_ARCH_BCMSTB) += bcm7xxx.dtb
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dtb-$(CONFIG_BCM47622) += \
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bcm947622.dtb
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dtb-$(CONFIG_BCM63138) += \
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bcm963138.dtb
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dtb-$(CONFIG_BCM63148) += \
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bcm963148.dtb
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dtb-$(CONFIG_BCM63178) += \
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149
arch/arm/dts/bcm63138.dtsi
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149
arch/arm/dts/bcm63138.dtsi
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@ -0,0 +1,149 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Broadcom BCM63138 DSL SoCs Device Tree
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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compatible = "brcm,bcm63138", "brcm,bcmbca";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0>;
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enable-method = "brcm,bcm63138";
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <1>;
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enable-method = "brcm,bcm63138";
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};
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};
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clocks {
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/* UBUS peripheral clock */
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periph_clk: periph_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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clock-output-names = "periph";
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};
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/* peripheral clock for system timer */
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axi_clk: axi_clk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&armpll>;
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clock-div = <2>;
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clock-mult = <1>;
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};
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/* APB bus clock */
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apb_clk: apb_clk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&armpll>;
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clock-div = <4>;
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clock-mult = <1>;
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};
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};
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/* ARM bus */
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axi@80000000 {
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compatible = "simple-bus";
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ranges = <0 0x80000000 0x784000>;
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#address-cells = <1>;
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#size-cells = <1>;
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L2: cache-controller@1d000 {
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compatible = "arm,pl310-cache";
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reg = <0x1d000 0x1000>;
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cache-unified;
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cache-level = <2>;
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cache-size = <524288>;
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cache-sets = <1024>;
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cache-line-size = <32>;
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interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
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};
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scu: scu@1e000 {
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compatible = "arm,cortex-a9-scu";
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reg = <0x1e000 0x100>;
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};
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gic: interrupt-controller@1f000 {
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compatible = "arm,cortex-a9-gic";
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reg = <0x1f000 0x1000
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0x1e100 0x100>;
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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};
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global_timer: timer@1e200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x1e200 0x20>;
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interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
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clocks = <&axi_clk>;
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};
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local_timer: local-timer@1e600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x1e600 0x20>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_EDGE_RISING)>;
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clocks = <&axi_clk>;
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};
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twd_watchdog: watchdog@1e620 {
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compatible = "arm,cortex-a9-twd-wdt";
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reg = <0x1e620 0x20>;
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interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_HIGH)>;
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};
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armpll: armpll@20000 {
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#clock-cells = <0>;
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compatible = "brcm,bcm63138-armpll";
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clocks = <&periph_clk>;
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reg = <0x20000 0xf00>;
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};
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};
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/* Legacy UBUS base */
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bus@fffe8000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0xfffe8000 0x8000>;
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timer0: timer@80 {
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compatible = "brcm,bcmbca-periph-timer";
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reg = <0x80 0x28>;
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clocks = <&periph_clk>;
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};
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uart0: serial@600 {
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compatible = "brcm,bcm6345-uart";
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reg = <0x600 0x20>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&periph_clk>;
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clock-names = "refclk";
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status = "disabled";
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};
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};
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};
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30
arch/arm/dts/bcm963138.dts
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30
arch/arm/dts/bcm963138.dts
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@ -0,0 +1,30 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2022 Broadcom Ltd.
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*/
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/dts-v1/;
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#include "bcm63138.dtsi"
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/ {
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model = "Broadcom BCM963138 Reference Board";
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compatible = "brcm,bcm963138", "brcm,bcm63138", "brcm,bcmbca";
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aliases {
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x08000000>;
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};
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};
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&uart0 {
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status = "okay";
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};
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@ -12,6 +12,14 @@ config BCM47622
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select DM_SERIAL
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select PL01X_SERIAL
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config BCM63138
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bool "Support for Broadcom 63138 Family"
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select TIMER
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select STI_TIMER
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select CPU_V7A
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select DM_SERIAL
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select BCM6345_SERIAL
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config BCM63148
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bool "Support for Broadcom 63148 Family"
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select SYS_ARCH_TIMER
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@ -48,6 +56,7 @@ config BCM6878
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select PL01X_SERIAL
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source "arch/arm/mach-bcmbca/bcm47622/Kconfig"
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source "arch/arm/mach-bcmbca/bcm63138/Kconfig"
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source "arch/arm/mach-bcmbca/bcm63148/Kconfig"
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source "arch/arm/mach-bcmbca/bcm63178/Kconfig"
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source "arch/arm/mach-bcmbca/bcm6756/Kconfig"
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@ -4,6 +4,7 @@
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#
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obj-$(CONFIG_BCM47622) += bcm47622/
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obj-$(CONFIG_BCM63138) += bcm63138/
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obj-$(CONFIG_BCM63148) += bcm63148/
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obj-$(CONFIG_BCM63178) += bcm63178/
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obj-$(CONFIG_BCM6756) += bcm6756/
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17
arch/arm/mach-bcmbca/bcm63138/Kconfig
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17
arch/arm/mach-bcmbca/bcm63138/Kconfig
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2022 Broadcom Ltd
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#
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if BCM63138
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config TARGET_BCM963138
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bool "Broadcom 63138 Reference Board"
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depends on ARCH_BCMBCA
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config SYS_SOC
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default "bcm63138"
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source "board/broadcom/bcmbca/Kconfig"
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endif
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5
arch/arm/mach-bcmbca/bcm63138/Makefile
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5
arch/arm/mach-bcmbca/bcm63138/Makefile
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2022 Broadcom Ltd
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#
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obj- += dummy.o
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@ -16,6 +16,13 @@ config SYS_CONFIG_NAME
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endif
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if TARGET_BCM963138
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config SYS_CONFIG_NAME
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default "bcm963138"
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endif
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if TARGET_BCM963148
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config SYS_CONFIG_NAME
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22
configs/bcm963138_defconfig
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22
configs/bcm963138_defconfig
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CONFIG_ARM=y
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CONFIG_ARCH_BCMBCA=y
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CONFIG_SYS_TEXT_BASE=0x01000000
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CONFIG_SYS_MALLOC_LEN=0x2000000
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CONFIG_SYS_MALLOC_F_LEN=0x8000
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CONFIG_BCM63138=y
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CONFIG_TARGET_BCM963138=y
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_DEFAULT_DEVICE_TREE="bcm963138"
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CONFIG_IDENT_STRING=" Broadcom BCM63138"
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CONFIG_SYS_LOAD_ADDR=0x01000000
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CONFIG_ENV_VARS_UBOOT_CONFIG=y
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CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
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CONFIG_OF_STDOUT_VIA_ALIAS=y
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CONFIG_DISPLAY_BOARDINFO_LATE=y
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CONFIG_HUSH_PARSER=y
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CONFIG_SYS_MAXARGS=64
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CONFIG_SYS_BOOTM_LEN=0x4000000
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CONFIG_CMD_CACHE=y
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CONFIG_OF_EMBED=y
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CONFIG_CLK=y
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12
include/configs/bcm963138.h
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12
include/configs/bcm963138.h
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2022 Broadcom Ltd.
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*/
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#ifndef __BCM963138_H
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#define __BCM963138_H
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_HZ_CLOCK 500000000
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#endif
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