This converts the VBUS detection and enable logic to GPIO instead of separate
axp functions and checks that have to be used aside usual GPIO functions.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Implemented board_usb_init(), board_usb_cleanup() and
usb_gadget_handle_interrupts() in am43xx board file that
can be invoked by various gadget drivers.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Implemented board_usb_init(), board_usb_cleanup() and
usb_gadget_handle_interrupts() in dra7xx board file that
can be invoked by various gadget drivers.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Added resource_size_t type in order to get rid of the following
compilation error whiel building dwc3 gadget.
include/linux/ioport.h:19:2: error: unknown type name ‘resource_size_t’
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Added dma_free_coherent corresponding to the dma_alloc_coherent in
dma-mapping.h in order to free memory allocated using dma_alloc_coherent.
This API is used in dwc3 driver.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Fixed the following warning here.
"warning: ‘dma_alloc_coherent’ defined but not used" while compiling
udc-core
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Enabled clocks for dwc3 controller and USB PHY present in AM43xx.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Enabled clocks for dwc3 controller and USB PHY present in DRA7.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
When we communicate with the VideoCore to perform property mailbox
transactions, that is a DMA operation as far as the property buffer
is concerned. Use phys_to_bus() on that buffer.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
The BCM283[56] contain both a L1 and L2 cache between the GPU (a/k/a
VideoCore CPU?) and DRAM. DMA-capable peripherals can also optionally
access DRAM via this same L2 cache (although they always bypass the L1
cache). Peripherals select whether to use or bypass the cache via the
top two bits of the bus address.
An IOMMU exists between the ARM CPU and the rest of the system. This
controls whether the ARM CPU's accesses use or bypass the L1 and/or L2
cache. This IOMMU is configured/controlled exclusively by the VideoCore
CPU.
In order for DRAM accesses made by the ARM core to be coherent with
accesses made by other DMA peripherals, we must program a bus address
into those peripherals that causes the peripheral's accesses to use the
same set of caches that the ARM core's accesses will use.
On the RPi1, the VideoCore firmware sets up the IOMMU to enable use of
the L2 cache. This corresponds to addresses based at 0x40000000.
On the RPi2, the VideoCore firmware sets up the IOMMU to disable use of
the L2 cache. This corresponds to addresses based at 0xc0000000.
This patch implements U-Boot's phys_to_bus/bus_to_phys APIs according
to those rules.
For full details of this setup, please see Dom Cobley's description at:
http://lists.denx.de/pipermail/u-boot/2015-March/208201.htmlhttp://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/215038https://www.mail-archive.com/u-boot@lists.denx.de/msg166568.html
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Since commit 79d75d7527 (ARM: move -march=* and -mtune= options to
arch/arm/Makefile), all the Tegra boards are broken because the SPL
is built for ARMv7.
Insert Tegra-specific code to arch/arm/Makefile to set compiler
flags for an earlier ARM architecture.
Note:
The v1 patch for commit 79d75d7527 *was* correct when it was
submitted. Notice it was originally written for multi .config
configuration where Kconfig set CONFIG_CPU_V7/CONFIG_CPU_ARM720T for
Tegra U-Boot Main/SPL, respectively. But, until it was merged into
the mainline, commit e02ee2548a (kconfig: switch to single .config
configuration) had been already applied there.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reported-by: Stephen Warren <swarren@nvidia.com>
Reported-by: Jan Kiszka <jan.kiszka@siemens.com>
Tested-by: Jan Kiszka <jan.kiszka@siemens.com>
Patch e11c6c27 (arm: Allow lr to be saved by board code) introduced
a different method to return from save_boot_params(). The SPL support
for AXP has been pulled and changing to this new method is now
required for SPL to work correctly.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Luka Perkov <luka.perkov@sartura.hr>
While testing "arc: make sure _start is in the beginning of .text
section" I haven't done proper clean-up of built binaries and so missed
another tiny bit that lead to the following error:
--->8---
LD u-boot
arc-linux-ld.bfd: cannot find arch/arc/lib/start.o
Makefile:1107: recipe for target 'u-boot' failed
make: *** [u-boot] Error 1
--->8---
Fix is trivial: put "start.o" in "extra-y".
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
This is important to have entry point in the beginning of .text section
because it allows simple loading and execution of U-Boot.
For example pre-bootloader loads U-Boot in memory starting from offset
0x81000000 and then just jumps to the same address.
Otherwise pre-bootloader would need to find-out where entry-point is. In
its turn if it deals with binary image of U-Boot there's no way for
pre-bootloader to get required value.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Work_92105 from Work Microwave is an LPC3250-
based board with the following features:
- 64MB or 128MB SDR DRAM
- 1 GB SLC NAND, managed through MLC controller.
- Ethernet
- Ethernet + PHY SMSC8710
- I2C:
- EEPROM (24M01-compatible)
- RTC (DS1374-compatible)
- Temperature sensor (DS620)
- DACs (2 x MAX518)
- SPI (through SSP interface)
- Port expander MAX6957
- LCD display (HD44780-compatible), controlled
through the port expander and DACs
This board has SPL support, and uses the LPC32XX boot
image format.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
The controller's Reed-Solomon ECC hardware is
used except of course for raw reads and writes.
It covers in- and out-of-band data together.
The SPL framework is supported.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Add support for Inverse Path USB armory board, an open source
flash-drive sized computer based on Freescale i.MX53 SoC.
http://inversepath.com/usbarmory
Signed-off-by: Andrej Rosano <andrej@inversepath.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Chris Kuethe <chris.kuethe@gmail.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Vagrant Cascadian <vagrant@debian.org>
Tested-By: Vagrant Cascadian <vagrant@debian.org>
Tested-by: Chris Kuethe <chris.kuethe@gmail.com>
Move the MX5 based boards to arch/arm/cpu/armv7/mx5, following the
commit: 89ebc82137
Signed-off-by: Andrej Rosano <andrej@inversepath.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Vagrant Cascadian <vagrant@debian.org>
Tested-by: Chris Kuethe <chris.kuethe@gmail.com>
Back in fc46bae a "clean up" was introduced that intended to reconcile
some of the AM335x codepaths based on how AM43xx operates.
Unfortunately this introduced a regression on the DDR2 platforms. This
was un-noticed on DDR3 (everything except for Beaglebone White) as we
had already populated sdram_config correctly in sequence. This change
brings us back to the older behavior and is fine on all platforms.
Tested on Beaglebone White, Beaglebone Black and AM335x GP EVM
Reported-by: Matt Ranostay <mranostay@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Add backlight enable GPIO, and delay needed for panel powerup
via FIMD DT node.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Now that parade driver supports reading SLP and RST GPIO
from DT, specify the same in parade DT node.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Now that the exynos_fb driver supports handling backlight GPIO
via DT, specify pwm output property via FIMD DT node.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The existing setting for rpll_sdiv generates 70.5Mhz RPLL
video clock to drive 1366x768 panel on peach_pit.
This clock rate is not sufficient to drive 1920x1080 panel on peach-pi.
So, we adjust rpll_sdiv to 3 so that it generates 141Mhz pixel clock
which can drive peach-pi LCD.
This change doesn't break peach-pit LCD since 141/2=70.5Mhz, i.e FIMD
divider at IP level will get set to 1(the required divider setting
will be calculated and set by exynos_fimd_set_clock()) and hence
peach-pit LCD still works fine.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add get_lcd_clk and set_lcd_clk callbacks for Exynos5800 needed by
exynos video driver.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Commit 2e82e92526 'Exynos: Clock: Cleanup
soc_get_periph_rate' introduced a bug in I2C config. This patch makes cros_ec
keyboard working again on Samsung Chromebook (snow).
Changes in V2: reorder lines as requested by Joonyoung Shim.
Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Akshay Saraswat <akshay.s@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Joonyoung Shim <jy0922.shim@samsung.com>
Reviewed-by: Simon Glass <sjg@chroimum.org>
Tested-by: Simon Glass <sjg@chroimum.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
ARCv2 cores may have built-in SLC (System Level Cache, AKA L2-cache).
This change adds functions required for controlling SLC:
* slc_enable/disable
* slc_flush/invalidate
For now we just disable SLC to escape DMA coherency issues until either:
* SLC flush/invalidate is supported in DMA APIin U-Boot
* hardware DMA coherency is implemented (that might be board specific
so probably we'll need to have a separate Kconfig option for
controlling SLC explicitly)
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Now when all infrastructure in ARC is ready for it let's switch ARC UART
to driver model.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
[1] Fix misspeling in ARC_CACHE_LINE_SHIFT dependency, now cache-line
lenth selection is correctly enabled if either I$ or D$ are enabled.
[2] Add dummy entry to target list to make sure target type is always
mentioned in defconfig. Otherwise defconfig for the first target in the
list will not have target name and later on with addition of the new
target on top of the list in Kconfig will lead to corrupted
configuration expanded from defconfig.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
As discussed on mailing list we're drifting away from
CONFIG_SYS_GENERIC_GLOBAL_DATA in favour to use of board_init_f_mem()
for global data.
So do this for ARC architecture.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Intention behind this work was elimination of as much assembly-written
code as it is possible.
In case of ARC we already have relocation fix-up implemented in C so why
don't we use C for U-Boot copying, .bss zeroing etc.
It turned out x86 uses pretty similar approach so we re-used parts of
code in "board_f.c" initially implemented for x86.
Now assembly usage during init is limited to stack- and frame-pointer
setup before and after relocation.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Simon Glass <sjg@chromium.org>
This separation makes maintenance of code easier because those low-level
interrupt- or exception handling routines are pretty static and usually
require not much care while start-up code is a subject of modifications
and enhancements.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Even though ARCompact and ARCv2 are not binary compatible most of
assembly instructions are used in both. With this change we'll get rid
of duplicate code.
Still IVTs are implemented differently so we're keeping them in separate
files.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
always
Make both invalidate_icache_all() and invalidate_dcache_all() available
even if U-Boot is configured with CONFIG_SYS_DCACHE_OFF and/or
CONFIG_SYS_ICACHE_OFF.
This is useful because configuration of U-Boot may not match actual
hardware features. Real board may have cache(s) but for some reason we
may want to run U-Boot with cache(s) disabled (for example if some
peripherals work improperly with existing drivers if data cache is
enabled). So board may start with cache(s) enabled (that's the case for
ARC cores with built-in caches) but early in U-Boot we disable cache(s)
and make sure all contents of data cache gets flushed in RAM.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Supports boot up from NAND flash with software ECC eanbled.
And supports boot up from SD/MMC card with FAT file system.
As the boot from SD/MMC card with FAT file system, the BSS
segment is too big to fit into SRAM, so, use the lds to put
it into SDRAM.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Config MCKR according to the datasheet sequence, or else it
will cause the MCKR configuration failed.
Remove timeout checking for clock configuration, if configure
the clock failed, let the system hang while not run in wrong
clock configuration.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
To facilitate changing lowlevel_init to become s_init, move the current
contents of s_init into board_init_f and add the rest of what
board_init_f does here.
In order to compile clean without CONFIG_SKIP_LOWLEVEL_INIT set, leave an
empty stub of s_init(). It can be removed when lowlevel_init becomes s_init.
Cc: Bo Shen <voice.shen@atmel.com>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Tested-by: Matt Porter <mporter@konsulko.com> on sama5d3_xplained
Signed-off-by: Tom Rini <trini@ti.com>
[rebased on current master, leave s_init() as empty stub]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
The commit 8dfafdd (Introduce common timer functions), add common
timer functions, we can use them directly.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
[rebase on current master]
Sigend-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Even the 8-bit case needs KBCB configured, as pin D7 is located in this
pingroup.
Please note that pingroup ATC seems to come out of reset with its
config set to NAND so one needs to explicitly configure some other
function to this group in order to avoid clashing settings which is
outside the scope of this patch.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Tested-by: Marcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
A while ago I got Russell to change the machine type of our Colibri T20
from COLIBRI_TEGRA2 to COLIBRI_T20 which at least in parts is also
reflected in his machine registry:
http://www.arm.linux.org.uk/developer/machines/list.php?id=3323
For us it is really very beneficial to actually still be able to boot
downstream L4T kernel with its working hardware accelerated
graphics/multimedia stack albeit it being proprietary/closed-source.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
In accordance with our other modules supported by U-Boot and as agreed
upon for Apalis/Colibri T30 get rid of the carrier board in the board/
configuration/device-tree naming.
While at it also bring the prompt more in line with our other products.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This allows selection between CSI and DSI_B on the MIPI pads.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Some pinmux controls are in a different register set. Add support for
manipulating those in a similar way to existing pins/groups.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Move struct pmux_pingrp_desc type and tegra_soc_pingroups variable
declaration together with other pin/mux level definitions. Now the whole
file is grouped/ordered pin/mux-related then drvgrp-related definitions.
Fix typo in ifdef comment.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Patches that added the Tegra210 pinctrl driver and renamed directories
arch/arm/cpu/tegra{$soc}-common -> arch/arm/mach-tegra/tegra-${soc}
crossed. Move the Tegra210 pinctrl driver to the correct location. This
wasn't detected since Tegra210 support is in the process of being added,
and isn't buildable yet.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
make the CPU clock selectable via Kconfig
this removes the sunxi specific CONFIG_CLK_FULL_SPEED defined in each
soc header and replaces it's use in board/sunxi/board.c with
CONFIG_SYS_CLK_FREQ from Kconfig which allows us to configure board
specific frequency on boot
Signed-off-by: Iain Paton <ipaton0@gmail.com>
[hdegoede@redhat.com s/CONFIG_SYS_CLK_FREQ/CONFIG_TIMER_CLK_FREQ/ for the
arch-timer clk speed on sun7i to fix mis-compile on sun7i]
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
clock_set_pll1 would pick the next highest available cpu clock speed if
a value not in the pre defined table was selected. this potentially
results in overclocking the soc.
reverse the selection method so that we select the next lowest speed
and add the missing 912Mhz setting that's requested by sun7i which also
uses the sun4i clock code.
Signed-off-by: Iain Paton <ipaton0@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The usb0 / otg phy on sunxi boards has a bug where it wrongly detects a
high speed squelch on usb reset deassert when a lo speed device is plugged in.
The android kernel has a work around for this in the form of temporary
disabling the phy's squelch detection on reset deassert, this commit adds
the same workaround to the u-boot sunxi musb code, thereby fixing various usb
lo speed devices not working.
Tested with a (before non working) usb keyboard and a usb 2.4 GHz wireless
keyboard/mouse combo receiver.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Now that loading files using semihosting can be done using
a command in standard scripts, and we have rewritten the boardfile
and added it to the Vexpress64, let's delete the external
interface to the semihosting file retrieveal and rely solely
on these commands, and staticize them inside that file so the
whole business is self-contained.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Instead of sprinkling custom code and calls over the Vexpress64
boardfile, create a command that loads images using semihosting
just like we would load from flash memory of over the network,
using a special command:
smhload <image> <address>
This will make it possible to remove some custom calls and
code and make the boot easier.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The semihosting trap call does not like being inlined, probably
because that will mean register reordering screwing up the return
value in r0, so tag this function "noinline".
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Collect CPU specific flags into the single place.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Alison Wang <alison.wang@freescale.com>
Cc: Angelo Dureghello <angelo@sysam.it>
Move the CPU type config options from include/configs/*.h
to arch/m68k/Kconfig and refactor the CPU flags select in
arch/m68k/cpu/mcf547x_8x/config.mk.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Alison Wang <alison.wang@freescale.com>
Cc: Angelo Dureghello <angelo@sysam.it>
Move the CPU type config options from include/configs/M5235EVB.h
to arch/m68k/Kconfig and refactor the CPU flags select in
arch/m68k/cpu/mcf523x/config.mk.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Alison Wang <alison.wang@freescale.com>
Cc: Angelo Dureghello <angelo@sysam.it>
Move the CPU type config options from include/configs/M52277EVB.h
to arch/m68k/Kconfig and refactor the CPU flags select in
arch/m68k/cpu/mcf5227x/config.mk.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Alison Wang <alison.wang@freescale.com>
Cc: Angelo Dureghello <angelo@sysam.it>
This commit intends to stop grepping CPU type in
arch/m68k/cpu/mcf5445x/config.mk.
Move the CPU type config options from include/configs/*.h
to arch/m68k/Kconfig and refactor the CPU flags select in
arch/m68k/cpu/mcf5445x/config.mk.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Alison Wang <alison.wang@freescale.com>
Cc: Angelo Dureghello <angelo@sysam.it>
This commit intends to stop grepping CPU type in
arch/m68k/cpu/mcf532x/config.mk.
Move the CPU type config options from include/configs/*.h
to arch/m68k/Kconfig and refactor the CPU flags select in
arch/m68k/cpu/mcf532x/config.mk.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Alison Wang <alison.wang@freescale.com>
Cc: Angelo Dureghello <angelo@sysam.it>
This commit intends to stop grepping CPU type in
arch/m68k/cpu/mcf530x/config.mk.
Move the CPU type config options from include/configs/amcore.h
to arch/m68k/Kconfig and refactor the CPU flags select in
arch/m68k/cpu/mcf530x/config.mk.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Alison Wang <alison.wang@freescale.com>
Cc: Angelo Dureghello <angelo@sysam.it>
This commit intends to stop grepping CPU type in
arch/m68k/cpu/mcf52x2/config.mk.
Move the CPU type config options from include/configs/*.h
to arch/m68k/Kconfig and refactor the CPU flags select in
arch/m68k/cpu/mcf52x2/config.mk.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Alison Wang <alison.wang@freescale.com>
Cc: Angelo Dureghello <angelo@sysam.it>
BCM2835 (used on Raspberry Pi) and BCM2836 (used on Raspberry Pi 2)
are similar enough. One of the biggest differences is the ARM
processor. It is reasonable to collect the source files into a
single place, arch/arm/mach-bcm283x/.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
This option has a bool type, not hex.
Fix it and enable it if CONFIG_DM is on because Driver Model always
requires malloc memory. Devices are scanned twice, before/after
relocation. CONFIG_SYS_MALLOC_F should be enabled to use malloc
memory before relocation. As it is board-independent, handle it
globally.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Robert Baldyga <r.baldyga@samsung.com>
The default value of CONFIG_SYS_MALLOC_F_LEN is defined by ./Kconfig
as 0x400. Each defconfig or Kconfig need not repeat the same value.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Robert Baldyga <r.baldyga@samsung.com>
All the M68000 boards have switched to Generic Board.
This file is no longer necessary.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Huan Wang <alison.wang@freescale.com>
Cc: Angelo Dureghello <angelo@sysam.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
We have done with the generic board conversion for all the boards
of ARC, Blackfin, M68000, MicroBlaze, MIPS, NIOS2, Sandbox, X86.
Let's select SYS_GENERIC_BOARD for those architectures, so we can
tell which architecture has finished the conversion at a glance.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexey Brodkin <abrodkin@synopsys.com>
Move the option to Kconfig renaming it to CONFIG_HAVE_GENERIC_BOARD.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexey Brodkin <abrodkin@synopsys.com>
My main motivations for this commit are:
[1] Follow the arch/arm/Makefile style of Linux Kernel
[2] Maintain compiler options systematically
Currently, we give -march=* and -mtune=* options inconsistently:
Only some of the CPUs pass -march=* and -mtune=* options.
By collecting such options into the single place arch/arm/Makefile
we can tell which options are missing at a glance.
[3] Prepare for deprecating arch/*/cpu/*/config.mk
Note:
This commit just moves the compiler options so as not to change
the behavior at all. It does not care about the correctness of
the given options. Fox example, "-march=armv5te" might be better
than "-march=armv4" for ARM946EJS, but it is beyond the scope this
commit. Also, filling the missing -march=* and -tune=* is left
to follow-up patches.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
Allocate memory space for pre-allocation malloc and zero global data.
This code is partly from crt0.S.
Signed-off-by: David Feng <fenghua@phytium.com.cn>
Intel Quark SoC integrates two 10/100 ethernet controllers which can
be connected to an external RMII PHY. The MAC IP is from Designware.
Enable this support with the existing U-Boot Designware MAC driver
so that the ethernet port on Intel Galileo board can be used.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Using __DATE__ and __TIME__ results in an error due to -Werror=date-time
with gcc-4.9 (__DATE__ / __TIME__ might prevent reproducible builds) so
switch these over to U_BOOT_DATE / U_BOOT_TIME
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Simon Glass <sjg@chromium.org>
This patch cleans up the quark MRC codes coding style by:
- Remove BIT0/1../31 defines from mrc_util.h
- Create names for the documented BITs and use them
- For undocumented single BITs, use (1 << n) directly
- For undocumented ORed BITs, use the hex number directly
- Remove redundancy parenthesis all over the codes
- Replace to use lower case hex numbers
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Various files are needlessly rebuilt every time due to the version and
build time changing. As version.h is not actually needed, remove the
include.
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Macpaul Lin <macpaul@andestech.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: York Sun <yorksun@freescale.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Philippe Reynes <tremyfr@yahoo.fr>
Cc: Eric Jarrige <eric.jarrige@armadeus.org>
Cc: "David Müller" <d.mueller@elsoft.ch>
Cc: Phil Edworthy <phil.edworthy@renesas.com>
Cc: Robert Baldyga <r.baldyga@samsung.com>
Cc: Torsten Koschorrek <koschorrek@synertronixx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Łukasz Majewski <l.majewski@samsung.com>
The callee (arch/arm/lib/cache-cp15.c) has a #ifdef
CONFIG_SYS_DCACHE_OFF conditional. The same conditional in the
caller (arch/arm/mach-uniphier/cache_uniphier.c) is redundant.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The L2 cache is used as a temporary SRAM on SPL.
Now the secondary CPUs store the necessary code for jumping to
Linux on their L1 I-caches. So, the L2 cache can be disabled
much earlier, at the very entry of U-Boot proper (lowlevel_init).
This makes the boot sequence clearer.
Also, as the L1 cache has been disabled by the start.S,
enable_caches() does not need to do it again.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Currently, the secondary CPU(s) are kicked three times:
Boot ROM ---(kick)--> SPL ---(kick)--> U-boot ---(kick)--> Linux.
It makes the boot sequence very complicated.
This commit merges the first and the second kicks, so the secondary
CPU(s) can directly jump from SPL to Linux.
arch/arm/mach-uniphier/smp.S is no longer necessary.
Linux boot test passed.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
To remove the ifdef conditional of CONFIG_SKIP_LOWLEVEL_INIT,
add late_lowlevel_init.S to U-Boot proper.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Ifdef conditionals for CONFIG options are not Kconfig-friendly.
Instead, define CONFIG_SPL_STACK to prepare for Kconfig moves.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Enable CONFIG_SPL_DM and CONFIG_SPL_SERIAL_SUPPORT, which provide
Driver Model UART support on SPL.
CONFIG_SYS_SPL_MALLOC_{START,SIZE} should be dropped because simple
malloc is preferred on SPL. Dlmalloc requires some static variables
on .data section that is not available yet for NOR boot mode etc.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The UniPhier platform is going to enable Driver Model and UART
support on SPL. Move UART pin settings to early_pin_init(),
which is called from SPL.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Since we do not have OF_CONTROL support for SPL, platform devices
are necessary to enable Driver Model on SPL.
To prepare for that, move platdevice.o to SPL and enable it by
CONFIG_SPL_DM.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The two Makefiles arch/arm/mach-uniphier/{ph1-ld4,ph1-sld8}/Makefile
are completely the same. We can improve the maintainability by
having one to include the other.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Since commit a86ac9540e (ARM: UniPhier: include <mach/*.h> instead
of <asm/arch/*.h>), UniPhier platform does not need the symbolic
link arch/arm/include/asm. This option is not necessary either.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Add basic SECO MX6Q/uQ7 board support (Ethernet, UART, SD are supported).
It also adds a Kconfig skeleton to later add more SECO board (supporting
SoC and board variants).
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
IMX_CONFIG is currently passed via the SYS_EXTRA_OPTIONS which is marked
as deprecated.
Add a new Kconfig file under arch/arm/imx-common and define the
IMX_CONFIG Kconfig in there.
Each board is supposed to provide a default value pointing to the
appropriate imximage.cfg file.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Freescale boards are currently all defined in arch/arm/Kconfig, which
makes them hard to detect.
Moreover the MX6 SoC variant (Q, D, DL, S, SL) selection is currently
done via the SYS_EXTRA_OPTIONS option which marked as deprecated.
Move to a more standard way to select sub-architecture and board by
creating a Kconfig under arch/arm/cpu/armv7/mx6 and a new ARCH_MX6
option.
Existing MX6 board definitions should be moved in this new Kconfig in
choice menu, and new boards should be directly declared in this menu.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
As the u-boot-spl.lds is used only for armv7 SoCs (includes
sama5d3 and sama5d4), so move it to armv7 directory.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
This patch enable the MCI support for at91sam9rlek board.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
[rebase on ToT]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Larry Johnson <lrj@acm.org>
This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Eric Millbrandt <emillbrandt@dekaresearch.com>
They have not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Erik Theisen <etheisen@mindspring.com>
They have not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Stephen Williams <steve@icarus.com>
This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Panasonic's System LSI products, UniPhier SoC family, have been
transferred to Socionext Inc.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
RX51 has a secure logic which uses different parameters compared to
traditional implementation. So, make the generic secure acr write
over-ride-able by board file and refactor rx51 code to use this.
While at it, enable the OMAP3 specific errata code for 454179, 430973,
621766.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Enable the OMAP3 specific errata code for 454179, 430973, 621766
and while at it, remove legacy non-revision checked errata logic.
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Update to existing recommendation for L2ACTLR configuration to prevent
system instability and optimize performance.
These apply to both OMAP5 and DRA7.
Reported-by: Vivek Chengalvala <vchengalvala@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This patch enables the workaround for ARM errata 798870 for OMAP5 /
DRA7 which says "If back-to-back speculative cache line fills (fill
A and fill B) are issued from the L1 data cache of a CPU to the
L2 cache, the second request (fill B) is then cancelled, and the
second request would have detected a hazard against a recent write or
eviction (write B) to the same cache line as fill B then the L2 logic
might deadlock."
An l2auxctlr accessor implementation for OMAP5 and DRA7 is introduced
here as well.
Signed-off-by: Praveen Rao <prao@ti.com>
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
omap_smc1 is now generic enough to remove duplicate
omap3_gp_romcode_call logic that omap3 introduced.
As part of this change, move to using the generic lowlevel_init.S for
omap3 as well.
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This is in preperation of using generic cross OMAP code.
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup
PL310 control register, however, that is something that is generic
enough to be used for OMAP5 generation of processors as well. The only
difference being the service being invoked for the function.
So, convert the service to a macro and use a generic name (same as
that used in Linux for some consistency). While at that, also add a
data barrier which is necessary as per recommendation.
While at this, smc #0 is maintained as handcoded assembly thanks to
various gcc version eccentricities, discussion thread:
http://marc.info/?t=142542166800001&r=1&w=2
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
621766: Under a specific set of conditions, executing a sequence of
NEON or vfp load instructions can cause processor deadlock
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set L1NEON to 1
Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
430973: Stale prediction on replaced inter working branch causes
Cortex-A8 to execute in the wrong ARM/Thumb state
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set IBE to 1
Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
454179: Stale prediction may inhibit target address misprediction on
next predicted taken branch
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set IBE and disable branch size mispredict to 1
Also provide a hook for SoC specific handling to take place if needed.
Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add workaround for Cortex-A15 ARM erratum 798870 which says
"If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second request would have
detected a hazard against a recent write or eviction (write B) to the
same cache line as fill B then the L2 logic might deadlock."
Implementations for SoC families such as Exynos, OMAP5/DRA7 etc
will be widely different.
Every SoC has slightly different manner of setting up access to L2ACLR
and similar registers since the Secure Monitor handling of Secure
Monitor Call(smc) is diverse. Hence an weak function is introduced
which may be overriden to implement SoC specific accessor implementation.
Based on ARM errata Document revision 18.0 (22 Nov 2013)
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Disable the warm reset and enable the cold reset for a more reliable
restart ('reset'). This is taken from the Linux kernel, see imx_src_init()
in arch/arm/mach-imx/src.c.
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
While the Freescale ARMv8 board LS2085A will enter U-Boot both
on a master and a secondary (slave) CPU, this is not the common
behaviour on ARMv8 platforms. The norm is that U-Boot is entered
from the master CPU only, while the other CPUs are kept in
WFI (wait for interrupt) state.
The code determining which CPU we are running on is using the
MPIDR register, but the definition of that register varies with
platform to some extent, and handling multi-cluster platforms
(such as the Juno) will become cumbersome. It is better to only
enable the multiple entry code on machines that actually need
it and disable it by default.
Make the single entry default and add a special
ARMV8_MULTIENTRY KConfig option to be used by the
platforms that need multientry and set it for the LS2085A.
Delete all use of the CPU_RELEASE_ADDR from the Vexpress64
boards as it is just totally unused and misleading, and
make it conditional in the generic start.S code.
This makes the Juno platform start U-Boot properly.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The way the PSCI DT update happens currently means we pull in
<asm/armv7.h> everywhere, including on ARMv8 and that in turn brings in
<asm/io.h> for some non-PSCI related things that header needs to deal
with.
To fix this, we rework the hook slightly. A good portion of
arch/arm/cpu/armv7/virt-dt.c is common looking and I hope that when PSCI
is needed on ARMv8 we can re-use this by and large. So rename the
current hook to psci_update_dt(), move the prototype to <asm/psci.h> and
add an #ifdef that will make re-use later easier.
Reported-by: York Sun <yorksun@freescale.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: York Sun <yorksun@freescale.com>
For ARM architecture, enable the CONFIG_USE_ARCH_MEMSET/MEMCPY,
will highly increase the memset/memcpy performance. This is able
thanks to the ARM multiple register instructions.
Unfortunatelly the relocation is done without the cache enabled,
so it takes some time, but zeroing the BSS memory takes much more
longer, especially for the configs with big static buffers.
A quick test confirms, that the boot time improvement after using
the arch memcpy for relocation has no significant meaning.
The same test confirms that enable the memset for zeroing BSS,
reduces the boot time.
So this patch enables the arch memset for zeroing the BSS after
the relocation process. For ARM boards, this can be enabled
in board configs by defining: 'CONFIG_USE_ARCH_MEMSET'.
This was tested on Trats2.
A quick test with trace. Boot time from start to main_loop() entry:
- ~1384ms - before this change
- ~888ms - after this change
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@konsulko.com>
For some assemblers, they use another character as newline in a macro
(e.g. arc uses '`'), so for generic assembly code, need use ASM_NL (a
macro) instead of ';' for it.
Basically this is the same patch as applied to Linux kernel -
http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/include/linux/linkage.h?id=9df62f054406992ce41ec4558fca6a0fa56fffeb
but modified a bit to fit in U-Boot.
Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@ti.com>
The 'nandecc sw' command selects a software-based error correction
algorithm. By default, this is OMAP_ECC_HAM1_CODE_SW but some
platforms use OMAP_ECC_BCH8_CODE_HW_DETECTION_SW as their
software-based correction algorithm. Allow a user to be specific e.g.
# nandecc sw <hamming|bch8>
where 'hamming' is still the default.
Note: we don't just use CONFIG_NAND_OMAP_ECCSCHEME as it might be set
to a hardware-based ECC scheme---a little strange when the user
has requested 'sw' ECC.
Signed-off-by: Ash Charles <ashcharles@gmail.com>
This patch extends OMAP3 support for AM/DM37xx and
introduces the AM3703-based Quipos Cairo board.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Reviewed-by: Simon Glass <sjg@chromium.org>
esbc_validate command uses various IP Blocks: Security Monitor, CAAM block
and SFP registers. Hence the respective CONFIG's are enabled.
Apart from these CONFIG_SHA_PROG_HW_ACCEL and CONFIG_RSA are also enabled.
Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Freescale sfp has been used for mpc8xxx. It will be used
for ARM-based SoC as well. This patch moves the CCSR defintion of
sfp_regs to common include. This patch also defines ccsr_sfp_regs
definition for newer versions of SFP.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
According to table 2-3 on page 87 of Marvell's latest PXA270
Specification Update Rev. I from 2010.04.19 [1] there exists a breed of
chips with a new CPU ID for PXA270M A1 stepping which our latest
Colibri PXA270 V2.4A modules actually have assembled. This patch helps
in correctly identifying those chips upon boot as well which then looks
as follows:
CPU: Marvell PXA27xM rev. A1
[1] http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_spec_update.pdf
Acked-by: Marek Vasut <marex@denx.de>
commit d9f43c8f5c sets
get_reset_cause() as static, but this conflicts with mx5
where its prototype is in sys_proto.h.
Drop it from sys_proto.h and drop print_cpuinfo from mx53_loco,
factorizing the call for this board.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Jason Liu <jason.hui@linaro.org>
Import DTS for Arria V development kit and enable support
for DT. The DT is imported from Linux 3.19-rc1 as of commit
97bf6af1f928216fd6c5a66e8a57bfa95a659672 .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
Import DTS for Cyclone V development kit and enable support
for DT. The DT is imported from Linux 3.19-rc1 as of commit
97bf6af1f928216fd6c5a66e8a57bfa95a659672 .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
Add support for the Altera Arria V development kit.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
Currently in some cases SDRAM init requires global_data to be available
and soon this will not be available prior to board_init_f(). Adjust the
code paths in these cases to be correct. In some cases we had the SPL
stack be in DDR as we might have large stacks (due to Falcon Mode +
Environment). In these cases switch to CONFIG_SPL_STACK_R. In other
cases we had simply been setting CONFIG_SPL_STACK into SRAM. In these
cases we no longer need to (CONFIG_SYS_INIT_SP_ADDR is used and is also
in SRAM) so drop those lines.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested on Beagleboard, Beagleboard xM
Tested-by: Matt Porter <mporter@konsulko.com>
Tested on Beaglebone Black, AM43xx GP EVM, OMAP5 uEVM, OMAP4 Pandaboard
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
At present SPL uses a single stack, either CONFIG_SPL_STACK or
CONFIG_SYS_INIT_SP_ADDR. Since some SPL features (such as MMC and
environment) require a lot of stack, some boards set CONFIG_SPL_STACK to
point into SDRAM. They then set up SDRAM very early, before board_init_f(),
so that the larger stack can be used.
This is an abuse of lowlevel_init(). That function should only be used for
essential start-up code which cannot be delayed. An example of a valid use is
when only part of the SPL code is visible/executable, and the SoC must be set
up so that board_init_f() can be reached. It should not be used for SDRAM
init, console init, etc.
Add a CONFIG_SPL_STACK_R option, which allows the stack to be moved to a new
address before board_init_r() is called in SPL.
The expected SPL flow (for CONFIG_SPL_FRAMEWORK) is documented in the README.
Signed-off-by: Simon Glass <sjg@chromium.org>
For version 1:
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Heiko Schocher <hs@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Use the full driver model GPIO and serial drivers in SPL now that these are
supported. Since device tree is not available they will use platform data.
Remove the special SPL GPIO function as it is no longer needed.
This is all in one commit to maintain bisectability.
Signed-off-by: Simon Glass <sjg@chromium.org>
This is already set up in crt0.S. We don't need a new structure and don't
really want one in the 'data' section of the image, since it will be empty
and crt0.S's changes will be ignored.
As an interim measure, remove it only if CONFIG_DM is not defined. This
allows us to press ahead with driver model in SPL and allow the stragglers
to catch up.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function has grown into something of a monster. Some boards are setting
up a console and DRAM here in SPL. This requires global_data which should be
set up in one place (crt0.S).
There is no need for SPL to use s_init() for anything since board_init_f()
is called immediately afterwards.
Signed-off-by: Simon Glass <sjg@chromium.org>
Modify CONFIG_USB_MAX_CONTROLLER_COUNT value to 1 on P1022DS.
As ETSEC2 and USB2 are muxed; thus if ETSEC2 is enabled, the
system bus hangs on USB2 if ETSEC2 is enabled but "usb start"
command is issued. Hence making default controller count to 1
to avoid system hang.
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: Yusong Sun <yorksun@freescale.com>
The code provides framework for heterogeneous multicore chips based on StarCore
and Power Architecture which are chasis-2 compliant, like B4860 and B4420
It will make u-boot recognize all non-ppc cores and peripherals like
SC3900/DSP CPUs, MAPLE, CPRI and print their configuration in u-boot logs.
Example boot logs of B4860QDS:
U-Boot 2015.01-00232-geef6e36-dirty (Jan 19 2015 - 11:58:45)
CPU0: B4860E, Version: 2.2, (0x86880022)
Core: e6500, Version: 2.0, (0x80400120)
Clock Configuration:
CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz,
DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz,
DSP CPU4:1200 MHz, DSP CPU5:1200 MHz,
CCB:666.667 MHz,
DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz
CPRI:600 MHz
MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz
FMAN1: 666.667 MHz
QMAN: 333.333 MHz
Top level changes include:
(1) Top level CONFIG to identify HETEROGENUOUS clusters
(2) CONFIGS for SC3900/DSP components
(3) Global structures like "cpu_type" and "MPC85xx_SYS_INFO"
updated for dsp cores and other components
(3) APIs to get DSP num cores and their Mask like:
cpu_dsp_mask, cpu_num_dspcores etc same as that of PowerPC
(5) Code to fetch and print SC cores and other heterogenous
device's frequencies
(6) README added for the same
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This fixes the MMC/SD card detect GPIOs for Apalis T30 which got broken
by the following commit:
2b2b50bc87 "dm: tegra: dts: Use TEGRA_GPIO() macro for all GPIOs"
While at it also re-add the comments describing which particular
Apalis/Colibri pins those GPIOs are on.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
All boards with a SPI interface have a suitable spi alias except Apalis
T30. Add these missing aliases just as the following commit did for the
others:
d2f60f9332 "dm: tegra: dts: Add aliases for spi on tegra30 boards"
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This patch incorporates a few fixes from Tom Warren <twarren@nvidia.com>.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Tegra210 has a per-pin option named e_io_hv, which indicates that the
pin's input path should be configured to be 3.3v-tolerant. Add support
for this.
Note that this is very similar to previous chip's rcv_sel option.
However, since the Tegra TRM names this option differently for the
different chips, we support the new name so that the code exactly matches
the naming in the TRM, to avoid confusion.
This patch incorporates a few fixes from Tom Warren <twarren@nvidia.com>.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Tegra210 starts its drive group registers at a different offset from the
APB MISC register block that other SoCs. Update the code to handle this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
T210 support HSM and Schmitt options in the pinmux register (previous
chips placed these options in the drive group register). Update the
code to handle this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Tegra210 moves some bits around in the pinmux registers. Update the code
to handle this.
This doesn't attempt to address the issues with the group-to-group varying
drive group register layout mentioned earlier. This patch handles the
SoC-to-SoC differences in the mux register layout.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
On some future SoCs, some per-drive-group features became per-pin
features. Move all type definitions early in the header so they can
be enabled irrespective of the setting of TEGRA_PMX_SOC_HAS_DRVGRPS.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
On some future SoCs, some of the per-drive-group features no longer
exist. Add some ifdefs to support this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Future SoCs have a slightly different combination of pinmux options per
pin. This will be simpler to handle if we simply have one define per
option, rather than grouping various options together, in combinations
that don't align with future chips.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Tegra's drive group registers have a remarkably inconsistent layout. The
current U-Boot driver doesn't take this into account at all. Add a
comment to describe the issue, so at least anyone debugging the driver
will be aware of this. To solve this, we'd need to add a per-drive-group
data structure describing the layout for the individual register. Since
we don't set up too many drive groups in U-Boot at present, this
hopefully isn't causing too much practical issue. Still, we probably need
to fix this sometime.
Wth Tegra210, the register layout becomes almost entirely consistent, so
this problem partially solves itself over time.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This is needed to correctly apply the new Jetson TK1 pinmux config.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
When the CPU is in non-secure (NS) mode (when running U-Boot under a
secure monitor), certain actions cannot be taken, since they would need
to write to secure-only registers. One example is configuring the ARM
architectural timer's CNTFRQ register.
We could support this in one of two ways:
1) Compile twice, once for secure mode (in which case anything goes) and
once for non-secure mode (in which case certain actions are disabled).
This complicates things, since everyone needs to keep track of
different U-Boot binaries for different situations.
2) Detect NS mode at run-time, and optionally skip any impossible actions.
This has the advantage of a single U-Boot binary working in all cases.
(2) is not possible on ARM in general, since there's no architectural way
to detect secure-vs-non-secure. However, there is a Tegra-specific way to
detect this.
This patches uses that feature to detect secure vs. NS mode on Tegra, and
uses that to:
* Skip the ARM arch timer initialization.
* Set/clear an environment variable so that boot scripts can take
different action depending on which mode the CPU is in. This might be
something like:
if CPU is secure:
load secure monitor code into RAM.
boot secure monitor.
secure monitor will restart (a new copy of) U-Boot in NS mode.
else:
execute normal boot process
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Some systems have so much RAM that the end of RAM is beyond 4GB. An
example would be a Tegra124 system (where RAM starts at 2GB physical)
that has more than 2GB of RAM.
In this case, we want gd->ram_size to represent the actual RAM size, so
that the actual RAM size is passed to the OS. This is useful if the OS
implements LPAE, and can actually use the "extra" RAM.
However, we can't use get_ram_size() to verify the actual amount of RAM
present on such systems, since some of the RAM can't be accesses, which
confuses that function. Avoid calling get_ram_size() when the RAM size
is too large for it to work correctly. It's never actually needed anyway,
since there's no reason for the BCT to report the wrong RAM size.
In systems with >=4GB RAM, we still need to clip the reported RAM size
since U-Boot uses a 32-bit variable to represent the RAM size in bytes.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
size_mb is used to hold a value that's sometimes KB, sometimes MB,
and sometimes bytes. Use separate correctly named variables to avoid
confusion here. Also fix indentation of a conditional statement.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add basic Xilinx ZynqMP arm64 support.
Serial and SD is supported.
It supports emulation platfrom ep108 and QEMU.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
With a389531 we now call readl() from this file so add <asm/io.h> so
that we have a prototype for the function.
Signed-off-by: Tom Rini <trini@konsulko.com>
Freescale's SEC block has built-in Data Encryption
Key(DEK) Blob Protocol which provides a method for
protecting a DEK for non-secure memory storage.
SEC block protects data in a data structure called
a Secret Key Blob, which provides both confidentiality
and integrity protection.
Every time the blob encapsulation is executed,
a AES-256 key is randomly generated to encrypt the DEK.
This key is encrypted with the OTP Secret key
from SoC. The resulting blob consists of the encrypted
AES-256 key, the encrypted DEK, and a 16-bit MAC.
During decapsulation, the reverse process is performed
to get back the original DEK. A caveat to the blob
decapsulation process, is that the DEK is decrypted
in secure-memory and can only be read by FSL SEC HW.
The DEK is used to decrypt data during encrypted boot.
Commands added
--------------
dek_blob - encapsulating DEK as a cryptgraphic blob
Commands Syntax
---------------
dek_blob src dst len
Encapsulate and create blob of a len-bits DEK at
address src and store the result at address dst.
Signed-off-by: Raul Cardenas <Ulises.Cardenas@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Signed-off-by: Ulises Cardenas <ulises.cardenas@freescale.com>
Signed-off-by: Ulises Cardenas-B45798 <Ulises.Cardenas@freescale.com>
Since commit 3ff46cc42b ("arm: relocate the exception vectors") mx35
does not boot anymore.
Add a specific relocate_vectors macro that skips the vector relocation, as the
i.MX35 SoC does not provide RAM at the high vectors address (0xFFFF0000), and
(0x00000000) maps to ROM.
This allows mx35 to boot again.
Cc: Sebastian Priebe <sebastian.priebe@cadcon.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Since commit 3ff46cc42b ("arm: relocate the exception vectors") mx31
does not boot anymore.
Add a specific relocate_vectors macro that skips the vector relocation, as the
i.MX31 SoC does not provide RAM at the high vectors address (0xFFFF0000), and
(0x00000000) maps to ROM.
This allows mx31 to boot again.
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Magnus Lilja <lilja.magnus@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
If CONFIG_ARMV7_PSCI is not defined and CONFIG_ARMV7_SECURE_BASE is defined,
smp_kicl_all_cpus may enable secondary cores and runs into secure_ram_addr(
_smp_pen), before code is relocated to secure ram.
So need relocation to secure ram before enable secondary cores.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Each way of the system cache has 256 entries for PH1-Pro4 and older
SoCs, whereas 512 entries for PH1-Pro5 and newer SoCs. The line
size is still 128 byte. Thus, the way size is 32KB/64KB for old/new
SoCs.
To keep lowlevel_init SoC-independent, set BOOT_RAM_SIZE to the
constant value 32KB. It is large enough for temporary RAM and
should work for all the SoCs of UniPhier family.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This function was intended for MN2WS0235 (what we call PH1-Pro4TV).
On that SoC, MPLL is already running on the power-on reset and it
makes sense to stop the PLL at early boot-up.
On the other hand, PH1-Pro4(R) does not have SC_MPLLOSCCTL register,
so this function has no point.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This code is duplicated in ph1-ld4/sg_init.c and ph1-pro4/sg_init.c.
Merge the same code into a new file, memconf.c.
The helper functions no longer have to be placed in the header file.
Also, move them into memconf.c.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Two support card variants are used with UniPhier reference boards:
- 1 chip select support card (original CPLD)
- 3 chip selects support card (ARIMA-compatible CPLD)
Currently, the former is only supported on PH1-Pro4, but it can be
expanded to PH1-LD4, PH1-sLD8 with a little code change.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Each USB port corresponds to the following IP core:
port0: xHCI (0x65a00000) SS+HS
port1: xHCI (0x65c00000) HS (SS PHY is not implemented)
port2: EHCI (0x5a800100) HS
port3: EHCI (0x5a810100) HS
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
EHCI host controllers have a common register interface.
We may wish to implement a generic EHCI driver someday.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Because uniphier_ehci_reset() is only called from ehci-uniphier.c,
it can be a static function there.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Marek Vasut <marex@denx.de>
Now UniPhier platform highly depends on Device Tree configuration
(CONFIG_OF_CONTROL is select'ed by Kconfig). Since the EHCI is only
used on main U-Boot, we can drop platform devices of the EHCI
controllers. We still keep UART platform devices because they might
be useful for SPL.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Marek Vasut <marex@denx.de>
Deassert the reset signal and provide the clock for STDMAC core.
This is necessary for the USB 2.0 host controllers.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
For all the UniPhier SoCs so far, the reset signal of the NAND core
is automatically deasserted after the PLL gets stabled.
(The bit 2 of SC_RSTCTRL is default to one.)
This causes a fatal problem on the NAND controller of PH1-LD4.
For that SoC, the NAND I/O pins are not set up yet at the power-on
reset except the NAND boot mode. As a result, the NAND controller
begins automatic device scanning with wrong I/O pins and finally
hangs up.
Actually, U-Boot dies after printing "NAND:" on the console unless
the boot mode latch detected the NAND boot mode.
To work around this problem, reset the NAND core in SPL for non-NAND
boot modes. If CONFIG_NAND_DENALI is enabled, the reset signal is
deasserted again in U-Boot proper. At this time, I/O pins have been
correctly set up, the device scanning should succeed.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Split the current clkrst_init() into two functions:
- early_clkrst_init(): called from SPL
Deassert the reset signals of the memory controller and some other
basic cores.
- clkrst_init(): called from main U-boot
Deassert the reset signals that are necessary for the access to
peripherals etc.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Now UniPhier SoCs only work with CONFIG_SPL and the function
sbc_init() is called from SPL.
The conditional #if !defined(CONFIG_SPL_BUILD) has no point
any more.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Since commit 0e7368c6c4 (kbuild: prepare for moving headers into
mach-*/include/mach), we can replace #include <asm/arch/*.h> with
<mach/*.h> so we do not need to create the symbolic link during the
build.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
It was found that the L2 cache timings that we had before could cause
freezes and hangs. We should make things more robust with better
timings. Currently the production ChromeOS kernel applies these
timings, but it's nice to fixup firmware too (and upstream probably
won't take our kernel hacks).
This also provides a big cleanup of the L2 cache init code avoiding
some duplication. The way things used to work:
* low_power_start() was installed by the SPL (both at boot and resume
time) and left resident in iRAM for the kernel to use when bringing
up additional CPUs. It used configure_l2_ctlr() and
configure_l2_actlr() when it detected it was on an A15. This was
needed (despite the L2 cache registers being shared among all A15s)
because we might have been the first man in after the whole A15
cluster was shutdown.
* secondary_cores_configure() was called on at boot time and at resume
time. Strangely this called configure_l2_ctlr() but not
configure_l2_actlr() which was almost certainly wrong. Given that
we'll call both (see next bullet) later in the boot process it
didn't matter for normal boot, but I guess this is how L2 cache
settings got set on 5420/5800 (but not 5250?) at resume time.
* exynos5_set_l2cache_params() was called as part of cache enablement.
This should happen at boot time (normally in the SPL except for USB
boot where it happens in main U-Boot).
Note that the old code wasn't setting ECC/parity in the cache
enablement code but we happened to get it anyway because we'd call
secondary_cores_configure() at boot time. For resume time we'd get it
anyway when the 2nd A15 core came up.
Let's make this a whole lot simpler. Now we always set these
parameters in the same place for all boots and use the same code for
setting up secondary CPUs.
Intended net effects of this change (other than cleanup):
* Timings go from before:
data: 0 cycle setup, 3 cycles (0x2) latency
tag: 0 cycle setup, 3 cycles (0x2) latency
after:
data: 1 cycle setup, 4 cycles (0x3) latency
tag: 1 cycle setup, 4 cycles (0x3) latency
* L2ACTLR is properly initted on 5420/5800 in all cases.
One note is that we're still relying on luck to keep low_power_start()
working. The compiler is being nice and not storing anything on the
stack.
Another note is that on its own this patch won't help to fix cache
settings in an RW U-Boot update where we still have the RO SPL. The
plan for that is:
* Have RW U-Boot re-init the cache right before calling the kernel
(after it has turned the L2 cache off). This is why the functions
are in a header file instead of lowlevel_init.c.
* Have the kernel save the L2 cache settings of the boot CPU and apply
them to all other CPUs. We get a little lucky here because the old
code was using "|=" to modify the registers and all of the bits that
it's setting are also present in the new settings (!). That means
that when the 2nd CPU in the A15 cluster comes up it doesn't
actually mess up the settings of the 1st CPU in the A15 cluster. An
alternative option is to have the kernel write its own
low_power_start() code.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
On warm reset, all cores jump to the low_power_start function because iRAM
data is retained and because while executing iROM code all cores find
the jump flag 0x02020028 set. In low_power_start, cores check the reset
status and if true they clear the jump flag and jump back to 0x0.
The A7 cores do jump to 0x0 but consider following instructions as a Thumb
instructions which in turn makes them loop inside the iROM code instead of
jumping to power_down_core.
This issue is fixed by replacing the "mov pc" instruction with a "bx"
instruction which switches state along with the jump to make the execution
unit consider the branch target as an ARM instruction.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
When compiled SPL for Thumb secondary cores failed to boot
at the kernel boot up. Only one core came up out of 4.
This was happening because the code relocated to the
address 0x02073000 by the primary core was an ARM asm
code which was executed by the secondary cores as if it
was a thumb code.
This patch fixes the issue of secondary cores considering
relocated code as Thumb instructions and not ARM instructions
by jumping to the relocated with the help of "bx" ARM instruction.
"bx" instruction changes the 5th bit of CPSR which allows
execution unit to consider the following instructions as ARM
instructions.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch does 3 things:
1. Enables ECC by setting 21st bit of L2CTLR.
2. Restore data and tag RAM latencies to 3 cycles because iROM sets
0x3000400 L2CTLR value during switching.
3. Disable clean/evict push to external by setting 3rd bit of L2ACTLR.
We need to restore this here due to switching.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
L2 Auxiliary Control Register provides configuration
and control options for the L2 memory system. Bit 3
of L2ACTLR stands for clean/evict push to external.
Setting bit 3 disables clean/evict which is what
this patch intends to do.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
iROM logic provides undesired jump address for CPU2.
This patch adds a programmable susbstitute for a part of
iROM logic which wakes up cores and provides jump addresses.
This patch creates a logic to make all secondary cores jump
to a particular address which evades the possibility of CPU2
jumping to wrong address and create undesired results.
Logic of the workaround:
Step-1: iROM code checks value at address 0x2020028.
Step-2: If value is 0xc9cfcfcf, it jumps to the address (0x202000+CPUid*4),
else, it continues executing normally.
Step-3: Primary core puts secondary cores in WFE and store 0xc9cfcfcf in
0x2020028 and jump address (pointer to function low_power_start)
in (0x202000+CPUid*4).
Step-4: When secondary cores recieve event signal they jump to this address
and continue execution.
Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds workaround for the ARM errata 799270 which says
"If the L2 cache logic clock is stopped because of L2 inactivity,
setting or clearing the ACTLR.SMP bit might not be effective. The bit is
modified in the ACTLR, meaning a read of the register returns the
updated value. However the logic that uses that bit retains the previous
value."
Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds workaround for ARM errata 798870 which says
"If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second request would have
detected a hazard against a recent write or eviction (write B) to the
same cache line as fill B then the L2 logic might deadlock."
Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds code to shutdown secondary cores.
When U-boot comes up, all secondary cores appear powered on,
which is undesirable and causes side effects while
initializing these cores in kernel.
Secondary core power down happens in following steps:
Step-1: After Exynos power-on, primary core starts executing first.
Step-2: In iROM code every core has to check 2 flags i.e.
addresses 0x02020028 & 0x02020004.
Step-3: Initially 0x02020028 is 0 for all cores and 0x02020004 has a
jump address for primary core and 0 for all secondary cores.
Step-4: Therefore, primary core follows normal iROM execution and jumps
to BL1 eventually, whereas all secondary cores enter WFE.
Step-5: When primary core comes into function secondary_cores_configure,
it puts pointer to function power_down_core into 0x02020004
and provides DSB and SEV for all cores so that they may come out
of WFE and jump to power_down_core function.
Step-6: And ultimately because of power_down_core all
secondary cores shut-down.
Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
ED Mini V2 is based on Orion 5x which boots at fixed
address 0xFFFF0000 in NOR Flash. Place SPL there, and
switch U-Boot from .bin to .img format, stored in
NOR Flash at 0xFFF90000.
Note: this patch was tested on HW and works, i.e.
it boots U-Boot properly, but SPL console output
currently does not appear, due to GD being trashed
by arch/arm/lib/spl.c. This trashing is soon to be
removed, and then ED Mini V2 SPL console output will
become visible.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Porter is an entry level development board based on R-Car M2 SoC (R8A7791)
This commit supports the following peripherals:
- SCIF, I2C, Ethernet, QSPI, SD, USB Host
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Now this feature works. Let's turn it on by default so we do not
depend on specific tool-chains.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
SuperH is supposed to support the Private Library feature, but it is
actually not working.
If CONFIG_USE_PRIVATE_LIBGCC is enabled, the build fails for the
undefined references to '__sdivsi3_i4i' and '__udivsi3_i4i'.
To fix this error, import missing libraries from Linux 3.19
and adjust them for U-Boot:
- Remove "#include <linux/module.h>" and "EXPORT_SYMBOL(...)"
- Use SPDX-License-Identifier
- Remove white space
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Rename two files to the corresponding file names in Linux.
This helps us find missing libraries in the next commit.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Lager board has two SDHI port as SDHI0 and SDHI2.
This adds GPIO configuration and initialization function of SDHI, and
enables MMC command.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Alt board has two SDHI port.
This adds GPIO configuration and initialization function of SDHI, and
enables MMC command.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Sughosh Ganu <urwithsughosh@gmail.com>
Cc: Syed Mohammed Khasim <sm.khasim@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
This is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Chan-Taek Park <c-park@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
This is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Po-Yu Chuang <ratbert@faraday-tech.com>
Acked-by: Marek Vasut <marex@denx.de>
These are still non-generic boards.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Greg Ungerer <greg.ungerer@opengear.com>
Acked-by: Marek Vasut <marex@denx.de>
This is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Lei Wen <leiwen@marvell.com>
Acked-by: Marek Vasut <marex@denx.de>
This is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Matthias Weisser <weisserm@arcor.de>
Acked-by: Marek Vasut <marex@denx.de>
Now CONFIG_SPL_BUILD is not defined in Kconfig, so
"!depends on SPL_BUILD" and "if !SPL_BUILD" are redundant.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
When Kconfig for U-boot was examined, one of the biggest issues was
how to support multiple images (Normal, SPL, TPL). There were
actually two options, "single .config" and "multiple .config".
After some discussions and thought experiments, I chose the latter,
i.e. to create ".config", "spl/.config", "tpl/.config" for Normal,
SPL, TPL, respectively.
It is true that the "multiple .config" strategy provided us the
maximum flexibility and helped to avoid duplicating CONFIGs among
Normal, SPL, TPL, but I have noticed some fatal problems:
[1] It is impossible to share CONFIG options across the images.
If you change the configuration of Main image, you often have to
adjust some SPL configurations correspondingly. Currently, we
cannot handle the dependencies between them. It means one of the
biggest advantages of Kconfig is lost.
[2] It is too painful to change both ".config" and "spl/.config".
Sunxi guys started to work around this problem by creating a new
configuration target. Commit cbdd9a9737 (sunxi: kconfig: Add
%_felconfig rule to enable FEL build of sunxi platforms.) added
"make *_felconfig" to enable CONFIG_SPL_FEL on both images.
Changing the configuration of multiple images in one command is a
generic demand. The current implementation cannot propose any
good solution about this.
[3] Kconfig files are getting ugly and difficult to understand.
Commit b724bd7d63 (dm: Kconfig: Move CONFIG_SYS_MALLOC_F_LEN to
Kconfig) has sprinkled "if !SPL_BUILD" over the Kconfig files.
[4] The build system got more complicated than it should be.
To adjust Linux-originated Kconfig to U-Boot, the helper script
"scripts/multiconfig.sh" was introduced. Writing a complicated
text processor is a shell script sometimes caused problems.
Now I believe the "single .config" will serve us better. With it,
all the problems above would go away. Instead, we will have to add
some CONFIG_SPL_* (and CONFIG_TPL_*) options such as CONFIG_SPL_DM,
but we will not have much. Anyway, this is what we do now in
scripts/Makefile.spl.
I admit my mistake with my apology and this commit switches to the
single .config configuration.
It is not so difficult to do that:
- Remove unnecessary processings from scripts/multiconfig.sh
This file will remain for a while to support the current defconfig
format. It will be removed after more cleanups are done.
- Adjust some makefiles and Kconfigs
- Add some entries to include/config_uncmd_spl.h and the new file
scripts/Makefile.uncmd_spl. Some CONFIG options that are not
supported on SPL must be disabled because one .config is shared
between SPL and U-Boot proper going forward. I know this is not
a beautiful solution and I think we can do better, but let's see
how much we will have to describe them.
- update doc/README.kconfig
More cleaning up patches will follow this.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
It is true that malloc is necessary for Driver Model before
relocation, but there is no good reason to reserve the malloc
space more than enough. The default value 0x400 works well.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
There 4 JRs, 4 RTICs and 8 DECOs, and set them the same stream id
for using the same SMMU3 on LS1021A.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The RCPM FSM may not be reset after power-on, for example,
in the cases of cold boot and wakeup from deep sleep.
It causes cache coherency problem and may block deep sleep.
Therefore, reset them if they are not be reset.
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
LS1021A's PCIe1 region begins 0x40_00000000; PCIe2 begins
0x48_00000000. In order to access PCIe device, we must create
TLB to map the 40bit physical address to 32bit virtual address.
This patch will enable MMU after DDR is available and creates MMU
table in DRAM to map all 4G space; then, re-use the reserved space
to map PCIe region. The following the mapping layout.
VA mapping:
------- <---- 0GB
| |
| |
|-------| <---- 0x24000000
|///////| ===> 192MB VA map for PCIe1 with offset 0x40_0000_0000
|-------| <---- 0x300000000
| |
|-------| <---- 0x34000000
|///////| ===> 192MB VA map for PCIe2 with offset 0x48_0000_0000
|-------| <---- 0x40000000
| |
|-------| <---- 0x80000000 DDR0 space start
|\\\\\\\|
|\\\\\\\| ===> 2GB VA map for 2GB DDR0 Memory space
|\\\\\\\|
------- <---- 4GB DDR0 space end
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch is to define default values for some CCSR macros
to make header files cleaner.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Upgrade Manage Complex (MC) flib API to 0.5.2. Rename directory
fsl_mc to fsl-mc. Change the fsl-mc node in Linux device tree
from "fsl,dprcr" to "fsl-mc". Print MC version info when
appropriate.
Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
FSL-LSCH3 platforms can have multiple DDR clocks. LS2085A has one clock for
general DDR controlers, and another clock for DP-DDR. DDR driver needs to
change to support multiple clocks.
Signed-off-by: York Sun <yorksun@freescale.com>
This patch adds the fdt-fixup logic for the clock frequency of the
NS16550A related device tree nodes.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using
assembly function to guarantee stack is not used before flushing is
completed. Timeout is needed for simualtor on which CCN-504 is not
implemented. Return value can be checked for timeout situation.
Change bootm.c to disable dcache instead of simply flushing, required
by flushing L3.
Signed-off-by: York Sun <yorksun@freescale.com>
U-Boot should only add "enable-method" and "cpu-release-address"
properties to the "cpu" node of the online cores.
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
According to hardware implementation, a single outer shareable global
coherence group is defined. Inner shareable has not bee enabled.
Signed-off-by: York Sun <yorksun@freescale.com>
This patch ensures that the TZPC (BP147) and TZASC-400 programming
happens for LS2085A SoC only when the desired config flags are
enabled and ensures that the TZPC programming is done to allow Non-secure
(NS) + secure (S) transactions only for DCGF registers.
The TZASC component is not present on LS2085A-Rev1, so the TZASC-400
config flag is turned OFF for now.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The WaRP Board is a Wearable Reference Plaform. The board features:
- Freescale i.MX6 SoloLite processor with 512MB of RAM
- Freescale FXOS8700CQ 6-axis Xtrinsic sensor
- Freescale Kinetis KL16 MCU
- Freescale Xtrinsic MMA955xL intelligent motion sensing platform
The board implements a hybrid architecture to address the evolving
needs of the wearables market. The platform consists of a main board
and an example daughtercard with the ability to add additional
daughtercards for different usage models.
For more information about the project, visit:
http://www.warpboard.org/
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Older linux-sunxi-3.4 kernels override our PLL6 setting with 300 MHz,
halving the mbus frequency, so set it to 300 MHz ourselves and base the
mbus divider on that.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
USB doesn't seem to work yet; the controller detects the on-board Hub/
Ethernet device but can't read the descriptors from it. I haven't
investigated yet.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
The bcm2835 and bcm2836 are essentially identical, except:
- The CPU is an ARM1176 v.s. a quad-core Cortex-A7.
- The physical address of many IO controllers has moved.
Rather than introducing a whole new bcm2836 value for $(SOC) or $(ARCH),
update the existing bcm2835 code to handle the minor differences, and
plumb it into the ARMv7 CPU architecture.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
This commit adds $(srctree)/arch/arm/$(machdirs)/include/mach to
the headers search path.
It allows us to replace "#include <asm/arch/foo.h>" with
"#include <mach/foo.h>". As "#include <asm/arch/foo.h>" is still
supported, we can modify each file one by one.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Move
arch/arm/cpu/arm926ejs/kirkwood/* -> arch/arm/mach-kirkwood/*
Note:
Perhaps, can we merge arch/arm/mach-kirkwood and
arch/arm/mvebu-common into arch/arm/mach-mvebu, like Linux?
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Stefan Roese <sr@denx.de>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
In U-boot, the directory structure, arch/$(ARCH)/cpu/$(CPU)/$(SOC)/
has been adopted except that $(CPU) is missing from some
architectures and $(SOC) is missing from some CPUs.
This structure did not fit very well in some cases.
[1] AT91
AT91 SoC family have been developed across some ARM processor
generations. Generally speaking, some IPs are often re-used in the
same SoC family (same SoC vendor) even when the main processor is
updated. As a result, a SoC-common directory is needed in the upper
level. Currently, AT91 source files are placed as follows:
arch/arm/cpu/arm920t/at91/*
arch/arm/cpu/arm926ejs/at91/*
arch/arm/cpu/armv7/at91/*
arch/arm/cpu/at91-common/*
Once directories are split, the motivation for refactorings across
CPU directories is lost. Some files in arm920t/at91/ and
arm926ejs/at91/ are so similar that they could be merged.
[2] Tegra
Tegra is a little bit special case where different CPUs are used for
SPL and the main U-boot. To obey the arch/$(ARCH)/cpu/$(CPU)/$(SOC)
structure, the source files must be placed across the CPUs,
again SoC-common directory is necessary in the upper level.
Moreover, there are several families in Tegra: Tegra20, Tegra30,
Tegra114, Tegra124. Here again, the tegra-common directory is needed
to contain commonly-used files.
Tegra directories have been sprinkled in the directory structure.
arch/arm/cpu/arm720t/tegra20
arch/arm/cpu/arm720t/tegra30
arch/arm/cpu/arm720t/tegra114
arch/arm/cpu/arm720t/tegra124
arch/arm/cpu/arm720t/tegra-common
arch/arm/cpu/armv7/tegra20
arch/arm/cpu/armv7/tegra30
arch/arm/cpu/armv7/tegra114
arch/arm/cpu/armv7/tegra124
arch/arm/cpu/armv7/tegra-common
arch/arm/cpu/tegra20-common
arch/arm/cpu/tegra30-common
arch/arm/cpu/tegra114-common
arch/arm/cpu/tegra124-common
arch/arm/cpu/tegra-common
As you see, splitting SoC code by the CPU is not going well,
especially for ARM.
Why don't we collect SoC-specific files into a single place?
A good example we can follow is Linux's arch/arm/mach-* structure.
This item was discussed in the following thread:
http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/188548/
Looks like I got some positive responses and we are almost ready to
start this movement.
This commit prepares arch/arm/Makefile for describing machdirs in it.
After this commit, we can move SoC directory to arch/arm/mach-$(SOC)
in simple steps although some cases such as AT91 and Tegra need more
fixes.
What we generally have to do is:
[1] Move files arch/arm/cpu/$(CPU)/$(SOC)/* to arch/arm/mach-$(SOC)/*
[2] Add machine entry into arch/arm/Makefile
[3] Remove "obj-y += $(SOC)" from arch/arm/cpu/$(CPU)/Makefile
[4] Fix the Kconfig file path in arch/arm/Kconfig
[5] Modify MAINTAINERS if necessary
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
The board select menu in arch/arm/Kconfig is still big.
To slim down it, this commit moves AT91 boards to
arch/arm/mach-at91/Kconfig.
Also, consolidate "config SYS_SOC" in each board Kconfig.
The Kconfig files under board/ directory were modified with the
following command:
find board -name Kconfig | xargs sed -i -e '
/config SYS_SOC/ {
N
/default "at91"/ {
N
d
}
}
'
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.co>
Introduce arch_reserve_stacks() to tailor gd->start_addr_sp and gd->irq_sp to
the architecture needs.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Before avr32 had an extra storage for stack end to have a nice stack printout
on exception. Remove this extra storage and use generic gd->start_addr_sp
instead.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Prefix mmu.h PAGE_xxx definitions with MMU_ in order to prevent a naming
conflict with other definitions.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
cpu_mmc_init() is required by the init sequence to have a working MMC interface
on avr32. This will not be included in the binary if we omit the avr32 board.c
when building the generic board.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
The self-bias circuit is used by the bandgap during startup.
Once the bandgap has stabilized, the self-bias circuit should
be disabled for best noise performance of analog blocks.
Also this bit should be disabled before the chip enters STOP mode or
when ever the regular bandgap is disabled.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
The only LPC3250 board works fine with enabled generic board support,
add CONFIG_SYS_GENERIC_BOARD right into the arch config header.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
So that the CONFIG_SPL_FEL option is not needed anymore. And the regular
SPL binary, generated by the default u-boot build, is now also bootable
over USB in the FEL mode. The SPL still can boot from the SD card too.
A bunch of system registers need to be saved/restored in order to ensure
that the IRQ handler still works in the BROM FEL code after getting
control back from the SPL. This is done in the sunxi code instead of
abusing ifdefs in 'start.S'.
The decision whether to load the main u-boot binary from the SD card or
return to the FEL code in the BROM is done at runtime.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
[hdegoede@redhat.com: Since we now restore various regs before returning to
the FEL BROM code we can drop the sunxi specific #ifdefs in start.S]
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Make sunxi's FEL code fit with the normal U-Boot boot sequence instead of
creating its own. There are some #ifdefs required in start.S. Future work
will hopefully remove these.
This series is available at u-boot-dm, branch sunxi-working.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Some boards have a special way of loading U-Boot that does not fit with
the existing SPL code. For example sunxi uses an 'FEL' mode where U-Boot
is loaded over USB. Add a CONFIG option and boot mode for this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The link register value can be required on some boards (e.g. FEL mode on
sunxi) so use a branch instruction to jump to save_boot_params() instead
of a branch link.
This requires a branch back to save_boot_params_ret so adjust the users
to deal with this. For exynos just drop the function since it doesn't
do anything.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Move the dram helper functions to a separate C file, rather then having them
as inline helpers in dram.h. This saves 144 bytes in the .text segment for
sun6i builds.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
KS2 ddr3 initialization uses ddr3_size global variable before u-boot
relocation. Even if the variable is not being used after relocation,
writing to it corrupts relocation table.
This patch removes the global ddr3_size variable and uses local one
instead.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
When EMAC is in the boot order, the boot ROM sets OPP50 and the
MAC clock is set to /2. SPL needs to change it to /5 for Ethernet
to generate the correct txclk. This patch sets it correctly.
Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
The value in SDRAM_REF_CTRL controls the delay time between
the initial rising edge of DDR_RESETn to rising edge of DDR_CKE
(JEDEC specs this as 500us). In order to achieve this, SDRAM_REF_CTRL
should be written with a value corresponding to 500us delay before
starting DDR initialization sequence, and configure proper
value at the end of sequence.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
DDR3 timing and latency paramenters were not configured
correctly for 666MHz. Fixing the timing and latency values
according to Data sheet.
This fixes the random crashes seen on DRA72-evm.
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
An option is provided to avoid using SDL in U-Boot sandbox (and drop
support for the LCD). However the check in the Makefile is too late
and warnings are printed even if NO_SDL=y is given.
Adjust the order to avoid this warning.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Jeroen Hofstee <jeroen@myspectrum.nl>
When a command is passed into sandbox using the '-c' argument the
command is run directly. This is most helpful when running tests (such
as test-dm.sh). Previously the exit code was an unused enum. Change it
to be the actual return code from the command so that the script calling
sandbox can know if the command succeeded (tests passed). Also remove
the now completely unused "exit_state" in sandbox.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
Since we have src, div and pre-div mask bits defined corresponding
to peripherals, calculation of clock specific to I2C appears
redundant and confusing. Using clk_bit_info struct we can write
calculations generic to all peripherals which makes code easy to
understand and free from peripheral specific exceptions.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
We have assumed and kept mask bits for divider and pre-divider
as 0xf and 0xff, respectively. But these mask bits change from
one peripheral to another, and hence, need to be specified in
accordance with the peripherals.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Replacing SoC and peripheral specific function calls with generic
clock_get_periph_rate calls to get the peripheral clocks.
Also, removing dead code of peripheral and SoC specific function
implementations which was used earlier for fetching peripheral clocks.
This code is not being used anymore because of the introduction
of generic clock_get_periph_rate function.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
exynos5_get_periph_rate function reads incorrect div for
SDMMC2 & 3. It also reads prediv and does division only for
SDMMC0 & 2 when actually various other peripherals need that.
Adding changes to fix these mistakes in periph rate calculation.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
We planned to fetch peripheral rate through one generic API per
peripheral. These generic peripheral functions are in turn
expected to fetch apt values from a function refactored as
per SoC versions. This patch adds support for fetching peripheral
rates for Exynos5420 and Exynos5800.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Moving exynos5420_get_pll_clk function definition up in the
code to keep it together with rest of SoC_get_pll_clk functions.
This makes code more legible and also removes the need of
declaration when called before the position of definition in
code. Also, renaming exynos5420_get_pll_clk to
exynos542x_get_pll_clk because it is being used for both Exynos
5420 and 5800.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Apparently, members of clk_bit_info array do not map correctly
to the members of enum periph_id. This mapping got broken after
we changed periph_id(s) to reflect interrupt number instead of
their position in a sequence. This patch intends to fix above
mentioned issue.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Exynos5420 has different registers with other exynos5 SoCs to control
usb device phy, so need separated function to enable exynos5420 usb
device phy.
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This needs for special handling of nRESET_OUT line(GPD1-0 gpio) for eMMC
memory to perform complete reboot on Odroid XU3 board.
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This needs for special handling of nRESET_OUT line(GPK1-2 gpio) for eMMC
memory to perform complete reboot on Odroid X2/U3 boards.
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The most exynos used the "Ratio + 1" as div value.
And value at register is "Ratio".
So if want to set exact value, it needs to subtract one.
Value at register ("Ratio") = div - 1
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
ARC HS and ARC EM are new cores based on ARCv2 ISA which is binary
incompatible with ISAv1 (AKA ARCompact).
Significant difference between ISAv2 and v1 is implementation of
interrupt vector table.
In v1 it is implemented in the same way as on many other architectures -
as a special location where user may put whether code executed in place
(if machine word of space is enough) or jump to a full-scale interrupt
handler.
In v2 interrupt table is just an array of adresses of real interrupt
handlers. That requires a separate section for IVT that is not encoded
as code by assembler.
This change adds support for following cores:
* ARC EM6 (simple 32-bit microcontroller without MMU)
* ARC HS36 (advanced 32-bit microcontroller without MMU)
* ARC HS38 (advanced 32-bit microcontroller with MMU)
As a part of ARC HS38 new version of MMU (v4) was introduced.
Also this change adds AXS131 board which is the same DW ARC SDP base board but
with ARC HS38 CPU tile.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
r8a7794 uses ARM SoC of CA7 base. If we want to use dcache on CA7, we
need to enable SMP bit of Auxiliary Control Register.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
SILK is an entry level development board based on R-Car E2 SoC (R8A7794)
This commit supports the following peripherals:
- SCIF, I2C, Ethernet, QSPI, MMC, USB Host
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Reviewed-by: Tom Rini <trini@ti.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
With driver model the number of PIO ports is defined by platform data, so
remove it from the header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
These additional nodes need to be provided to get U-Boot to boot correctly
on the Canyonlands / Glacier board:
- chosen path to the console-uart
- reg-shift set to 0 in the uart device nodes
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Define an _end symbol indicating the end of u-boot.bin. Also add some dummy
words into the link script to ensure that u-boot.bin will always extend
that far. There may be a better way of doing this.
Signed-off-by: Simon Glass <sjg@chromium.org>
This is required at present for device tree control. The ppc4xx does support
GPIOs but does not seem to have a proper driver. So this file is empty.
Signed-off-by: Simon Glass <sjg@chromium.org>
The canyonlands.h config file works with canyonlands, glacier and arches
boards. Bring in the device tree files for these from Linux 3.17.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a new ramboot config for glacier so that it is possible to test U-Boot
loaded over Ethernet instead of using JTAG.
Signed-off-by: Simon Glass <sjg@chromium.org>
Many CONFIG options have an unnecessary value of 1. CONFIG_440 is set in
the various board config files. Also simplify the CONFIG_440 check in
config.mk
Signed-off-by: Simon Glass <sjg@chromium.org>
When booting in JTAG mode, there is no way to use soft break-points, and
no way of knowing when SPL has finished executing (so the user can issue
a 'halt' command to load u-boot.bin for example)
Add a debug output and simple loop to stop execution at the completion of
the SPL initialisation as a pseudo break-point when booting in JTAG mode
Signed-off-by: Graeme Russ <gruss@tss-engineering.com>
Section 4.1.2 of Freescale Application Note AN4199 describes the
configuration required to operate the mx28 from a 5V source without a
battery.
This patch changes the behaviour of the dropout control of the DC-DC
converter (refer to section 11.12.9 of the mx28 Application Processor
Reference Manual - Document Number: MCIMX28RM, Rev 2, 08/2013) to the
following:
- Always use 4P2 Linear Regulator if CONFIG_SYS_MXS_VDD5V_ONLY is defined
- Switch between 4P2 Linear Regulator and Battery, using whichever has
the highest voltage if CONFIG_SYS_MXS_VDD5V_ONLY isnot set (this is
the same as the pre-patch behaviour)
Signed-off-by: Graeme Russ <gruss@tss-engineering.com>
Signed-off-by: Damien Gotfroi <dgotfroi@greenwatch.be>
It is difficult to track down fail to boot issues in the mxs SPL.
Implement the following to make it easier:
- Add debug outputs to allow tracing of SPL progress in order to track
where failure to boot occurs. DEUBUG and CONFIG_SPL_SERIAL_SUPPORT must
be defined to enable debug output in SPL
- Add TODO comments where it is not clear if the code is doing what it
is meant to be doing, even tough the board boots properly (these comments
refer to existing code, not to any code added by this patch)
Signed-off-by: Graeme Russ <gruss@tss-engineering.com>
Should use AIPS3 configuration address 0x0227C000 to set AIPS3,
not the AIPS3 base address.
Additional, replace AIPS1_BASE_ADDR to AIPS3_ARB_BASE_ADDR to align with
AIPS1 and AIPS2, and resolve the AIPS3_ARB_BASE_ADDR undefine problem.
Signed-off-by: Ye.Li <B37916@freescale.com>
This patch has some parts connected together:
- Use _gd in bss section which is automatically cleared
Location at SPL_MALLOC_END wasn't cleared at all
- Use MALLOC_F_LEN(early alloc) instead of FULL MALLOC
(mem_malloc_init is not called at all)
- Simplify malloc and stack init.
At the end of SPL addr is malloc area and below is stack
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Because it is not compatible with DM where
malloc_base has to be available early and init
has to be done in ASM.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Compile code with -fPIC to get GOT. Do not build SPL
with fPIC because it increasing SPL size for nothing.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Setup gd from ASM to be availalbe for board_init_r.
Setting it up in spl_board_init is too late when
MALLOC is used.
Space for gd is located behind MALLOC area at the end of BRAM.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Do not use specific macros for debugging.
Also remove compilation warning:
w+../arch/microblaze/cpu/interrupts.c: In function 'interrupt_handler':
w+../arch/microblaze/cpu/interrupts.c:153:2: warning: format '%x'
expects argument of type 'unsigned int', but argument 2 has type 'void
(*)(void *)' [-Wformat]
w+../arch/microblaze/cpu/interrupts.c:153:2: warning: format '%x'
expects argument of type 'unsigned int', but argument 4 has type 'void
*' [-Wformat]
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Do not save registers below r1 stack pointer because
it is not checked by stack undeflow is not able to detect
it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This way we may have very limited set of functions implemented so we
save some space.
Also it allows us to build U-Boot for any ARC core with the same one
toolchain because we don't rely on pre-built libgcc.
For example:
* we may use little-endian toolchain but build U-Boot for ether
endianess
* we may use non-multilibbed uClibc toolchain but build U-Boot for
whatever ARC CPU flavour that current GCC supports
Private libgcc built from generic C implementation contributes only 144
bytes to .text section so we don't see significant degradation of size:
--->8---
$ arc-linux-size u-boot.libgcc-prebuilt
text data bss dec hex filename
222217 24912 214820 461949 70c7d u-boot.libgcc-prebuilt
$ arc-linux-size u-boot.libgcc-private
text data bss dec hex filename
222361 24912 214820 462093 70d0d u-boot.libgcc-private
--->8---
Also I don't notice visible performance degradation compared to
pre-built libgcc (where at least "*div*" functions are had-written in
assembly) on typical operations of downloading 10Mb uImage over TFTP and
bootm.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
As a preparation to ARCv2 port submission we're moving CPU slection
flags to a common location.
Also it will allow us to have more flexible CPU specification, not only
ISA version but CPU family as well checking CONFIG_ARC_CPU_xxx.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Common arch_early_init_r() is used in "arc/lib/cpu.c" for all ARC boards
so there's no sense in separate per-board definitions.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
There're no other options for ARC except "generic board" so ther's no
point to define CONFIG_SYS_GENERIC_BOARD per board.
We now have it set fo all ARC boards.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
This change allows to keep board description clean and minimalistic.
This is especially helpful if one board may house different CPUs with
different features.
It is applicable to both FPGA-based boards or those that have CPUs
mounted on interchnagable daughter-boards.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
This change allows to keep board description clean and minimalistic.
This is especially helpful if one board may house different CPUs with
different features.
It is applicable to both FPGA-based boards or those that have CPUs
mounted on interchnagable daughter-boards.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Now we may select a particular version of ARC700:
* ARC750D or
* ARC770D
It allows more flexible (or more fine tuned) configuration of U-Boot.
Before that change we relied on minimal configuration but now we may
use specific features of each CPU.
Moreover allows us to escape manual selection of options that
exist in both CPUs but may have say different version like MMUv2 in
ARC750D vs MMUv3 in ARC770D.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
It's prohibited to put branch instruction in the very end of zero-delay
loop. On execution this causes "Illegal instruction" exception.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
As the at91cap9adk board is removed by commit: b5508344
(ARM: remove broken "at91cap9adk" board), so the at91cap9
code is not used anymore, and also the document for
at91cap9 can not be found on www.atmel.com, so remove the
at91cap9 related code.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
Some SoC need to redirect the saic to aic to make the interrupt to
work, here add a weak function to be replaced by real function.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
The SFR (special function registers) can be shared bwteen
sama5d3 and sama5d4 soc.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
[whitespace adoptions for 80 char compliance]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
This matrix header file can be shared between sama5d3 and sama5d4 soc.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
[whitespace adaptions for 80 char compliance]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Space is used before 'default' in PCIE_ECAM_BASE in arch/x86/Kconfig
so it looks misaligned. Replace the space with tab to indent.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Intel Galileo board has a microSD slot which is routed from Quark SoC
SDIO controller. Enable SD/MMC support so that we can use an SD card.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
The Quark SoC contains a legacy SPI controller in the legacy bridge
which is ICH7 compatible. Like Tunnel Creek and BayTrail, the BIOS
control register offset in the ICH SPI driver is wrong for the Quark
SoC too, unprotect_spi_flash() is added to enable the flash write.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Quark SoC has a legacy GPIO block in the legacy bridge (D0:F31),
which is just the same one found in other x86 chipset. Since we
programmed the GPIO register block base address, we should be
able to enable the GPIO support on Intel Galileo board.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Quark SoC has some non-standard BARs (excluding PCI standard BARs)
which need be initialized with suggested values. This includes GPIO,
WDT, RCBA, PCIe ECAM and some ACPI register block base addresses.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Now that we have added Quark MRC codes, call MRC in dram_init() so
that DRAM can be initialized on a Quark based board.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
For some unknown reason, the TSC calibration via PIT does not work on
Quark. Enable bypassing TSC calibration and override TSC_FREQ_IN_MHZ
to 400 per Quark datasheet in the Kconfig.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
We should allow the value of TSC_FREQ_IN_MHZ to be overridden by
the one in arch/cpu/<xxx>/Kconfig.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Make the Intel quark/galileo support avaiable in Kconfig and Makefile.
With this patch, we can generate u-boot.rom for Intel galileo board.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
New board/intel/galileo board directory with minimum codes, plus
board dts, defconfig and configuration files.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Add minimum codes to support Intel Quark SoC. DRAM initialization
is not ready yet so a hardcoded gd->ram_size is assigned.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Quark SoC contains an embedded 512KiB SRAM (eSRAM) that is
initialized by hardware. eSRAM is the ideal place to be used
for Cache-As-RAM (CAR) before system memory is available.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Move PCI_REG_ADDR and PCI_REG_DATA from arch/x86/lib/pci_type1.c to
arch/x86/include/asm/pci.h, also define PCI_CFG_EN so that these
macros can be used for pci configuration space access.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
In the Quark SoC, some chipset commands are accomplished by utilizing
the internal message network within the host bridge (D0:F0). Accesses
to this network are accomplished by populating the message control
register (MCR), Message Control Register eXtension (MCRX) and the
message data register (MDR).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
device.h for integrated pci devices' bdf on Quark SoC and quark.h for
various memory-mapped and i/o-mapped base addresses within SoC.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
This is a relatively low-cost x86 board in a small form factor. The main
peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800
series CPU. So far only the dual core 2GB variant is supported.
This uses the existing FSP support. Binary blobs are required to make this
board work. The microcode update is included as a patch (all 3000 lines of
it).
Change-Id: I0088c47fe87cf08ae635b343d32c332269062156
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Since the FSP is a black box it helps to have some sort of debugging
available to check its inputs. If the debug UART is in use, set it up
after CAR is available.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
While queensbay is the first chip with these settings, others will want to
use them too. Make them common.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Since these board functions seem to be the same for all boards which use
FSP, move them into a common file. We can adjust this later if future FSPs
need more flexibility.
This creates a generic PCI MMC device.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
This code is ported from the Marvell bin_hdr code into mainline
SPL U-Boot. It needs to be executed very early so that the devices
connected to the serdes PHY are configured correctly.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
This patch adds SPL support to the Marvell Armada-XP. With this addition
the bin_hdr integration is not needed any more. The SPL will first
initialize the serdes/PHY and the call the DDR setup and training code
now integrated into mainline U-Boot.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
This patch adds SPL support to the db-mv784mp-gp eval board.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
This patch adds SPL support to the maxbcm MV78460 based board. Including
the fixed DDR configuratrion needed for the DDR training code. And the
the serdes PHY init code.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
Checking if the pointer is NULL would be easier to know the tail
of the boot_device_table[] array.
For clarification, add the /* sentinel */ comment.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
The return value of get_boot_mode_sel() is used as the index of
the boot_device_table[] array. Its type should be "int" rather
than "u32".
Use only the iterator "i" for the loop in do_pinmon().
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
To use I2C controllers on PH1-sLD8, the bit 10 (SCL0/SDA0)
and bit 11 (SCL1/SDA1) of IECTRL register must be set.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
It is true that unused functions are removed from the ELF image
by the compiler's garbage collection but relying on it too much
does not look nice.
Currently, the build is taking more than it should.
Refactor the makefiles to compile only files that are really needed.
CONFIG_SOC_INIT and CONFIG_DRAM_INIT are no longer needed by the
optimization.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Since commit 0365ffcc0b (generic-board: show model name in
board_init_f() too), checkboard() is invoked only when
show_board_info() fails to get the model name from Device Tree.
It never happens because UniPhier SoCs now only work with
CONFIG_OF_CONTROL and all the root nodes of UniPhier device trees
have the "model" property.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Since commit 0365ffcc0b (generic-board: show model name in
board_init_f() too), the support card information has not been
displayed because check_support_card() is invoked only when
show_board_info() fails to get the model name from Device Tree.
This commit adds misc_init_f() function to call check_support_card()
from there.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Now init functions called from board_postclk_init() and dram_init()
are only necessary for SPL.
Move them to spl_board_init() for clean-up.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Currently, I/O pin settings are not necessary for SPL.
The board_early_init_f() seems a suitable place to call pin_init().
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
The EEPROM chips on UniPhier reference daughter boards expect 2-byte
offset address.
Since 7132b9fd68 (dm: i2c: dts: Support an offset-len device tree
property), I2C sub-nodes can have "u-boot,i2c-offset-len" property.
It is convenient to set the default I2C offset address length in
Device Tree, so that we do not have to set it on the command line.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This EEPROM chip is installed on the expansion board commonly used
on UniPhier platform. To avoid duplicated description, move the
EEPROM node to a separate file and include it from other device tree
sources.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This dummy header was introduced by commit 630bf80ebb (ARM:
UniPhier: add dummy gpio.h to enable CONFIG_OF_CONTROL).
Thanks to commit a08d643dbd (dm: Drop gpio.h header from
fdtdec.c), such an ugly workaround is no longer needed.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
For now this code seems to be the same for all FSP platforms. Make it
common until we see what differences are required.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
To avoid casts, find_fsp_header() should return a pointer. Add asmlinkage
to two API functions which use that convention. UPD_TERMINATOR is common
so move it into a common file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
If the BIOS emulator is not available, allow use of native execution if
available, and vice versa. This can be controlled by the caller.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This setting will be used by more than just ivybridge so make it common.
Also rename it to PCIE_ECAM_BASE which is a more descriptive name.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
If we don't know the relocation address, the raw values are not very useful.
Show the pre-relocation values as well as these can be looked up in
System.map, etc.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
It turns out that the device_mode_data is rsb specific, rather then slave
specific, so integrate the rsb_set_device_mode() call into rsb_init().
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
And use this to set the GMAC Transmit Clock Delay Chain value on Banana
boards, rather then keying of CONFIG_TARGET_FOO.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This patch adds basic constructs in the ARMv8 u-boot code
to handle and apply Cortex-A57 specific erratas.
As and example, the framework showcases how erratas 833069, 826974
and 828024 can be handled and applied.
Later on this framework can be extended to include other
erratas.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
It is painful to specify the full path to the device tree with the -d
option. It is normally kept in the same directory as U-Boot, so provide
an option to use this by default.
Signed-off-by: Simon Glass <sjg@chromium.org>
The Juno Development Platform is a physical Versatile Express
device with some differences from the emulated semihosting
models. The main difference is that the system is split in
a SoC and an FPGA where the SoC hosts the serial ports at
totally different adresses.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The Versatile Express ARMv8 semihosted FVP platform is still
using the legacy CONFIG_SYS_EXTRA_OPTIONS method to configure
some compile-time flags. Get rid of this and create a Kconfig
entry for the FVP model, and a selectable bool for the
semihosting library.
The FVP subboard is now modeled as a target choice so we can
eventually choose between different ARMv8 versatile express
boards (FVP, base model, Juno...) this way. All dependent
symbols are updated to reflect this.
The 64bit Versatile Express board symbols are renamed
VEXPRESS64 so we have some chance to see what is actually
going on. Tested on the FVP fast model.
Acked-by: Steve Rae <srae@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Unify and move code in arch/mips/cpu/mips[32|64]/ to arch/mips/cpu/.
The CPU specific config.mk files need to remain until
CONFIG_STANDALONE_LOAD_ADDR is converted to a global Kconfig symbol.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Move all au1x00 code out of arch/mips/cpu/mips32 to allow
unification of CPU code in a later patch. The reorganization
of the SoC specific header files will be done in a later patch
series.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Paul Burton <paul.burton@imgtec.com>
In preparation for sharing a single copy of start.S between mips32 &
mips64, handle setting the KX bit of the cop0 Status register when the
mips32 start.S is built for mips64.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
In preparation for sharing a single copy of start.S between mips32 &
mips64, handle mips64 relocations in the mips32 start.S when built for
mips64.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Where the mips32 & mips64 implementations of start.S differ in terms of
access sizes & offsets, use the appropriate macros from asm.h to
abstract those differences away. This is in preparation for sharing a
single copy of start.S between mips32 & mips64.
The exception to this is loads of immediates to be written to the cop0
Config register, which is a 32bit register on mips64 and therefore
constants written to it can be loaded as such.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This change fixes i2c bus numbering for Odroid U3.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Some versions of Exynos5 supports High-Speed I2C,
on few interfaces, this change allows support this.
The new flag is: PINMUX_FLAG_HS_MODE
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Akshay Saraswat <akshay.s@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Without this alias setting, the seq numbers
of the i2c devices are wrong.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Minkyu Kang <mk7.kang@samsung.com>
This patch modify i2c nodes in exynos4.dtsi with:
- adding proper interrupts arrays for each i2c node,
which allows to decode periph id
- add reg address for each i2c node for i2c driver internal use
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
this is an atempt to make the export of functions typesafe.
I replaced the jumptable void ** by a struct (jt_funcs) with function pointers.
The EXPORT_FUNC macro now has 3 fixed parameters and one
variadic parameter
The first is the name of the exported function,
the rest of the parameters are used to format a functionpointer
in the jumptable,
the EXPORT_FUNC macros are expanded three times,
1. to declare the members of the struct
2. to initialize the structmember pointers
3. to call the functions in stubs.c
Signed-off-by: Martin Dorwig <dorwig@tetronik.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
(resending to the list since my tweaks are not quite trivial)
Rather than assuming that the chip offset length is 1, allow it to be
provided. This allows chips that don't use the default offset length to
be used (at present they are only supported by the command line 'i2c'
command which sets the offset length explicitly).
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
U-Boot now supports using GPIOs using bank phandles instead of global
numbers. Update the exynos device tree files to use this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
Add a new 'demo light' command which uses GPIOs to control imaginary lights.
Each light is assigned a bit number in the overall value. This provides an
example driver for using the new GPIO API.
Signed-off-by: Simon Glass <sjg@chromium.org>
In f0c3a6c we stopped setting gd in board_init_f, but later had to
revert to due problems on certain platforms. As davinci does not look
to have these problems, we can drop the setting here and rely upon
crt0.S to do it.
Cc: Peter Howard <pjh@northern-ridge.com.au>
Signed-off-by: Tom Rini <trini@ti.com>
On the DRA72x (J6Eco) EVM one PMIC SMPS is powering three SoC
core rails. This concept of using one SMPS to supply multiple
core domains (in various, although limited combinations, per
primary device use case) has now become common and is used by
many customer J6/J6Eco designs; it is supported by a number of
corresponding PMIC OTP versions.
This patch implements correct operation of the core voltages
scaling routine by ensuring that each SMPS that is supplying
more than one domain shall be written only once, and with the
highest voltage of those fused in the SoC (or of those defined
in the corresponding header if fuse read is disabled or fails)
for the power rails belonging to the group.
The patch also replaces some PMIC-related magic numbers with
the appropriate definitions. The default OPP_NOM voltages for
the DRA7xx SoCs are updated as well, per the latest DMs.
Signed-off-by: Lubomir Popov <l-popov@ti.com>
This patch adds IDE support to the MIPS Malta board. The IDE controller
is enabled after probing the PCI bus and otherwise just makes use of
U-boot generic IDE support.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Current MIPS cores from Imagination Technologies use TagLo select 2 for
the data cache. The architecture requires that it is safe for software
to write to this register even if it isn't present, so take the trivial
option of clearing both selects 0 & 2.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Current MIPS systems do not require that loads be performed to force the
parity of cache lines, a simple invalidate by clearing the tag for each
line will suffice. Thus this patch makes the loads & subsequent second
invalidation conditional upon the CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
option, and defines that for existing mips32 targets. Exceptions are
malta where this is known to be unnecessary, and qemu-mips where caches
are not implemented.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
The mips_init_[id]cache functions are small & only called once from a
single callsite. Inlining them allows mips_cache_reset to avoid having
to bother moving arguments around & leaves it a leaf function which is
thus able to simply keep the return address live in the ra register
throughout, simplifying the code.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reduce duplication by performing loops through cache tags using an
assembler macro.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reduce duplication between reading the configuration of the L1 dcache &
icache by performing both using a macro which calculates the appropriate
line & cache sizes from the coprocessor 0 Config1 register.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
The mips32 & mips64 cache initialization code differs only in that the
mips32 code supports reading the cache size from coprocessor 0 registers
at runtime. Move the more developed mips32 version to a common
arch/mips/lib/cache_init.S & remove the now-redundant mips64 version in
order to reduce duplication. The temporary registers used are shuffled
slightly in order to work for both mips32 & mips64 builds. The RA
register is defined differently to suit mips32 & mips64, but will be
removed by a later commit in the series after further cleanup.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Move the more developed mips32 version of the cache maintenance
functions to a common arch/mips/lib/cache.c, in order to reduce
duplication between mips32 & mips64.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
As a step towards unifying the cache maintenance code for mips32 &
mips64 CPUs, stop using ".set <ISA>" directives in the more developed
mips32 version of the code. Instead, when present make use of the GCC
builtin for emitting a cache instruction. When not present, simply don't
bother with the .set directives since U-boot always builds with
-march=mips32 or higher anyway.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Set only the 0-3 bits of the FPGA_RST_CTRL register
as other bits should not be set to 1.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Nathan Rossi <nathan.rossi@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Setup half of memory from ram_size for ECC case.
All the time the same board can be configured
with or without ECC. Based on ECC case detection
use half of memory with the same configuration.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Added the lowlevel_init to enable the Neon instructions.
Initially the u-boot was causing undefined instruction
exception if loaded through tcl, and working fine if loaded
through FSBL. The exception was causing in convertion formula
of given time to ticks. It was because, the Neon instructions
were disabled and hence causing the undefined exception. In
FSBL case, the FSBL was enabling the Neon instructions. Hence,
added the lowlevel_init to enable the Neon instructions.
Also enable neon instructions for non-xilinx toolchain.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Acked-by: Radhey Shyam Pandey <radheys@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add deep sleep support on Freescale LS1021QDS platform.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
[York Sun: Fix conflict in fdt.c]
Reviewed-by: York Sun <yorksun@freescale.com>
The memory reference code takes a very long time to 'train' its SDRAM
interface, around half a second. To avoid this delay on every boot we can
store the parameters from the last training sessions to speed up the next.
Add an implementation of this, storing the training data in CMOS RAM and
SPI flash.
Signed-off-by: Simon Glass <sjg@chromium.org>
Correct the SPI flash compatible string, add an alias and specify the
position of the MRC cache, used to store SDRAM training settings for the
Memory Reference Code.
Signed-off-by: Simon Glass <sjg@chromium.org>
The existing IP checksum function is only accessible to the 'coreboot' cpu.
Drop it in favour of the new code in the network subsystem.
Signed-off-by: Simon Glass <sjg@chromium.org>
As QSPI/DSPI and IFC are pin multiplexed, QSPI and DSPI are
only enabled in QSPI boot, and disabled in other boot modes.
IFC is enabled in NOR/NAND/SD boot, and disabled in QSPI boot.
This patch will add fdt support for the above rules.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
CAAM is connected to CCI-400 S0 slave interface. Disable snooping for
S0 will cause CAAM self test failure. This patch is to enable snooping
for S0 slave interface. These CCI-400 operations are moved to
board_early_init_f() to be initialized earlier. For S4 slave interface,
issuing of snoop requests and DVM message requests are enabled.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Defining variable gic_dist_addr as a globe one prevents some
functions, which use it, from being used before relocation
which is the case in the deep sleep resume process on Freescale
SoC platforms.
Besides, we can always get the GIC base address by calling
get_gicd_base_address() without referring gic_dist_addr.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Era property is added in the crypto node in device tree.
Move the code to do so from arch/powerpc/mpc8xxx/fdt.c to
drivers/sec/sec.c so that it can be used across arm and
powerpc platforms having crypto node.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
[York Sun: Fix commit message indentation]
Reviewed-by: York Sun <yorksun@freescale.com>
If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled.
It includes <asm/gpio.h> and then <asm/gpio.h> includes
<asm/arch/gpio.h>. As a result, all the SoCs that enable
CONFIG_OF_CONTROL must have <asm/arch/gpio.h> even if they
do not support GPIO.
The right fix would be to split the lib/fdtdec.c to remove
dependency on GPIO.This commit adds a dummy <asm/arch/gpio.h>
to support OF_CONTROL for LS102x platform. This dummy header
will be removed after FDT-GPIO stuff is fixed correctly.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch reverts to use ge0_clk125 for eTSEC clock muxing. For SAI and
CAN which are pin multiplexed with RGMII1 in EC1 of RCW, ge2_clk125 will
be used via hwconfig.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Internal memory controller counters can reach a bad state after
training in DDR4 mode if accumulated ECC or DBI mode is eanbled.
Signed-off-by: York Sun <yorksun@freescale.com>
Various minor code format issues are fixed in start16.S:
- U-boot -> U-Boot
- 32bit -> 32-bit
- Use TAB instead of SPACE to indent
- Move the indention location of the GDT comment block
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
On some x86 processors (like Intel Quark) the MTRR registers are not
supported. This is reflected by the CPUID (EAX 01H) result EDX[12].
Accessing the MTRR registers on such processors will cause #GP so we
must test the support flag before accessing MTRR MSRs.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
CPUID (EAX 01H) returns MTRR support flag in EDX bit 12. Probe this
flag in x86_cpu_init_f() and save it in global data.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
arch/x86/cpu/mtrr.c has access to the U-Boot global data thus
DECLARE_GLOBAL_DATA_PTR is needed.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
We shouldn't assume that the VGA ROM can always be loaded at c0000. This
is only true on x86 machines.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
These boards are still non-generic boards.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
These boards are still non-generic boards.
It is a good thing that we can drop board-specific hack code
from drivers/mtd/nand/nand_base.c
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Stefan Roese <sr@denx.de>
Cc: Andrea "llandre" Marson <andrea.marson@dave-tech.it>
These boards are still non-generic boards.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Dave Liu <daveliu@freescale.com>
Cc: Anton Vorontsov <avorontsov@ru.mvista.com>
Match the suffixes of SG_MEMCONF_* macros with SZ_* macros defined
by <linux/sizes.h> for readability.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
The inlining is done by GCC when needed, there is no need to do it
explicitly. Furthermore, the inline keyword does not force-inline
the code, but is only a hint for the compiler.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
For PH1-Pro4, the bit 6 of the IECTRL must be set. It is the only
available bit in this register. There is no effect of the write
access to the other bits.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
The assembly directive ".rept ... .endr" allows us to write the
init_page_table much shorter. To make things further simpler,
set the text and stack area as Normal Memory, and the other sections
as Device attribute.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
The DDR PHY training function, ddrphy_prepare_training() would not
work if compiled with GCC 4.9.
The struct ddrphy (arch/arm/include/asm/arch-uniphier/ddrphy-regs.h)
is specified with __packed because it represents a hardware register
mapping, but it turned out to cause a problem on GCC 4.9.
If -mno-unaligned-access is specified (yes, it is in
arch/arm/cpu/armv7/config.mk), GCC 4.9 is aware of the
__attribute__((packed)) and generates extra instructions to perform
the memory access in a way that does not cause unaligned access.
(Actually it is not need here because the register base, the first
argument of the ddrphy_prepare_training(), is always given with a
4-byte aligned address.)
Anyway, as a result, readl() / writel() is divided into byte-wise
accesses. The problem is that this hardware only accepts 4-byte
register access. Byte-wise accesses lead to unexpected behavior.
There are some options to avoid this problem.
[1] Remove -mno-unaligned-access
[2] Add __aligned(4) along with __packed to struct ddrphy
[3] Remove __packed from struct ddrphy
[1] solves the problem for ARMv7, but it does not for pre-ARMv6 and
ARMv6-M architectures where -mno-unaligned-access is default.
So, [1] does not seem reasonable in terms of code portability.
Both [2] and [3] work well, but [2] seems too much. All the members
of struct ddrphy have the u32 type. No padding would be inserted
even if __packed is dropped.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Tom Rini <trini@ti.com>
Hookup OTG USB controller support and enable the otg controller + USB-keyb
on various tablets.
This allows tablet owners to interact with u-boot without needing to solder
a serial console onto their tablet PCB.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Testing has shown that on sun4i the display backend engine does not have
deep enough fifo-s causing flickering / tearing in full-hd mode due to
fifo underruns. On sun4i use the display frontend engine to do the dma from
memory, as the frontend does have deep enough fifo-s.
As added advantage of this is that it results in much better memory bandwidth
as it reduces the amount of dram bank switches, for more details see:
http://ssvb.github.io/2014/11/11/revisiting-fullhd-x11-desktop-performance-of-the-allwinner-a10.html
Note that this changes the pipeline searched for in the simplefb node, we can
get away with doing this now, since no kernel has yet shipped with simplefb
dtb nodes, and I will make sure to get a simplefb node with the new pipeline
into 3.19 before it ships.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
While working on adding more boards I noticed that we lack a config for
the 512M cubieboard, and that some of the new boards which I want to add also
have 512M and 1G variants, rather then adding 2 defconfig's for all of these,
lets switch the exising boards which have both a 512M and 1024M variant over
to the sun4i dram autoconfig code.
This also drops the foo_RAMSIZE_defconfig variants of boards where we currently
have 2 separate configs already.
Note:
1) The newly introduced CONFIG_DRAM_EMR1 kconfig value is not used with
a value other then its default for now, but we need this to be configurable
to support some new boards with auto dram config.
2) We always set all CONFIG_DRAM_foo values in defconfigs, even if they match
the defaults, this is done to make it more clear what values are used for a
certain board.
This has been tested on a Mele A1000, Mini-X and a Cubieboard, all 1G
variants, the dram autoconfig code has also been tested on a 512M mk802
(a defconfig for the mk802 is added in a later patch).
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The clocks on the A80 are hooked up slightly different, add support for this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add initial sun9i (A80) clock setup support, enough to get the uart + mmc
going.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add a headerfile with all the base addresses from the sun9i blocks.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
sun4i - sun8i have (aprox.) the same iomem layout, but sun9i is quite
different, so add a wrapper cpu.h which includes the right mach specific
cpu_sun#i.h based on mach, like we already do with clock.h and dram.h .
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Which pll-s are available depends on the machine type, move the
clock_get_pllX / clock_set_pllX prototypes to the clock_sun?i.h header files
so that we only declare what is actually available. e.g. clock_get_pll5p()
is not available on sun6i / sun8i, and with sun9i we get a completely
different set of plls.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
As the comment says now that we have SPL support this is no longer necessary,
as PLL6 is already setup with the exact same parameters by the SPL.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
While running some tests with an Olinuxino-A13-Micro + a 7" Olimex LCD module
I noticed that the screen flickered. This is caused by the lcd display clk
phase reg value being set to 0, where it should be 1 in this setup.
This commit adds a Kconfig option for the lcd display clk phase, so that we
can set it per board. This defaults to 1, because looking at all the fex
files in sunxi-boards, that is by far the most used value.
This commit updated the Ippo and MSI Primo73 tablet defconfigs to override the
default of 1 with 0, as that is the correct value for those tablets, this
keeps the register settings the same as before this commit.
The Olinuxino-A13 defconfigs are not updated, changing the register setting
for these boards from 0 to 1, this is intentional.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Define two structure mx6sx_iomux_ddr_regs and mx6sx_iomux_grp_regs.
Add a new function mx6sx_dram_iocfg to configure dram io.
Since mx6sx only have one channel mmdc0, define a new empty macro MMDC1
to replace mmdc1->entry=value for mx6sx. And to other mx6 soc, MMDC1
effects as "mmdc1->entry=value".
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2 recent sunxi changes have removed the usage of lowlevel_init by moving some
code around and then setting CONFIG_SKIP_LOWLEVEL_INIT.
This is problematic for 2 reasons:
1) It does not just stop s_init from being called, it also stops
cpu_init_cp15 from getting called, which is undesirable.
2) We want u-boot.bin to be usable standalone, without SPL, some people e.g.
use an upstream u-boot.bin together with Allwinner's boot0 loader. So
u-boot.bin must (re)initialize the gpios, timer, etc.
This commit restores the lowlevel_init / s_init usage, while keeping the
changes to no longer use the global-data (gd) struct in the SPL.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This patch initializes VSC9953 L2 Switch for boards that have
CONFIG_VSC9953 defined in their config file.
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Implement MIPS specific setup of the gd_t structure to support
pre-relocation malloc. If CONFIG_SYS_MALLOC_F_LEN is specified,
a memory area will be reserved after the initial stack area and
the gd->malloc_base pointer will be initialized.
After this patch the new driver model can be used on MIPS.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Support the existing config option CONFIG_SYS_INIT_SP_ADDR on
MIPS. This allows to move the initial stack to other places
than the beginning of RAM.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Conditionally set head-y and lib-y with boolean Kconfig symbols
for selected CPU. This deprecates the usage of the $(CPU) variable.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
The common code just needs the C0_COUNT as free running counter,
without the need of writing and checking C0_COMPARE.
The function get_tbclk() is still implemented here instead of changing
all places of CONFIG_SYS_MIPS_TIMER_FREQ to CONFIG_SYS_TIMER_RATE.
The change was tested on a MIPS32 system, but as the MIPS64 code
was/is the same, this should be no problem.
Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Add the initial code to prepare a flattened device tree for
the kernel like relocating the FDT blob and fixing up the
/chosen and /memory nodes.
The final hand over to the kernel is not yet implemented. After
the community agreed on the MIPS boot interface for device trees,
the corresponding code will be added.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
If the user wants to boot a kernel without legacy environment,
information like memory size, initrd address and size should be
handed over to the kernel in the command line.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Move preparation of Linux kernel environment in a separate
function and mark it as legacy. Add a Kconfig option to make
that legacy mode configurable.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Move preparation of Linux kernel command line in a separate
function and mark it as legacy. Add a Kconfig option to make
that legacy mode configurable.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
The global_data pointer (gd) has already been set before board_init_f()
is called. We should not assign it again. We should also not use gdata since
it is going away.
Signed-off-by: Simon Glass <sjg@chromium.org>
in thumb mode compiler says for example for arch/arm/lib/cache-cp15.c
when enabling CONFIG_SYS_THUMB_BUILD:
{standard input}: Assembler messages:
{standard input}:373: Error: selected processor does not support Thumb mode `mrc p15,0,r4,c1,c0,0'
{standard input}:416: Error: selected processor does not support Thumb mode `mcr p15,0,r3,c2,c0,0'
so, if caches are disabled, do not use this command on arm926ejs.
used on at91 in SPL, to reduce size of SPL.
Signed-off-by: Heiko Schocher <hs@denx.de>
This patch adds the new Barco platinum platform. It currently
includes those two boards:
platinum-titanium
-----------------
This is the same board as the titanium that is already supported in
mainline U-Boot. But its now moved to this new platform to support
multiple "flavors" of imx6 boards in one directory. Its also moved
to support SPL booting. And with this we use the run-time DDR
configuration of this SPL support. The board is equipped with the
Micron MT41J128M16JT-125 DDR chips. We now can remove the DDR
related registers tuples from the imximage.cfg file. As all this
is done in the SPL at run-time.
platinum-picon
--------------
This board is new and based on the MX6DL with 1GiB DDR using the
Micron MT41K256M16HA DDR3 chips. Its also equipped with 2 NAND
chips (each 512MiB).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Pieter Ronsijn <pieter.ronsijn@barco.com>
This does nothing now, so drop it. We have SPL anyway to do our low-level
init.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The current sunxi implementation uses gdata, which is going away. It also
sets up DRAM before board_init_f() in SPL.
There is really no reason to do much in s_init() since board_init_f() is
called immediately afterwards. The only change is that we need our own
implementation of board_init_f() which sets up DRAM before the BSS (which
is in DRAM) is cleared.
The s_init() code runs once for SPL and again for U-Boot proper. We
shouldn't need to init the clock/timer/gpio/i2c init twice, so just have it
in SPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
We need to get rid of this SPL-specific setting of the global_data pointer.
It is already set up in start.S immediately before board_init_f() is called,
and there may be information there that is needed (e.g. pre-reloc malloc
info).
Signed-off-by: Simon Glass <sjg@chromium.org>
Prior to this change we set the gd pointer early so that we can store
data in it. This becomes problematic for DM changes as well as being
odd in general. Re-work the code paths so that we don't need to set the
gd pointer so early and instead can rely upon the normal setting of it.
In order to do this we do need to move certain calls from s_init into
spl_board_init(), mainly preloader_console_init and
save_omap_boot_params.
Tested on: Beaglebone Black, AM43xx GP EVM, Beagleboard, Beagleboard xM,
OMAP5 uEVM, DRA7xx EVM
Signed-off-by: Tom Rini <trini@ti.com>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Some Freescale SoCs like T1020 and T1040 have an integrated
L2 Switch. The L2 Switch ports may be connected to Ethernet PHYs
over SGMII and QSGMII.
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The number of supported serdes protocols on Freescale SoCs
has increased over time. Until now, an u64 variable have been
initialized on boot with the configured protocols. However,
since this number has increased (enum srds_prtcl has more
than 64 values), 64 bits are no longer sufficient to hold track
of all the configured protocols.
This patch replaces the u64 map values with static arrays.
To keep track of the number of serdes protocols, the
SERDES_PRCTL_COUNT vale has been added at the end of
enum srds_prtcl. This value must always be the last one.
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
All the boards that support deep sleep feature are converted
to deep sleep generic board interface. The old interface which
support non-generic board is not used anymore. So clean it up.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
CONFIG_SYS_PBI_FLASH_BASE is defined for Secure Boot on C29X
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
For B4 the LIODN register for PCIe is in PCIe address space and not in
GUTs
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled.
It includes <asm/gpio.h> and then <asm/gpio.h> includes
<asm/arch/gpio.h>. As a result, all the SoCs that enable
CONFIG_OF_CONTROL must have <asm/arch/gpio.h>.
The right fix would be to split the lib/fdtdec.c to remove
dependency on GPIO.
This commit adds a dummy <asm/arch/gpio.h> to support OF_CONTROL
for mpc85xx platform. A file mpc85xx_gpio.h exists in
arch/powerpc/include/asm. The defintions in that file conflict
with the ones in asm-generic/gpio.h. Hence a dummy header file
has been added. This will be removed after FDT-GPIO stuff is
fixed correctly.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
All the 74xx_7xx boards are still non-generic boards:
P3G4, ZUMA, ppmc7xx, ELPPC, mpc7448hpc2
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: York Sun <yorksun@freescale.com>
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Nye Liu <nyet@zumanetworks.com>
Cc: Roy Zang <tie-fei.zang@freescale.com>
Now TQM8xx is the only remaining board family of mpc8xx.
It uses its own linker script, board/tqc/tqm8xx/u-boot.lds.
arch/powerpc/cpu/mpc8xx/u-boot.lds is not used by any boards.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Since commit 843125daeb (ppc4xx: remove HH405 board), CONFIG_HH405
is not defined.
Since commit d526330479 (ppc4xx: remove PMC405), CONFIG_PMC405
is not defined.
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Matthias Fuchs <matthias.fuchs@esd.eu>
As a preparation to ARCv2 port submission we rename "arc700" folder to
"arcv1" which stands for ARCv1 ISA also known as ARCompact.
This will allow us to add more flavours of binary-compatible ARCv1 CPUs
like ARC600 if needed later on and all required ARCv2 CPUs (which are
binary incompatible with ARCv1) in "arcv2" folder in subsequent commits.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
Both ARCangel4 and AXS10x are FPGA-based boards so they may have
different CPUs. For now we have only 1 option (ARC700) and we define
this as default in arch Kconfig.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
"reset.c" and "cpu.c" have no architecture-specific code at all.
Others are applicable to either ARC CPU.
This change is a preparation to submission of ARCv2 architecture port.
Even though ARCv1 and ARCv2 ISAs are not binary compatible most of
built-in modules still have the same programming model - AUX registers
are mapped in the same addresses and hold the same data (new featues
extend existing ones).
So only low-level assembly code (start-up, interrupt handlers) is left
as CPU(actually ISA)-specific. This significantyl simplifies maintenance
of multiple CPUs/ISAs.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
* use better symbols for relocatable region boundaries
("__image_copy_start" instead of "CONFIG_SYS_TEXT_BASE")
* remove useless debug messages because they will only show up in case
of both problem (when normal "if" branch won't be taken) and DEBUG take
place which is pretty rare situation.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Even though existing implementation works fine in preparation to
submission of ARCv2 architecture we need this change.
In case of ARCv2 interrupt vector table consists of just addresses
of corresponding handlers. And if those addresses will be in .text
section then assembler will encode them as everything in .text section
as middle-endian and then on real execution CPU will read swapped
addresses and will jump into the wild.
Once introduced new section is situated so .text section remains the
first which allows us to use common linker option for linking everything
to a specified CONFIG_SYS_TEXT_BASE.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
Depending on MMU presence in CPU there're differences in HW behavior.
For example address of instruction that caused exception is put in
ECR register if MMU exists and in ERET register otherwise.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
To disable interrupts we need to reset corresponding flags in STATUS32
register. For this we need to OR flags for interrupts level1 and level2
and then AND with current value in STATUS32.
Before that implementation was incorrect.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
Exception cause register (ECR) contains value that describes a reason
for exception that has happened. This helps a lot to figure-out what
went wrong.
Now we print this register contents when dumping registers.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
Some cache operations ({i|d}cache_{enable|disable|status} or
flush_dcache_all) are built and used even if CONFIG_SYS_{I|D}CACHE_OFF
is set.
This is required for force disable of caches on early boot.
What if something was executed before U-boot and enabled caches
(low-level bootloaders, previously run kernel etc.)?
But if CPU doesn't really have caches any attempt to access
cache-related AUX registers triggers instruction error exception.
So for convenience we'll try to avoid exceptions by checking if CPU
actually has caches (we check separately data and instruction cache
existence) at all.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
The axp221 / axp223's N_VBUSEN pin can be configured as an output rather
then an input, and this is used on some boards to control usb-vbus0, add
support for this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Most of the usb-controller init code found in ehci-sunxi.c also is necessary
to init the otg usb controller, so move it to a common place.
While at it also update various #ifdefs / defines for sun8i support.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
"adr rX, text_end" only works if the label is close. Adding further code
to the other functions will prevent this. So move the containing
function close to label. No functional change.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Based on the original version by Marc Zyngier. It adds a psci_cpu_off
implementation for the A20 SoC. The mechanism works by first preparing
the calling CPU to go offline (disable and flush cache, disable SMP),
then requesting CPU 0 to pull the plug. The request is sent as FIQ on
SGI15.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add support for VGA directly from the sunxi SoC / display engine.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add lcd output support, see the new Kconfig entries and doc/README.video for
how to enable / configure this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Modify sunxi_lcdc_pll_set to work with both tcon0 and tcon1, this is a
preparation patch for adding lcd support.
While at it also swap the divider search order, searching from low to
high, as the comment above the code says we should do. In cases where there
are multiple solutions this will result in picking a lower pll clock and
divider, which is more stable and saves power.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Some boards use GPIO-s on the pmic, one example of this is the A13-OLinuXino
board, which uses gpio0 of the axp209 for the lcd-power signal.
This commit adds support for gpio pins on the AXP209 pmic, the sunxi_gpio.c
changes are universal, adding gpio support for the other AXP pmics (when
necessary) should be a matter of adding the necessary axp_gpio_foo functions
to their resp. drivers, and add "#define AXP_GPIO" to their header file.
Note this commit only adds support for the non device-model version of the
gpio code, patches for adding support to the device-model version are very
welcome.
The string representation for these gpio-s is AXP0-#, the 0 in the AXP0 prefix
is there in case we need to support gpio-s on more then 1 pmic in the future.
At least A80 boards have 2 pmics, and we may end up needing to support gpio-s
on both.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Move a few mux defines around so that all the mux defines are properly sorted
by port number.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add a write to the "unknown" (*) register to enable auto input sync, when
initially adding sunxi hdmi output support this magic write from the android
kernel code was missed, causing lcdc -> hdmi encoder sync problems.
With this write added, we can drop the modesetting retries and the extra
delays added to work around these sync problems.
With the retries dropped there also is no need to 0 all the enable flags at
the beginning of the modeset, as they are initialized to 0 already by
engines_init.
*) "unknown" is the actual name of this register in the android kernel sources
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Anatolij Gustschin <agust@denx.de>
So far we've been programming the hdmi-encoder to send out dvi data over the
hdmi connector. This works well for most devices, including hdmi devices, but
not all devices accept dvi data on a hdmi input.
Add support for sending proper hdmi data over the hdmi output found on most
sunxi boards. This can be turned on by adding monitor=hdmi as option to the
video-mode env. variable.
A follow up patch will determine whether to send dvi or hdmi automatically when
EDID is used.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Anatolij Gustschin <agust@denx.de>
Add DDC & EDID support and use it to automatically select the native mode of
the attached monitor. This can be disabled by adding edid=0 as option
to the video-mode env. variable.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Anatolij Gustschin <agust@denx.de>
PLL1 on sun6i / sun8i also has a p factor which divides the clock by
2^p (to the power p). On sun6i the p factor is ignored, but on sun8i it is
used and we were setting it to 1, resulting in the CPU running at 504 MHz
instead of 1008 MHz, this commit fixes this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
After reboot, reset or even short power off, DRAM typically retains
the old stale data for some period of time (for this type of memory,
the bits of data are stored in slowly discharging capacitors).
The current sun6i/sun8i DRAM size detection logic, which is
inherited from the Allwinner code, relies on using a large magic
signature with the hope that it is unique enough and unlikely to
ever accidentally match this leftover garbage data in RAM. But
this approach is inherently unsafe, as can be demonstrated using
the following test program:
/***** A testcase for reproducing the problem ******/
void main(int argc, char *argv[])
{
size_t size, i;
uint32_t *buf;
/* Allocate the buffer */
if (argc < 2 || !(size = (size_t)atoi(argv[1]) * 1048576) ||
!(buf = malloc(size))) {
printf("Need buffer size in MiB as a cmdline argument\n");
exit(1);
}
/* Fill it with the Allwinner DRAM "magic" values */
for (i = 0; i < size / 4; i++)
buf[i] = 0xaa55aa55 + ((uintptr_t)&buf[i] / 4) % 64;
/* Try to reboot */
system("reboot");
/* And wait */
for (;;) {}
}
/***************************************************/
If this test program is run on the device (giving it a large
chunk of memory), then the DRAM size detection logic in u-boot
gets confused after reboot and fails to initialize DRAM properly.
A better approach is not to rely on luck and abstain from making
any assumptions about the properties of the leftover garbage
data in RAM. Instead just use a more reliable code for testing
whether two different addresses refer to the same memory location.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Based on the register / dram_para headers from the Allwinner u-boot / linux
sources + the init sequences from boot0.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The sun8i boot0 code fills the DRAM with a "random" pattern before comparing
it at different offsets to do columns, etc. detection. The sun6i boot0 code
does not do it, instead relying on the memory contents being random enough
to begin with for the memcmp to properly detect the wrap-around address, iow
it is working purely by chance. Since our sun6i dram code was modelled after
the boot0 code it contained the same issue.
This commit fixes this by filling the memory with a unique, distinct pattern.
The new mctl_mem_fill function this introduces is added as an inline helper
in dram.h, so that it can be shared with the sun8i dram code.
While at it move mctl_mem_matches to dram.h for re-use in sun8i too.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The await_completion helper is already copy pasted between the sun4i and sun6i
dram code, and we need it for sun8i too, so lets make it an inline helper in
dram.h, rather then adding yet another copy.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Our old hardcoded k and m values are based on PLL5 being configured in steps
of 48 MHz, which is correct for sun6i where the DRAM PLL runs at twice the
DRAM CLK, which is usually configured in 24 MHz step. But on the A23 (sun8i)
the PLL5 runs at half the DRAM CLK, so we require 12 MHz steps.
This commit adjusts clock_set_pll5 to automatically select the best k and m
depending on the requested clk rate.
Suggested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The sun8i dram code sometimes wants to enable sigma delta mode,
add a parameter to allow this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The axp223 appears to be the same as the axp221, except that it uses the
rsb to communicate rather then the p2wi. At least all the registers we use
are 100% the same.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
sun8i (A23) introduces a new bus for communicating with the pmic, the rsb,
the rsb is also used to communicate with the pmic on the A80, and is
documented in the A80 user manual.
This commit adds support for this based on the rsb driver from the allwinner
u-boot sources.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The p2wi interface is only available on sun6i, adjust the gpio pinmux and
base address defines for it to reflect this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
0x400 is true 1K.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
On sun6i the SID is stored in the pmic, rather then in the SoC itself,
add a helper function to abstract this away.
This makes our MAC address generation code also work on sun6i.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The sunxi mmc controller has both an internal clock divider, as well as
the divider in the mod0-clk for the mmc controller.
The internal divider cannot be used, as it conflicts with the setting of
clock sampling phases which is done in the mod0-clk, so it must be set to
0 (divide by 1).
For some reason while the kernel has had this correct from day one, the
u-boot sunxi mmc code has been using a fixed mod0-clk and setting its
internal divider depending on the desired speed. This is something which
we've inherited from the original Allwinner u-boot sources, but while this
has been fixed in Allwinner's own u-boot code at least for the A23 and later
upstream u-boot was still doing this wrong.
This commit fixes this, thereby also fixing mmc support not working reliable
on the A23 (which seems more sensitive to this) and possible also fixes some
other sunxi mmc issues.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The A31s only has one dram channel, so do not bother with trying to initialize
a second channel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add a sunxi_get_ss_bonding_id() function, and use it to differentiate between
the A31s and the A31.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
It turns out that there is a too large spread between boards to handle this
with a default value, turn this into Kconfig options, and set the values
the factory images are using for the Colombus and Mele_M9 boards.
Note this changes the ZQ default when not overriden through defconfig from
120 to 123, as that is what most boards seem to actually use.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Switch to using hardware leveling for certain parameters on the EMIF
rather than using precalculated values. Doing this also means we have a
common place now between am437x and am335x for setting
emif_sdram_ref_ctrl with a value for the correct delay length.
Tested-by: Felipe Balbi <balbi@ti.com>
Tested-by: Tom Rini <trini@ti.com>
Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Configure coreboot pci memory regions so that pci device drivers
could work correctly.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link
which is currently the only real board officially supported to run
U-Boot loaded by coreboot.
Note the symbolic link file chromebook_link.dts is deleted and
link.dts is renamed to chromebook_link.dts.
To avoid multiple definition of video_hw_init, the CONFIG_VIDEO_X86
define needs to be moved to arch/x86/cpu/ivybridge/Kconfig.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
There are many places in the U-Boot source tree which refer to
CONFIG_SYS_COREBOOT, CONFIG_CBMEM_CONSOLE and CONFIG_VIDEO_COREBOOT
that is currently defined in coreboot.h.
Move them to arch/x86/cpu/coreboot/Kconfig so that we can switch
to board configuration file to build U-Boot later.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
When CONFIG_X86_RESET_VECTOR is not selected, specifying the ROM chip
size is meaningless, hence hide it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Convert CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig
options so that we can remove them from board configuration file.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
By default U-Boot automatically calibrates TSC running frequency via
MSR and PIT. The calibration may not work on every x86 processor, so
a new Kconfig option CONFIG_TSC_CALIBRATION_BYPASS is introduced to
allow bypassing the calibration and assign a hardcoded TSC frequency
CONFIG_TSC_FREQ_IN_MHZ.
Normally the bypass should be turned on in a simulation environment
like qemu.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
If coreboot is built with CONFIG_COLLECT_TIMESTAMPS, use the value
of base_time in coreboot's timestamp table as our timer base,
otherwise TSC counter value will be used.
Sometimes even coreboot is built with CONFIG_COLLECT_TIMESTAMPS,
the value of base_time in the timestamp table is still zero, so
we must exclude this case too (this is currently seen on booting
coreboot in qemu).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
These two are not worth having separate inline functions as they are
really simple, so drop them.
Also changed 'type' parameter of fsp_get_next_hob() from u16 to uint.
Suggested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
It is useful to be able to see the MTRR setup in U-Boot. Add a command
to list the state of the variable MTRR registers and allow them to be
changed.
Update the documentation to list some of the available commands.
This does not support fixed MTRRs as yet.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
At present the normal update (which happens much later) does not work. This
seems to have something to do with the 'no eviction' mode in the CAR, or at
least moving the microcode update after that causes it not to work.
For now, do an update early on so that it definitely works. Also refuse to
continue unless the microcode update check (later in boot) is successful.
Signed-off-by: Simon Glass <sjg@chromium.org>
For platforms with CAR we should disable it before relocation. Check if
this function is available and call it if so.
Signed-off-by: Simon Glass <sjg@chromium.org>
Cache-as-RAM should be turned off when we relocate since we want to run from
RAM. Add a function to perform this task.
Signed-off-by: Simon Glass <sjg@chromium.org>
Once we stop running from ROM we should set up the MTTRs to speed up
execution. This is only needed for platforms that don't have an FSP.
Also in the Coreboot case, the MTRRs are set up for us.
Signed-off-by: Simon Glass <sjg@chromium.org>
We should use MTRRs to speed up execution. Add a list of MTRR requests which
will dealt with when we relocate and run from RAM.
We set RAM as cacheable (with write-back) and registers as non-cacheable.
Signed-off-by: Simon Glass <sjg@chromium.org>
Set the frame buffer to write-combining. This makes it faster, although for
scrolling write-through is even faster for U-Boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Memory Type Range Registers are used to tell the CPU whether memory is
cacheable and if so the cache write mode to use.
Clean up the existing header file to follow style, and remove the unneeded
code.
These can speed up booting so should be supported. Add these to global_data
so they can be requested while booting. We will apply the changes during
relocation (in a later commit).
Signed-off-by: Simon Glass <sjg@chromium.org>
This is set up along with CAR (Cache-as-RAM) anyway. When we relocate we
don't really need ROM caching (we read the VGA BIOS from ROM but that is
about it)
Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
There are some bits which should be ignored when displaying the mode number.
Make sure that they are not included in the mode that is displayed.
Signed-off-by: Simon Glass <sjg@chromium.org>
There is no need to run with the cache disabled, and there is no point in
clearing the display frame buffer since U-Boot does it later.
Signed-off-by: Simon Glass <sjg@chromium.org>
This takes about about 700ms on link when running natively and 900ms when
running using the emulator. It is a waste of time if video is not enabled,
so don't bother running the video BIOS in that case.
We could add a command to run the video BIOS later when needed, but this is
not considered at present.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We don't need this in U-Boot since we calculate it based on available memory.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The Topcliff PCH has 4 UART devices integrated (Device 10, Funciton
1/2/3/4). Add the corresponding device nodes in the crownbay.dts per
Open Firmware PCI bus bindings.
Also a comment block is added for the 'stdout-path' property in the
chosen node, mentioning that by default the legacy superio serial
port (io addr 0x3f8) is still used on Crown Bay as the console port.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Use ePAPR defined properties for x86-uart: clock-frequency and
current-speed. Assign the value of clock-frequency in device tree
to plat->clock of x86-uart instead of using hardcoded number.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Remove the troublesome union hob_pointers so that some annoying casts
are no longer needed in those hob access routines. This also improves
the readability.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Introduce a gd->hose to save the pci hose in the early phase so that
apis in drivers/pci/pci.c can be used before relocation. Architecture
codes need assign a valid gd->hose in the early phase.
Some variables are declared as static so change them to be either
stack variable or global data member so that they can be used before
relocation, except the 'indent' used by CONFIG_PCI_SCAN_SHOW which
just affects some print format.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
On x86, some peripherals on pci buses need to be accessed in the
early phase (eg: pci uart) with a valid pci memory/io address,
thus scan the pci bus and do the corresponding resource allocation.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
arch/x86/cpu/pci.c has access to the U-Boot global data thus
DECLARE_GLOBAL_DATA_PTR is needed.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commits cleans up the board dts files.
- Correct the serial port register size to 8
- Remove the misleading status = "disabled" statement in the
serial.dtsi
- Move the inclusion of skeleton.dtsi from serial.dtsi to board
dts files
- Let the board dts file define stdout-path in the chosen node
- Remove device nodes in board dts files thar are duplicated to
skeleton.dtsi
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
The name of coreboot.dtsi is misleading, as it actually describes
the legacy serial port device node.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
MetaWare debugger (MDB) is still used as a primary tool for interaction
with target via JTAG. Moreover some very advanced features are not yet
implemented in GDB for ARC (and not sure if they will be implemnted
sometime soon given complexity and rare need for those features for
common user).
So if we're talking about development process when U-Boot is loaded in
target memory not by low-level boot-loader but manually through JTAG
chances are high developer uses MDB for it.
But MDB doesn't support PIE (position-independent executable) - it will
refuse to even start - that means no chance to load elf contents on
target.
Then the only way to load U-Boot in MDB is to fake it by:
1. Reset PIE flag in ELF header
This is simpe - on attempt to open elf MDB checks header and if it
doesn't match its expectation refuces to use provided elf.
2. Strip all debug information from elf
If (1) is done then MDB will open elf but on parsing of elf's debug
info it will refuse to process due to debug info it cannot understand
(symbols with PIE relocation).
Even though it could be done manually (I got it documented quite a while
ago here http://www.denx.de/wiki/U-Boot/ARCNotes) having this automated
way is very convenient. User may build U-Boot that will be loaded on
target via MDB saying "make mdbtrick".
Then if we now apply the manipulation MDB will happily start and will
load all required sections into the target.
Indeed there will be no source-level debug info available. But still MDB
will do its work on showing disassembly, global symbols, registers,
accessing low-level debug facilities etc.
As a summary - this is a pretty dirty hack but it simplifies life a lot
for us ARc developers.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Resynchronize memcpy/memset with kernel 3.17 and build them in
Thumb2 mode (unified syntax). Those assembler files can be built
and linked in ARM mode too, however when calling them from Thumb2
built code, the stack got corrupted and the copy did not succeed
(the exact details have not been traced back). However, the Linux
kernel builds those files in Thumb2 mode. Hence U-Boot should
build them in Thumb2 mode too when CONFIG_SYS_THUMB_BUILD is set.
To build the files without warning, some assembler instructions
had to be replaced with their UAL compliant variant (thanks
Jeroen for this input).
To build the file in Thumb2 mode the implicit-it=always option need
to be set to generate Thumb2 compliant IT instructions where needed.
We add this option to the general AFLAGS when building for Thumb2.
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Since commit 3ff46cc42b ("arm: relocate the exception vectors") mx25pdk
hangs like this:
CPU: Freescale i.MX25 rev1.2 at 399 MHz
Reset cause: WDOG
Board: MX25PDK
I2C: ready
DRAM: 64 MiB
(hangs)
Add a specific relocate_vectors macro that skips the vector relocation, as the
i.MX25 SoC does not provide RAM at the high vectors address (0xFFFF0000), and
(0x00000000) maps to ROM.
This allows mx25 to boot again.
Acked-By: Bill Pringlemeir <bpringlemeir@nbsps.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Currently there is an unneeded empty line after printing the reset cause:
U-Boot 2015.01-rc4-00080-g0551a93 (Jan 06 2015 - 13:04:19)
CPU: Freescale i.MX25 rev1.2 at 399 MHz
Reset cause: POR
Board: MX25PDK
I2C: ready
DRAM: 64 MiB
MMC: FSL_SDHC: 0
Remove the extra "\n" when printing the reset cause.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
The low-level debugging functions are useful to debug the early boot
stage where the full UART driver is not available.
UniPhier SoCs need to initialize the UART port 0 to use this feature.
The initialization routine is called at the very entry of the
lowlevel_init().
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
For NAND boot on PH1-LD4, PH1-sLD8, and some other SoCs,
the output of the system bus is disabled by default.
It must be enabled by software to have access to the system bus.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
The max size of available memories on slot0 and slot1 is 32MB because
- EA[25] signal is not output on the save-pin mode which is
used PH1-LD4 or later SoCs.
- EA[25] signal is not connected by the limitation (or bug?) of
the PLD logic of DCC support card.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This optional DT property is called 'num-cs', so repair the misnomers.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Linux now also contains SPI driver, yet the name is 'snps,dw-apb-ssi'.
Fix the naming before we have to support both names.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
The ChromeOS EC keyboard is used by various different chromebooks. Peach
pi being the third board in the u-boot tree to use it (snow and peach
pit the other two). Rather then embedding the same big DT node in the
peach-pi DT again, copy the dtsi snippit & bindings documentation from
linux and include it in all 3 boards.
This slightly changes the dt bindings in u-boot:
* google,key-rows becomes keypad,num-rows
* google,key-colums becomes keypad,num-colums
* google,repeat-delay-ms and google,repeat-rate-ms are no longer used
and replaced by hardcoded values (similar to tegra kbc)
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
pci ports are used as root complex in Linux. So set this as default
in u-boot for keystone devices
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
On OMAP platforms (like OMAP5) Linux kernel fails to detect a SATA
device if it is used by U-Boot.
It happens because U-Boot does not reset SATA controller before boot.
Reset the controller on OS boot so that Linux will have a clean state
to work with.
Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
Reviewed-by: Tom Rini <trini@ti.com>
Part of DMM logic is reuse from commit
47a4bea6af ("ARM: omap4: Update sdram
setting for panda rev A6") Which broke SDP4430 with ES2.3 (uses old
DDR).
So, to maintain support for newer DDR used in Panda ES rev B3, we
should, in addition to the commit
675cc77a3a ("ARM:OMAP4+: panda-es: Support
Rev B3 Elpida DDR2 RAM"), DDR timings, also do DMM configuration
specific to Panda.
Signed-off-by: Nishanth Menon <nm@ti.com>
The gd will be cleared at first so we don't need to set arch.tbl to 0.
In addition, the checks later against lastinc also work fine with an
initial value of 0 here. This also brings us in line with sunxi code
for example.
Signed-off-by: Tom Rini <trini@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
In both SPL and non-SPL cases we will make a call to timer_init() early
on and do not need to call it again within s_init().
Signed-off-by: Tom Rini <trini@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The save_boot_params function here is the same as the default weak one
from arch/arm/cpu/armv7/start.S, drop.
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Commit 8bc347e2ec "ARM: bootm: Allow booting in secure mode on hyp capable
systems" added the capability to select nonsec vs sec mode boot via an
environment var.
There is a subtle gotcha with this functionality, which is that the PSCI nodes
are still created in the fdt (via armv7_update_dt->fdt_psci) even when booting
in secure mode. Which means that if the kernel is PSCI aware then it will fail
to boot because it will try and do PSCI from secure world, which won't work.
This likely didn't get noticed before because the original purpose was to
support booting the legacy linux-sunxi kernels which don't understand PSCI.
To fix expose boot_nonsec (renaming with armv7_ prefix) outside of bootm.c and
use from the virt-dt code.
As well as avoiding the creation of the PSCI nodes we should also avoid
reserving the secure RAM, so do so.
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
All the MPC824X boards are still non-generic boards:
A3000, CPC45, CU824, eXalion, MVBLUE, MUSENKI, Sandpoint824x, utx8245
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Josef Wagner <Wagner@Microsys.de>
Cc: Torsten Demke <torsten.demke@fci.com>
Cc: Jim Thompson <jim@musenki.com>
Cc: Greg Allen <gallen@arlut.utexas.edu>
These boards are still non-generic boards.
drivers/rtc/ds12887.c should also be removed because it can not
be built without CONFIG_ATC.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
This board is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
This board is still a non-generic board.
Unused code in arch/powerpc/cpu/mpc8xx/video.c should be also deleted
because CONFIG_VIDEO_ENCODER_AD7176, CONFIG_VIDEO_ENCODER_AD7177,
CONFIG_VIDEO_ENCODER_AD7179 are not defined any more.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
These boards are still non-generic boards.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Stefan Roese <sr@denx.de>
The malloc() calls are unnecessary, just allocate the stuff on stack.
While at it, reorder the code a little, so that only one variable is
used for the text, use snprintf() instead of sprintf() and use %01d
as a formatting string to avoid any possible overflows.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Sean Cross <xobs@kosagi.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
This commit adds a dump command of DDR PHY parameters of UniPhier
SoC family. It might not be used very often for the regular operation
but it would be useful when something goes wrong with DDR memories.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This training code provides run-time adjustment of DDR PHY parameters
for stable DDR operation.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
enable this clock with the following:
clk_usb_otg_enable((void *)HSOTG_BASE_ADDR)
Signed-off-by: Steve Rae <srae@broadcom.com>
Reviewed-by: Felipe Balbi <balbi@ti.com>
Add a board rev entry for the new model A+, and augment the board
rev error handling code to be a bit more verbose.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
By rearranging the functions in the semihosting code we can
avoid forward-declaration of the internal static functions.
This puts the stuff in a logical order: read/open/close/len
and then higher-order functions follow at the end.
Cc: Darwin Rambo <drambo@broadcom.com>
Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Mark Hambleton <mark.hambleton@arm.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Steve Rae <srae@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
There is currently a regression when using newer ARM64 compilers
for semihosting: the way long types are inferred from context
is no longer the same.
The semihosting runtime uses long and size_t, so use this
explicitly in the semihosting code and interface, and voila:
the code now works again.
Tested with aarch64-linux-gnu-gcc: Linaro GCC 4.9-2014.09.
Cc: Darwin Rambo <drambo@broadcom.com>
Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Mark Hambleton <mark.hambleton@arm.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Steve Rae <srae@broadcom.com>
Suggested-by: Mark Hambleton <mark.hambleton@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The semihosting code exposes internal file handle handling
functions to read(), open(), close() and get the length of
a certain file handle.
However the code using it is only interested in either
reading and entire named file into memory or getting the
file length of a file referred by name. No file handles
are used.
Thus make the file handle code internal to this file by
removing these functions from the semihosting header file
and staticize them.
This gives us some freedom to rearrange the semihosting
code without affecting the external interface.
Cc: Darwin Rambo <drambo@broadcom.com>
Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Mark Hambleton <mark.hambleton@arm.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Steve Rae <srae@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
MMC of exynos5420 can select SPLL as source clock, so add to support
SPLL in exynos5420_get_mmc_clk(). It was tested on Odroid-XU3 board.
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add samsung,vbus-gpio information for the XU3. This allows the usage of
the EHCI controller on the XU3, which is connected to the SMSC LAN9514
chip (usb hub + network).
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Not all exynos 5420 based devices with an LCD also have a parade LVDS
bridge. So make sure compilation doesn't break if CONFIG_LCD is enabled
and CONFIG_VIDEO_PARADE is not.
As a side-effect move the parade functions from the exynos system header
file to its own file.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Unlike the Peach-Pit board, there is no parade edp to lvds bridge on the
Pi. So drop it from device-tree
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds support for Odroid-XU3.
Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The current current watchdog timeout of 12 seconds is a bit small for
booting into Linux, especially when using a NFS based rootfs. So lets
change this timeout to a more defensive value of 30 seconds.
Also we now call the hw_watchdog_init() function so that we override
the value already configured from the Preloader.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
mxc_get_clock's return type is unsigned int. 'return -1' is same with
'return 0xffffffff', so 0 should be used as the return value when
unsupported mxc_clock type is passed to mxc_get_clock.
Also include an err message when unsupported mxc_clock type is passed
to mxc_get_clock.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
This is the follow-on patch to clean up the FSP support codes:
- Remove the _t suffix on the structures defines
- Use __packed for structure defines
- Use U-Boot's assert()
- Use standard bool true/false
- Remove read_unaligned64()
- Use memcmp() in the compare_guid()
- Remove the cast in the memset() call
- Replace some magic numbers with macros
- Use panic() when no valid FSP image header is found
- Change some FSP utility routines to use an fsp_ prefix
- Add comment blocks for asm_continuation and fsp_init_done
- Remove some casts in find_fsp_header()
- Change HOB access macros to static inline routines
- Add comments to mention find_fsp_header() may be called in a
stackless environment
- Add comments to mention init(¶ms) in fsp_init() cannot
be removed
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
There are two standard SD card slots on the Crown Bay board, which
are connected to the Topcliff PCH SDIO controllers. Enable the SDHC
support so that we can use them.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
The Crown Bay board has an SST25VF016B flash connected to the Tunnel
Creek processor SPI controller used as the BIOS media where U-Boot
is stored. Enable this flash support.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Intel Tunnel Creek GPIO register block is compatible with current
ich6-gpio driver, except the offset and content of GPIO block base
address register in the LPC PCI configuration space are different.
Use u16 instead of u32 to store the 16-bit I/O address of the GPIO
registers so that it could support both Ivybridge and Tunnel Creek.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
To avoid having two microcode formats, adjust the build system to support
obtaining the microcode from the device tree, even in the case where it
must be made available before the device tree can be accessed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Implement minimum required functions for the basic support to
queensbay platform and crownbay board.
Currently the implementation is to call fsp_init() in the car_init().
We may move that call to cpu_init_f() in the future.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Integrate the processor microcode version 1.05 for Tunnel Creek,
CPUID device 20661h.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
There are several problems in the code. The device tree decode is incorrect
in ways that are masked due to a matching bug. Both are fixed. Also
microcode_read_rev() should be inline and called before the microcode is
written.
Note: microcode writing does not work correctly on ivybridge for me. Further
work is needed to resolve this. But this patch tidies up the existing code
so that will be easier.
Signed-off-by: Simon Glass <sjg@chromium.org>
There are new microcode revisions available. Update them. Also change
the format so that the first 48 bytes are not omitted from the device tree
data.
Signed-off-by: Simon Glass <sjg@chromium.org>
We might end up with a few of these, so put them in their own directory.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Implement an API that can be used by drivers to allocate memory from a
pool that is mapped uncached. This is useful if drivers would otherwise
need to do extensive cache maintenance (or explicitly maintaining the
cache isn't safe).
The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting.
Boards can set this to the size to be used for the non-cached area. The
area will typically be right below the malloc() area, but architectures
should take care of aligning the beginning and end of the area to honor
any mapping restrictions. Architectures must also ensure that mappings
established for this area do not overlap with the malloc() area (which
should remain cached for improved performance).
While the API is currently only implemented for ARM v7, it should be
generic enough to allow other architectures to implement it as well.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The Jetson TK1 has an ethernet NIC connected to the PCIe bus and routes
the second root port to a miniPCIe slot. Enable the PCIe controller and
the network driver to allow the device to boot over the network.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add the device tree node for the PCIe controller found on Tegra124 SoCs.
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add a device tree node for the GIC v2 found on the Cortex-A15 CPU
complex of Tegra124. U-Boot doesn't use this but subsequent patches will
add device tree nodes that reference it by phandle.
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The Beaver has an ethernet NIC connected to the PCIe bus. Enable the
PCIe controller and the network device driver so that the device can
boot over the network.
In addition the board has a mini-PCIe expansion slot.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The PCIe bus on Cardhu is routed to the dock connector. An ethernet NIC
is available on the dock over the PCIe bus. Enable the PCIe controller
and the network device driver so that the device can boot over the
network.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add the device tree node for the PCIe controller found on Tegra30 SoCs.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add a device tree node for the GIC found on Tegra30. U-Boot doesn't use
it directly but subsequent patches will add device tree nodes that
reference it by phandle.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The TrimSlice has an ethernet NIC connected to the PCIe bus. Enable the
PCIe controller and the network driver so that the device can boot over
the network.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add the device tree node for the PCIe controller found on Tegra20 SoCs.
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add the PCIe and SATA lane configuration to the Jetson TK1 device tree,
so that the XUSB pad controller can be appropriately configured.
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The XUSB pad controller is used for pinmuxing of the XUSB, PCIe and SATA
lanes.
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This controller was introduced on Tegra114 to handle XUSB pads. On
Tegra124 it is also used for PCIe and SATA pin muxing and PHY control.
Only the Tegra124 PCIe and SATA functionality is currently implemented,
with weak symbols on Tegra114.
Tegra20 and Tegra30 also provide weak symbols for these functions so
that drivers can use the same API irrespective of which SoC they're
being built for.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Implement the powergate API that allows various power partitions to be
power up and down.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This reset is required for PCIe and the corresponding ID therefore needs
to be defined. The enumeration value for this was properly defined on
some SoCs but not on others. Similarly, some contained it in the mapping
of peripheral IDs to clock IDs, other didn't. This patch defines it
consistently for all supported SoC generations.
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This function is required by PCIe and SATA. This patch implements it on
Tegra20, Tegra30 and Tegra124. It isn't implemented for Tegra114 because
it doesn't support PCIe or SATA.
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The property name of the "aliases" node should be "serial*"
to assign a desired number for the device sequence number.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Not all portals might be managed and therefore visible.
Set the isdr register so that the corresponding isr register
won't be set. This is required when supporting power management.
Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Commit f29f804a93 generalized the TLB
mapping function, but made the DDR mapping leftover size to zero,
causing the message not printed.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Alexander Graf <agraf@suse.de>
CC: Scott Wood <scottwood@freescale.com>
Commit 65dd74a674 (x86: ivybridge: Implement SDRAM init) introduced
x86-specific asmlinkage into arch/x86/include/asm/config.h.
Commit ed0a2fbf14 (x86: Add a definition of asmlinkage) added the
same macro define again, this time, into include/common.h.
(Please do not add arch-specific stuff to include/common.h any more;
it is already too cluttered.)
The generic asmlinkage is defined in <linux/linkage.h>. If you want
to override it with an arch-specific one, the best way is to add it
to <asm/linkage.h> like Linux Kernel.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
FSP builds a series of data structures called the Hand-Off-Blocks
(HOBs) as it progresses through initializing the silicon. These data
structures conform to the HOB format as described in the Platform
Initialization (PI) specification Volume 3 Shared Architectual
Elements specification, which is part of the UEFI specification.
Create a simple command to parse the HOB list to display the HOB
address, type and length in bytes.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Per Intel FSP architecture specification, FSP provides 3 routines
for bootloader to call. The first one is the TempRamInit (aka
Cache-As-Ram initialization) and the second one is the FspInit
which does the memory bring up (like MRC for other x86 targets)
and chipset initialization. Those two routines have to be called
before U-Boot jumping to board_init_f in start.S.
The FspInit() will return several memory blocks called Hand Off
Blocks (HOBs) whose format is described in Platform Initialization
(PI) specification (part of the UEFI specication) to the bootloader.
Save this HOB address to the U-Boot global data for later use.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Use inline assembly codes to call FspNotify() to make sure parameters
are passed on the stack as required by the FSP calling convention.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
This is the initial import from Intel FSP release for Queensbay
platform (Tunnel Creek processor and Topcliff Platform Controller
Hub), which can be downloaded from Intel website.
For more details, check http://www.intel.com/fsp.
Note: U-Boot coding convention was applied to these codes, so it
looks completely different from the original Intel release.
Also update FSP support codes license header to use SPDX ID.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8)
are provided by a superio chip connected to the LPC bus. We must
program the superio chip so that serial ports are available for us.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Movie setup_pch_gpios() in the ich6-gpio driver to the board support
codes, so that the driver does not need to know any platform specific
stuff (ie: include the platform specifc chipset header file).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Move GD_BIST from lib/asm-offsets.c to arch/x86/lib/asm-offsets.c
as it is x86 arch specific stuff. Also remove GENERATED_GD_RELOC_OFF
which is not referenced anymore.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Currently the ROM_SIZE is hardcoded to 8MB in arch/x86/Kconfig. This
will not be the case when adding additional board support. Hence we
make ROM_SIZE configurable (512KB/1MB/2MB/4MB/8MB/16MB) and have the
board Kconfig file select the default ROM_SIZE.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
This converts all Tegra boards over to use driver model for I2C. The driver
is adjusted to use driver model and the following obsolete CONFIGs are
removed:
- CONFIG_SYS_I2C_INIT_BOARD
- CONFIG_I2C_MULTI_BUS
- CONFIG_SYS_MAX_I2C_BUS
- CONFIG_SYS_I2C_SPEED
- CONFIG_SYS_I2C
This has been tested on:
- trimslice (no I2C)
- beaver
- Jetson-TK1
It has not been tested on Tegra 114 as I don't have that board.
Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
Nyan-big is a Tegra124 clamshell board that is very similar to venice2, but
it has a different panel, the sdcard cd and wp sense are flipped, and it has
a different revision of the AS3722 PMIC.
This is the Acer Chromebook 13 CB5-311-T7NN (13.3-inch HD, NVIDIA
Tegra K1, 2GB). The display is not currently supported, so it should
boot on other nyan-based Chromebooks also, but only the device tree for
nyan-big is provided here.
The device tree file is from Linux but with features removed which are
unlikely to be supported in U-Boot soon (regulators, pinmux). Also the
addresses are updated to 32-bit.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
(rebase, change to 'nyan-big', fix pinmux that resets nyan-big)
Sync this up with Linux v3.18-rc5. Exclude features that are unlikely to
supported in U-Boot soon (regulators, pinmux). Also the addresses are
updated to 32-bit. Otherwise it is the same. Also bring in the dt-bindings
for pinctrl.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
This will be used by nyan-big, but bring it in in a separate patch since it
will be common to other boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add an I2C bus to the device tree, with an EEPROM emulator attached to one
of the addresses.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
To enable testing of I2C, add a simple I2C EEPROM simulator for sandbox.
It supports reading and writing from a small data store.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
As NOR/NAND/SD boot are all supported on LS1021AQDS/TWR
boards, the prompt message "Support ls1021aqds_nor" in
Kconfig is not clear. This patch changes it to
"Support ls1021aqds".
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
LS1 has 4 SMMUs for address translation of the masters. All the
SMMUs' stream IDs are 8-bit. The address translation depends on the
stream ID of the incoming transaction.
Each master has unique stream ID assigned to it and is configurable
through SCFG registers. The stream ID for the masters is identical
and share the same register field of STREAM ID registers.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The Central Security Unit (CSU) allows secure world software to
change the default access control policies of peripherals/bus
slaves, determining which bus masters may access them. This
allows peripherals to be separated into distinct security domains.
Combined with SMMU configuration of the system masters privileges,
these features provide protection against indirect unauthorized
access to data.
For now we configure all the peripheral access permissions as R/W.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Enable hypervisors utilizing the ARMv7 virtualization extension
on the LS1021A-QDS/TWR boards with the A7 core tile, we add the
required configuration variable.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Define the board specific smp_set_cpu_boot_addr() function to set
the start address for secondary cores in the LS1021A specific manner.
Define the board specific smp_kick_all_cpus() functioin to boot a
secondary core. Here the BRR contains control bits for enabling boot
for each core. On exiting HRESET or PORESET, the RCW BOOT_HO field
optionally allows for logical core 0 to be released for booting or to
remain in boot holdoff. All other cores remain in boot holdoff until
their corresponding bit is set.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
For some SoCs, the system clock frequency may not equal to the
ARCH Timer's frequency.
This patch uses the CONFIG_TIMER_CLK_FREQ instead of
CONFIG_SYS_CLK_FREQ, then the system clock macro and arch timer
macor could be set separately and without interfering each other.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
For some SoCs, the pen address register maybe in BE mode and the
CPUs are in LE mode.
This patch adds BE mode support for smp pen address.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
move usb device tree fixup code from "arch/powerpc/" to "drivers/usb/"
so that it works independent of architecture it is running on
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch adds NAND boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from NAND flash to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch adds QSPI boot support for LS1021AQDS/TWR board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then the booting will start from QSPI memory space.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch adds SD boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from SD card to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Add SUPPORT_SPL feature for SD and NAND boot on
LS1021AQDS and LS1021ATWR.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
On LS1, DDR is initialized by reading SPD through I2C interface
in SPL code. For I2C, ll_entry_count() is called, and it returns
the number of elements of a linker-generated array placed into
subsection of .u_boot_list section specified by _list argument.
So add I2C linker list in the generic .lds to fix the issue about
using I2C in SPL.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The patch changes PCIe dts node status to 'disabled' if the
corresponding controller is disabled according to serdes protocol.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
After wakeup from deep sleep, Clear EPU registers as early as possible
to prevent from possible issue. It's also safe to clear at normal boot.
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The bus frequency in SOC node should be clock frequency of platform.
That is not true if it is devided by 2.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
R-Mobile and R-Car ARM SoCs use sh_mmcif as MMC host driver.
This adds arch-rmobile/mmc.h that defines mmcif_mmc_init().
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
stv0991 architecture support added. It contains the support for
following blocks
- Timer
- uart
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
[trini: Add arch/arm/cpu/armv7/Makefile hunk]
Signed-off-by: Tom Rini <trini@ti.com>
Some UniPhier boards are equipped with an expansion slot that
some optional SRAM/NOR-flash cards can be attached to. So, run-time
detection of the number of flash banks would be more user-friendly.
Until this commit, UniPhier boards have achieved this by (ab)using
board_flash_wp_on() because the boot failed if flash_size got zero.
Fortunately, this problem was solved by commit 70879a9256 (flash:
do not fail even if flash_size is zero).
Now it is possible to throw away such a tricky workaround. This
commit also enables CONFIG_SYS_MAX_FLASH_BANKS_DETECT for further
refactoring.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
The macro __iomem is defined in include/linux/compiler.h.
Let's include it rather than double __iomem defines.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Sonic Zhang <sonic.adi@gmail.com>
Introduce a Makefile under arch/$ARCH/ and include it in the
top Makefile (similar to Linux kernel). This allows further
refactoringi like moving architecture-specific code out of global
makefiles, deprecating config variables (CPU, CPUDIR, SOC) or
deprecating arch/$ARCH/config.mk.
In contrary to Linux kernel, U-Boot defines the ARCH variable by
Kconfig, thus the arch Makefile can only included conditionally
after the top config.mk.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This board sprinkles #ifdef(CONFIG_HERMES) over various global files
such as include/common.h, common/board_r.c, common/cmd_bdinfo.c.
Let's zap such an ill-behaved board.
It has not been converted to generic board yet and mpc8xx is old
enough.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
The U-Boot port runs on a variety of RPi models, not just the B. So,
rename the port to something slightly more generic.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Detect the board revision early during boot, and print the decoded
model name.
Eventually, this information can be used for tasks such as:
- Allowing/preventing USB device mode; some models have a USB device on-
board so only host mode makes sense. Others connect the SoC directly
to the USB connector, so device-mode might make sense.
- The on-board USB hub/Ethernet requires different GPIOs to enable it,
although luckily the default appears to be fine so far.
- The compute module contains an on-board eMMC device, so we could store
the environment there. Other models use an SD card and so don't support
saving the environment (unless we store it in a file on the FAT boot
partition...)
Set $fdtfile based on this information. At present, the mainline Linux
kernel doesn't contain a separate DTB for most models, but I hope that
will change soon.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Some configurations have been moved to Kconfig and the difference
among the config headers of UniPhier SoC variants is getting smaller
and smaller. Now is a good time to merge them into a single file.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
There are two kinds of expansion boards which are often used for
the UniPhier platform and they are only exclusively selectable.
It can be better described by the "choice" menu of Kconfig.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This ugly work-around code is unnecessary since commit f09eb52b3f
(mtd: denali: set some registers after nand_scan_ident()).
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Correctly increment the base address of the freeze controller. And since
SYSMGR_FRZCTRL_VIOCTRL_SHIFT is not needed, remove it from the include file.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
socfpga_scan_manager structure was missing a data member.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
As suggested by Pavel, lets combine the two calls into one.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Without this alias, DM based probing does not work. So lets add this
alias to get the bus numbering correct for the Designware SPI
controllers.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Without this alias, DM based probing does not work. So lets add this
alias to get the bus numbering correct.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
This DT node is taken from the Rocketboard.org Linux repsitory. And
is needed to enable (configure) the Cadence DM SPI driver.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
The socfpga dts files are copied from the Rocketboards.org repository.
In U-Boot we usually replace the full-blown license header text with
the SPDX license identifiers. Lets do this for these new dts files
as well.
I just forgot to do this while adding the DT support for socfpga.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Newer qoriq socs have an updated dma ip block with a
different compatible. Let's make sure we use the proper
string so that the dmas get their liodn.
In order to have the means to specify the compatible
string, the liodn setting macros were updated to receive
a new parameter for it.
The following SoCs were changed to use the new compatible:
T1023/4, T1040, T2080/1, T4240, B4860.
Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Increase IO drive strength to fix FCS error on RGMII ports
on T1024QDS.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
fm_standard_init() initializes each 10G port by FM_TGEC_INFO_INITIALIZER.
but it needs different implementation of FM_TGEC_INFO_INITIALIZER on different SoCs.
on SoCs earlier(e.g. T4240, T2080), the notation between 10GEC and MAC as below:
10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2
on SoCs later(e.g. T1024, etc), the notation between 10GEC and MAC as below:
10GEC1->MAC1, 10GEC2->MAC2
so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to fit the new SoCs on
which 10GEC enumeration is consistent with MAC enumeration.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
T1024RDB is a Freescale Reference Design Board that hosts the T1024 SoC.
T1024RDB board Overview
-----------------------
- T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- CoreNet fabric supporting coherent and noncoherent transactions with
prioritization and bandwidth allocation
- 32-/64-bit DDR3L SDRAM memory controller with ECC and interleaving support
- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC
- Ethernet interfaces:
- Two 10M/100M/1G RGMII ports on-board
- one 10Gbps XFI interface
- PCIe: Three PCIe controllers: one PCIe Slot and two Mini-PCIe connectors.
- SerDes: 4 lanes up to 10.3125GHz
- IFC: 128MB NOR Flash, 512MB NAND Flash and CPLD
- eSPI: 64MB N25Q512 SPI flash.
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
- USB: Two Type-A USB2.0 ports with internal PHY
- eSDHC: Support SD, SDHC, SDXC and MMC/eMMC
- I2C: Four I2C controllers
- UART: Two UART serial ports
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: Fix ft_board_setup() type, fix MAINTAINERS for SECURE_BOOT
Fix Kconfig by adding SUPPORT_SPL]
Reviewed-by: York Sun <yorksun@freescale.com>
T1024QDS is a high-performance computing evaluation, development and
test platform for T1024 QorIQ Power Architecture processor.
T1024QDS board Overview
-----------------------
- T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- CoreNet fabric supporting coherent and noncoherent transactions with
prioritization and bandwidth allocation
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC
- Ethernet interfaces:
- Two 10M/100M/1G RGMII ports on-board
- Three 1G/2.5Gbps SGMII ports
- Four 1Gbps QSGMII ports
- one 10Gbps XFI or 10Base-KR interface
- SerDes: 4 lanes up to 10.3125GHz Supporting SGMII/QSGMII, XFI, PCIe, SATA and Aurora
- PCIe: Three PCI Express controllers with five PCIe slots.
- IFC: 128MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA
- Video: DIU supports video up to 1280x1024x32 bpp.
- Chrontel CH7201 for HDMI connection.
- TI DS90C387R for direct LCD connection.
- Raw (not encoded) video connector for testing or other encoders.
- QUICC Engine block
- 32-bit RISC controller for flexible support of the communications peripherals
- Serial DMA channel for receive and transmit on all serial channels
- Two universal communication controllers, supporting TDM, HDLC, and UART
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
- eSPI: Three SPI flash devices.
- SATA: one SATA 2.O.
- USB: Two USB2.0 ports with internal PHY (one Type-A + one micro Type mini-AB)
- eSDHC: Support SD, SDHC, SDXC and MMC/eMMC.
- I2C: Four I2C controllers.
- UART: Two UART on board.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: Fix ft_board_setup() type, fix MAINTAINERS for SECURE_BOOT
Fix Kconfig by adding SUPPORT_SPL]
Reviewed-by: York Sun <yorksun@freescale.com>
Add support for Freescale T1024/T1023 SoC.
The T1024 SoC includes the following function and features:
- Two 64-bit Power architecture e5500 cores, up to 1.4GHz
- private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC)
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI)
- High-speed peripheral interfaces
- Three PCI Express 2.0 controllers
- Additional peripheral interfaces
- One SATA 2.0 controller
- Two USB 2.0 controllers with integrated PHY
- Enhanced secure digital host controller (SD/eSDHC/eMMC)
- Enhanced serial peripheral interface (eSPI)
- Four I2C controllers
- Four 2-pin UARTs or two 4-pin UARTs
- Integrated Flash Controller supporting NAND and NOR flash
- Two 8-channel DMA engines
- Multicore programmable interrupt controller (PIC)
- LCD interface (DIU) with 12 bit dual data rate
- QUICC Engine block supporting TDM, HDLC, and UART
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0
Differences between T1024 and T1023:
Feature T1024 T1023
QUICC Engine: yes no
DIU: yes no
Deep Sleep: yes no
I2C controller: 4 3
DDR: 64-bit 32-bit
IFC: 32-bit 28-bit
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
XFI does not work stable on current board, it's due to heat sink issue,
to make it work stable the board needs additional heat sink, enable two
XFI lanes only. Right now we do not have such an erratum for the issue,
so use a define CONFIG_SYS_FSL_B4860QDS_XFI_ERR to identify it.
The workaround will only be used in XFI protocols and only if the
hwconfig indicates that XFI is prefered.
A new VSC3308 config function is used instead of re-use the original
function, to avoid making the function complex and ugly.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
T2080 v1.0 has this errata while v1.1 has fixed
this errata by hardware, add a new function has_errata_a007186
to check the SVR_SOC_VER, SVR_MAJ and SVR_MIN first,
if the sil has errata a007186, then run the errata code,
if not, doesn't run the code.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Workaround of Errata A-008044 was implemented without errata number and it is
enabled by default. Errata A-008044 is only valid for T1040 Rev 1.0.
So put errata number and make it conditional.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
When device is configured to load RCW from NAND flash IFC_A[16:31] are driven
low after RCW loading. Hence Devices connected on IFC_CS[1:7] and using
IFC_A[16:31] lines are not accessible.
Workaround is already in-place.
Put the errata number to adhere errata handling framework.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
T2080 rev 1.1 changes MEM_RAT in RCW, which requires new parsing for ratio,
the same way as T4240 rev 2.0.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Re-map NAND&I2C boot-device to the "normal" NAND boot-device.
Otherwise the SPL boot IF can't handle this device correctly.
Somehow booting with Hynix 4GBit NAND H27U4G8 on Siemens
Draco leads to this boot-device passed to SPL from the BootROM.
With this change, Draco boots just fine into main U-Boot.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Roger Meier <r.meier@siemens.com>
Cc: Samuel Egli <samuel.egli@siemens.com>
The infomation of module control register for R-Car ARM SoC (r8a7790, r8a7791,
r8a7793 and r8a7794) are almost the same, they can be combined into one
structure. This provides structure that summarizes infomation of module control
register and default register values.
And this structure is the module control use of the kernel at boot time.
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This adds infomation of bits for module control register. This is used
to control modules on ARM R-Car SoCs.
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This addes macro for set and clear bit control for module control register.
This is used when user want to disable the function of the devices
corresponding to register.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Control macro of mstp is common in R-Car ARM SoC (r8a7790, r8a7791,
r8a7793 and r8a7794). This moves these to arch-rmobile/rcar-mstp.h
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Module control registers of R-Car ARM SoC (r8a7790, r8a7791, r8a7793 and
r8a7794) are same address. This moves these to header file of SoC.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
BeagleBoard-X15 is the next generation Open Source
Hardware BeagleBoard based on TI's AM5728 SoC
featuring dual core 1.5GHZ A15 processor. The
platform features 2GB DDR3L (w/dual 32bit busses),
eSATA, 3 USB3.0 ports, integrated HDMI (1920x108@60),
separate LCD port, video In port, 4GB eMMC, uSD,
Analog audio in/out, dual 1G Ethernet.
For more information, refer to:
http://www.elinux.org/Beagleboard:BeagleBoard-X15
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
just add a few ifdefs around because this
device is very similar to dra7xxx.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
expose those two definitions so they can be
used by another board which we're adding in upcoming
patches.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
this will allow for boards to overwrite those
in case memory setup is different.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
If we want to have two sections, one on each EMIF, without
interleaving, current code wouldn't enable emif2. Fix that
problem.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
some boards might want to use USB1 for host,
without fiddling those registers it'll be
impossible.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Those regulators don't have any coupling with
what they supply, so remove the suffixes in order
to not confuse anybody.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
As checkpatch complaines about these camel-case defines, lets change
them to only use upper-case characters.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Jon Nettleton <jon.nettleton@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
- fix crash when sata device is not initialized
- remove disable_sata_clock() since it is not clear which clock for which
device should be disabled here
- call disable_sata_clock() for mx6 in preboot_os instead
Signed-off-by: Soeren Moch <smoch@web.de>
Acked-by: Nikita Kiryanov <nikita@compulab.co.il>
Tested-by: Nikita Kiryanov <nikita@compulab.co.il>
If CONFIG_OF_CONTROL is defined, search device tree nodes that are
compatible with "panasonic,uniphier-ehci" and take the base address
from their "reg" property.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Marek Vasut <marex@denx.de>
This commit implements the ofdata_to_platdata handler for the UniPhier
serial driver and adds serial device nodes to the device tree sources.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled.
It includes <asm/gpio.h> and then <asm/gpio.h> includes
<asm/arch/gpio.h>. Consequently, all the SoCs that enable
CONFIG_OF_CONTROL must have <asm/arch/gpio.h> even if they do not
support GPIO.
In the first place, GPIO has nothing to do with OF_CONTROL.
It is wrong that lib/fdtdec.c includes GPIO functions; it should
be split into two files, FDT-common things and GPIO things.
It is, however, a pretty big work to fix that correctly.
This is a compromised commit to add a dummy <asm/arch/gpio.h>
to support OF_CONTROL for UniPhier platform. This dummy header
will be removed after FDT-GPIO stuff is fixed correctly.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The initramfs is currently only relocated if the user calls
the bootm ramdisk subcommand. If bootm should be used without
subcommands, the arch-specific bootm code needs to implement
the relocation.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
After all MIPS boards are switched to generic-board, the
MIPS specific board.c can be removed.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
To get correct stack walking and backtrace functionality in gdb,
registers fp and ra should be initialized before calling board_init_f
or board_init_r. Thus allocating stack space and zeroing it as it is
currently done in board.c becomes obsolete.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Merge struct s3c2410_nand and struct s3c2440_nand into one unified
struct s3c24x0_nand. While at it, fix up and rename the functions
to retrieve the NAND base address and fix up the s3c NAND driver to
reflect this change.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Vladimir Zapolskiy <vz@mleia.com>
This fixes the following two problems:
cppcheck reports:
[arch/sandbox/cpu/start.c:132]: (error) Uninitialized variable: err
[arch/sandbox/cpu/os.c:371]: (error) Memory leak: fname
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Wolfgang Denk <wd@denx.de>
Intel's Graphics Media Accelerator (GMA) is a generic name for a wide range
of video devices. Add code to set up the hardware on ivybridge. Part of the
init happens in native code, part of it happens in a 16-bit option ROM for
those nostalgic for the 1970s.
Signed-off-by: Simon Glass <sjg@chromium.org>
On x86 machines we can use an emulator to run option ROMS as with other
architectures. But with some additional effort (mostly due to the 16-bit
nature of option ROMs) we can run them natively. Add support for this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Option ROMs require a few additional descriptors. Add these, and remove the
enum since we now have to access several descriptors from assembler.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add code to set up the Local Advanced Peripheral Interrupt Controller.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Rename interrupt_init() in arch/x86/lib/pcat_interrupts.c to
i8259_init() and create a new interrupt_init() in
arch/x86/cpu/interrupt.c to call i8259_init() followed by a
call to cpu_init_interrupts().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Since cpu_init_interrupts() was moved out of cpu_init_r(), it is
useless to keep cpu_init_r() for x86, thus remove it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Currently cpu_init_interrupts() is called from cpu_init_r() to
setup the interrupt and exception of the cpu core, but at that
time the i8259 has not been initialized to mask all the irqs
and remap the master i8259 interrupt vector base, so the whole
system is at risk of being interrupted, and if interrupted,
wrong interrupt/exception message is shown.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Intel chips have a turbo mode where they can run faster for a short period
until they reach thermal limits. Add code to adjust and query this feature.
Signed-off-by: Simon Glass <sjg@chromium.org>
These peripherals should not be at the top level, since they exist inside
the PCI bus. We don't have a full device tree node for pci yet, but we
should at least put it at the right level.
Signed-off-by: Simon Glass <sjg@chromium.org>
Set up all the remaining pieces of the LPC (low-pin-count) peripheral in
PCH (Peripheral Controller Hub).
Signed-off-by: Simon Glass <sjg@chromium.org>
Some boards will want to do some setup before and after a PCI hose
is scanned.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Define the reset base in config.mk so that it does not need to be calculated
twice in the link script. Also tidy up the START_16 and RESET_VEC_LOC values
to fit with this new approach.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Some toolchains put the relocation data into separate sections. Adjust the
linker script to catch this case. Without relocation data, U-Boot will not
boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This normally indicates a problem which will prevent relocation from
functioning, resulting in a hang. Panic in this case to make it easier
to debug.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This function is not needed. Remove it to improve the generic init sequence
slightly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
It is now required to add subdirectories in the x86 cpu Makefile. Add this
to fix a build breakage for chromebook_link.
Signed-off-by: Simon Glass <sjg@chromium.org>
Allwinner tells us that this bit of code is the rtc ram being used to detect
coming out of "super-standby" mode, and if that is the case, going out of
self-refresh mode.
Since we do not support "super-standby" mode, this can be dropped.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add simplefb support, note this depends on the kernel having support for
the clocks property which has recently been added to the simplefb devicetree
binding.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
[hdegoede@redhat.com: Use pre-populated simplefb node under /chosen as
disussed on the devicetree list]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>.
This adds a fixed mode hdmi driver for the sunxi platform. The fixed
mode is a relatively safe 1024x768, more complete EDID handling is
currently not provided. Only HDMI is supported today.
This code is enabled when HPD detects an attached monitor.
Current config is such that 8MB is shaved off at the top of the RAM.
This avoids several memory handling issues, most significant is the fact
that on linux on ARM you are not allowed to remap known RAM as IO. A
clued in display driver will be able to recycle this reserved RAM in
future though.
cfbconsole was chosen as it provides the most important functionality: a
working u-boot console, allowing for the debugging of certain issues
without the need for a UART.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
[hdegoede@redhat.com: Major cleanups and some small bugfixes]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This is a preparation patch for adding support for HDMI out.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The data sheet just calls it DRAM_CLK_REG, and on sun6i we've both a
dram_clk_cfg and dram_clk_gate, and the sun4i reg matches dram_clk_gate on
sun6i, so name it the same on sun4i.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
SCFG_SCFGREVCR is SCFG bit reverse register. This register
must be written with 0xFFFFFFFF before writing to any other
SCFG register. Then other SCFG register could be written in
big-endian mode.
Address: 157_0000h base + 200h offset = 157_0200h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15|16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
W/R SCFGREV
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0-31
SCFGREV SCFG Bit Reverse Control Filed
32'h 0000_0000 - No bit reverse is applied
32'h FFFF_FFFF - Bit reverse is applied; so 31:0 will be stored/read as
0:31
This patch removes the bit reversing for SCFG registers in
u-boot. It will be implemented through PBI commands in RCW
.pbi
write 0x570200, 0xffffffff
.end
So other SCFG register could be written in big-endian mode
in u-boot or kernel directly.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Disable the snoop for slave interface 0, 1 and 2
to avoid the interleaving on the CCI400 BUS.
Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Define USB configs for LS1021XA such as CONFIG_SYS_FSL_USB1_ADDR,
CONFIG_USB_MAX_CONTROLLER_COUNT
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Set TXFIFOTHRESH to adjust ddr pipeline delay for successful large
usb writes
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Ideally, the Linux kernel should get the hardware in its most
untouched state. For the most part, U-Boot does not reset the various
subsystems it touches before boot, and usually Linux deals with it, but
on some boards (cm_fx6) the Linux kernel fails to detect the ssd
correctly if sata is used by U-Boot.
Power off sata on OS boot so that Linux will have a clean state to work
with.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Add reset_sata() to the sata driver interface and implement it
for dwc_ahsata. This function cleans up after sata_init(), and
therefore accepts a device number like sata_init() does.
A dummy implementation is provided for the rest of the drivers.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Older Linux kernels will not properly boot in hyp mode, add support for a
bootm_boot_mode environment variable, which can be set to "sec" or "nonsec"
to force booting in secure or non-secure mode when build with non-sec support.
The default behavior can be selected through CONFIG_ARMV7_BOOT_SEC_DEFAULT,
when this is set booting in secure mode is the default. The default setting
for this Kconfig option is N, preserving the current behavior of booting in
non-secure mode by default when non-secure mode is supported.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Add arch/arm/cpu/armv7/Kconfig with non-secure and virt options, this is a
preparation patch for adding an env variable to choose between secure /
non-secure boot on non-secure boot capable systems, specifically this
prepares for adding CONFIG_ARMV7_BOOT_SEC_DEFAULT as a proper Kconfig option.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Change the internal sandbox functions to use loff_t for file offsets.
Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Some tegra makefiles only contain a dummy line to generate
a built-in.o. Let's do not descend into such directories.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
The references of CONFIG_SYS_COREBOOT in arch/x86/cpu/coreboot/Makefile
are redundant because the build system descends into the directory
only when CONFIG_SYS_COREBOOT is defined.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Some CPUs of some architectures have SOC directories.
At present, the build system directly descends into SOC directories
from the top Makefile, but it should generally descend into each
directory from its parent directory.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
bcm911360_entphn
bcm911360_entphn-ns
bcm911360k
bcm958300k-ns
bcm958305k
- updates to support Cygnus and NSP board families better
- add functions so CONFIG_ARMV7_NONSEC can be enabled on Cygnus boards
Signed-off-by: Steve Rae <srae@broadcom.com>
U-Boot has never cared about the type when we get max/min of two
values, but Linux Kernel does. This commit gets min, max, min3, max3
macros synced with the kernel introducing type checks.
Many of references of those macros must be fixed to suppress warnings.
We have two options:
- Use min, max, min3, max3 only when the arguments have the same type
(or add casts to the arguments)
- Use min_t/max_t instead with the appropriate type for the first
argument
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Pavel Machek <pavel@denx.de>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[trini: Fixup arch/blackfin/lib/string.c]
Signed-off-by: Tom Rini <trini@ti.com>
Move USB Errata checking code from "arch/powerpc" to architecture independent
file "fsl_usb.h" so that errata(s) become independent of the architecture.
For each erratum checking function for PPC arch, define a nop function for
non PPC arch for successful compilation in either case
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Add imx6 thermal device to mx6 soc file. Read the cpu temperature
using this device to access onchip thermal sensor.
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Add api to check and enable pll3 as required
for thermal sensor driver.
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
The linker lists feature is useful in SPL as it holds the driver model
platform data. So don't throw away the lists.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@ti.com>
For SPL it is sometimes useful to have a simple malloc() just to permit
driver model to work, in the cases where the full malloc() is not made
available by the board config.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add driver model support while retaining the existing legacy code. This
allows the driver to support boards that have converted to driver model
as well as those that have not.
Signed-off-by: Simon Glass <sjg@chromium.org>
These boards all have the same GPIO arrangement, so add some common platform
data that can be used by all boards. Remove the configs which are no longer
required.
Signed-off-by: Simon Glass <sjg@chromium.org>
Modify this driver to support driver model, with platform data required to
determine the GPIOs that it controls.
Signed-off-by: Simon Glass <sjg@chromium.org>
Rename this vendor since it is intended to be used on any platform where
coreboot runs at reset and then loads U-Boot.
So far it is only tested on link. When other boards are supported it is
likely that we will need to move to multiple board names, all under the
'coreboot' vendor. So while it would be possible to remove the vendor for
now, that would be short-sighted.
Suggested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in
the board directory and the SDRAM SPD information in the device tree. This
also needs the Intel Management Engine (me.bin) to work. Binary blobs
everywhere: so far we have MRC, ME and microcode.
SDRAM init works by setting up various parameters and calling the MRC. This
in turn does some sort of magic to work out how much memory there is and
the timing parameters to use. It also sets up the DRAM controllers. When
the MRC returns, we use the information it provides to map out the
available memory in U-Boot.
U-Boot normally moves itself to the top of RAM. On x86 the RAM is not
generally contiguous, and anyway some RAM may be above 4GB which doesn't
work in 32-bit mode. So we relocate to the top of the largest block of
RAM we can find below 4GB. Memory above 4GB is accessible with special
functions (see physmem).
It would be possible to build U-Boot in 64-bit mode but this wouldn't
necessarily provide any more memory, since the largest block is often below
4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large
ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit
kernels directly so this does not pose a limitation in that area. Also there
are probably parts of U-Boot that will not work correctly in 64-bit mode.
The MRC is one.
There is some work remaining in this area. Since memory init is very slow
(over 500ms) it is possible to save the parameters in SPI flash to speed it
up next time. Suspend/resume support is not fully implemented, or at least
it is not efficient.
With this patch, link boots to a prompt.
Signed-off-by: Simon Glass <sjg@chromium.org>
The local advanced programmable interrupt controller is not used much in
U-Boot but we do need to set it up. Add basic support for this, which will
be extended as needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
When not relying on Coreboot for GPIO init the GPIOs must be set up
correctly. This is currently done statically through a rather ugly method.
As the GPIOs are figured out they can be moved to the device tree and set
up as needed rather than all at the start.
In this implementation, board files should call ich_gpio_set_gpio_map()
before the GPIO driver is used in order to provide the GPIO information.
We use the early PCI interface so that this driver can now be used before
relocation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add two microcode updates that are provided for this CPU. The updates
have been converted to a device tree form.
Note: SPDX submission has been done. If this license is approved I will
convert the files to use SPDX.
Signed-off-by: Simon Glass <sjg@chromium.org>
The built-in self test value should be checked before we continue booting.
Refuse to continue if there is something wrong.
Signed-off-by: Simon Glass <sjg@chromium.org>
It is convenient to be able to adjust MSRs with a structure that splits the
two 32-bit halves into separate fields, as they are often dealt with
separately. Add a few functions to support this.
Signed-off-by: Simon Glass <sjg@chromium.org>
There is no need to explicitly write 'arch-coreboot' when including headers,
as when the arch directory points to coreboot the correct files will be
used.
Signed-off-by: Simon Glass <sjg@chromium.org>
The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device
which provides a serial port. This is accessible on Chromebooks, so enable
it early in the boot process.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add simple PCI access routines for x86 which permit use before relocation.
The normal PCI stack is still used, but for pre-relocation use there can
only ever be a single hose. After relocation, fall back to the normal
access, although even then on x86 machines there is normally only a single
PCI bus.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add support for using PCI before SDRAM is available, using early malloc()
and global_data.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We want access PCI earlier in the init sequence, so refactor the code so
that it does not require use of a BSS variable to work. This will allow us
to use early malloc() to store information about a PCI hose.
Common PCI code moves to arch/x86/cpu/pci.c and a new
board_pci_setup_hose() function is provided by boards to set up the (single)
hose used by that board.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add support for CAR so that we have memory to use prior to DRAM init.
On link there is a total of 128KB of CAR available, although some is
used for the memory reference code.
Signed-off-by: Simon Glass <sjg@chromium.org>
On x86 it is common to use 'post codes' which are 8-bit hex values emitted
from the code and visible to the user. Traditionally two 7-segment displays
were made available on the motherboard to show the last post code that was
emitted. This allows diagnosis of a boot problem since it is possible to
see where the code got to before it died.
On modern hardware these codes are not normally visible. On Chromebooks
they are displayed by the Embedded Controller (EC), so it is useful to emit
them. We must enable this feature for the EC to see the codes, so add an
option for this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
On x86 machines U-Boot needs to be added to a large ROM image which is
then flashed onto the target board. The ROM has a particular format so it
makes sense for U-Boot to build this image automatically. Unfortunately
it relies on binary blobs so we cannot require this for the default
build as yet.
Create a u-boot.rom output file for this purpose.
Signed-off-by: Simon Glass <sjg@chromium.org>
This board is a 'bare' version of the existing 'link 'board. It does not
require coreboot to run, but is intended to start directly from the reset
vector.
This initial commit has place holders for a wide range of features. These
will be added in follow-on patches and series. So far it cannot be booted
as there is no ROM image produced, but it does build without errors.
Signed-off-by: Simon Glass <sjg@chromium.org>
Unfortunately MSR_FSB_FREQ is not available on this CPU, and the PIT method
seems to take up to 50ms which is much too long.
For this CPU we know the frequency, so add another special case for now.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The references of CONFIG_SYS_COREBOOT in arch/x86/cpu/coreboot/Makefile
are redundant because the build system descends into the directory
only when CONFIG_SYS_COREBOOT is defined.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
This implementation has a 'cpu' prefix and returns a pointer to the string,
avoiding the need for copying.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a function to get the stack pointer and another to halt the CPU.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Return the saved TSC frequency in get_tbclk_mhz().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Use the same way that Linux does for quick TSC calibration via PIT
when calibration via MSR fails.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Using MSR_PLATFORM_INFO (0xCE) to calibrate TSR will cause #GP on
processors which do not have this MSR. Instead only doing the MSR
calibration for known/supported CPUs.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
The CPU identification happens in x86_cpu_init_f() and corresponding
fields are saved in the global data for later use.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
The built in self test value is available in register eax on start-up. Save
it so that it can be accessed later. Unfortunately we must wait until the
global_data is available before we can do this, so there is a little bit of
shuffling to keep it around.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Some functions are missing prototypes. Fix those that are specific to x86.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Instead of an x86-specific cpu_init_f() function, use the normal U-Boot one
for this purpose. Also remove a useless/misleading comment.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Instead of having an x86-specific DRAM init function, adjust things so we
can use the normal one.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This code is a little muddled, so tidy it up. Make sure that we put the
GDT in the right place and set it up properly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We should invalidate the TLB right at the start to ensure that we don't get
false address translations even though paging is disabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This allows a board to do very early init, but no boards need to do this.
We may as well drop this feature.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This was missed when the real mode support was dropped. Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This function can fail if the device tree runs out of space. Rather than
silently booting with an incomplete device tree, allow the failure to be
detected.
Unfortunately this involves changing a lot of places in the code. I have
not changed behvaiour to return an error where one is not currently
returned, to avoid unexpected breakage.
Eventually it would be nice to allow boards to register functions to be
called to update the device tree. This would avoid all the many functions
to do this. However it's not clear yet if this should be done using driver
model or with a linker list. This work is left for later.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
U-Boot has imported various utility macros from Linux
scattering them to various places without consistency.
In include/common.h are min, max, min3, max3, ARRAY_SIZE, ALIGN,
container_of, DIV_ROUND_UP, etc.
In include/linux/compat.h are min_t, max_t, round_up, round_down,
etc.
We also have duplicated defines of min_t in some *.c files.
Moreover, we are suffering from too cluttered include/common.h.
This commit moves various macros that originate in
include/linux/kernel.h of Linux to their original position.
Note:
This commit simply moves the macros; the macros roundup,
min, max, min2, max3, ARRAY_SIZE are different
from those of Linux at this point.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
The Linux-compatible macro DIV_ROUND_CLOSEST is a bit more flexible
and safer than DIV_ROUND.
For example,
foo = DIV_ROUND_CLOSEST(x, y++)
works expectedly, but
foo = DIV_ROUND(x, y++)
does not. (y is incremented twice.)
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
CONFIG_CPU_ARM1136 was introduced into Kconfig by commit 2e07c249a6
(kconfig: arm: introduce symbol for ARM CPUs).
This commit removes all the defines of CONFIG_ARM1136 and replaces
the only reference in arch/arm/lib/cache.c with CONFIG_CPU_ARM1136.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
CONFIG_CPU_ARM926EJS was introduced into Kconfig by commit 2e07c249a6
(kconfig: arm: introduce symbol for ARM CPUs).
This commit removes all the defines of CONFIG_ARM926EJS and replaces
the only reference in arch/arm/lib/cache.c with CONFIG_CPU_ARM926EJS.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
CONFIG_CPU_ARM920T was introduced into Kconfig by commit 2e07c249a6
(kconfig: arm: introduce symbol for ARM CPUs).
This commit removes all the defines of CONFIG_ARM920T and replaces the
only reference in drivers/usb/host/ohci-hcd.c with CONFIG_CPU_ARM920T.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Some (not all) of ARMv7 boards define CONFIG_ARMV7, which is useless.
Besides, it is never referenced.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Move MX5 specific set_chipselect_size function into generic i.MX part,
such that MX6 based boards are able to use this function as well.
While doing this the iomuxc gpr member needed to be consolidated between
MX5 and MX6.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Many boards use a minimal .cfg file in the SPL case.
Introduce spl_sd.cfg so that we can reuse it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Commit 3ff46cc4 fixed exception vectors setting in
the general ARM case, by either copying the exception
and indirect vector tables to normal (0x00000000) or
high (0xFFFF0000) vectors address, or setting VBAR to
U-Boot's base if applicable.
i.MX27 SoC is ARM926E-JS, thus has only normal and
high options, but does not provide RAM at 0xFFFF0000
and has only ROM at 0x00000000; it is therefore not
possible to move or change its exception vectors.
Besides, i.MX27 ROM code does provide an indirect
vectors table but at a non-standard address and with
the reset and reserved vectors missing.
Turn the current vector relocation code into a weak
routine called after relocate_code from crt0, and add
strong version for i.MX27.
Series-Cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Tested-by: Stefano Babic <sbabic@denx.de>
Tested-by: Philippe Reynes <tremyfr@gmail.com>
Tested-by: Philippe Reynes <tremyfr@yahoo.fr>
mkimage -T mxs now support new flag in config file:
DISPLAYPROGRESS - makes boot process print HTLLC characters for each BootROM
instruction.
Signed-off-by: Alexey Ignatov <lexszero@gmail.com>
As auto-negotiation is not supported for 2.5G SGMII, we need
to add a new type PHY_INTERFACE_MODE_SGMII_2500 to differentiate
SGMII-1G and SGMII-2.5G with different setting for auto-negotiation.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
There are 8 SCFG_SPARECR registers in SCFG memory block, not one.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
ls1021 is arm-core and support qe which is u-qe.
add u-qe init for arm board.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
[York Sun: Fix compiling error caused by u_qe_init()]
Reviewed-by: York Sun <yorksun@freescale.com>
When an MPC5200 based board is used with SPL support, the main
U-Boot needs to clear the GD (global data) struct again.
Otherwise the generic board init code in board_init_f (when
CONFIG_SYS_GENERIC_BOARD is defined) will not initialize all
GD variables correctly. Resulting in a hangup on the a4m2k
board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
The gdsys hrcon board is based on a Freescale MPC8308 SOC.
It boots from NOR-Flash, kernel and rootfs are stored on
SD-Card.
On board peripherals include:
- 1x GbE (optional)
- Lattice ECP3 FPGA connected via eLBC and PCIe
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
The code for this board supports following features:
- Boot media support: NAND flash/SD card/SPI flash
- Support LCD display (optional, disabled by default)
- Support ethernet
- Support USB mass storage
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
The code for this board supports following features:
- Boot media support: NAND flash/SD card/SPI flash
- Support LCD display
- Support ethernet
- Support USB mass storage
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
replaces the at91bootstrap code with SPL code.
make the spl image with:
./tools/mkimage -T atmelimage -d spl/u-boot-spl.bin spl/boot.bin
this writes the length of the spl image into the 6th
execption vector. This is needed from the ROM bootloader.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Bo Shen <voice.shen@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
replaces the at91bootstrap code with SPL code.
make the spl image with:
./tools/mkimage -T atmelimage -d spl/u-boot-spl.bin spl/boot.bin
this writes the length of the spl image into the 6th
execption vector. This is needed from the ROM bootloader.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
add support for using spl code on at91sam9260 and at91sam9g45
based boards.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Bo Shen <voice.shen@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
[adopt Bo's change in spl.c]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
- compile mpddrc ram init code also for AT91SAM9M10G45
based boards.
- in CONFIG_SAMA5D3 case, look for the ATMEL_MPDDRC_CR_DECOD_INTERLEAVED
in the cr configuration
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Reviewed-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
use the configure value for computing the ba_off value
not the value from the cr register. This leaded in a
wrong ram configuration on the upcoming corvus spl board
support.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
The clock source for master clock can be slow clock, main clock,
plla clock or upll clock. So, make the clock source selection
field in mckr can be configured.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
We need to make sure the main clock ready field in MCFR is set
after switch to main crystal oscillator.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
This change adds support for enabling the USB host features of the board.
This includes the USB3503A hub and the SMC LAN9730 ethernet controller
as well.
Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Enable/disable the usb host phy on the odroid U/X2 boards which are based
on the Exynos4412 SOC.
Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The current vbus GPIOs on snow make very little sense, their number is
far above the maximum. As a result, USB doesn't work on snow.
Correct the GPIO numbering so they match the current scheme for exynos5.
Tested both EHCI and XHCI to correctly work after this change.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Exynos5800 IROM has a different, from 5250 and 5420, prototype of the
usb_copy() function. Luckily the earlier version did not expect any
arguments, which means the same code could be used with old and new
SoCs, the old ones just ignoring the arguments.
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add a 4G configuration and choose it based on the number of banks
declared in config file. A board with 4 SDRAM banks declared (as
per CONFIG_NR_DRAM_BANKS) will end up with the 2G confiuration.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
As per Exynos5800 UM ver 0.00 section 17.13.2.1
CONCONTROL register bit 3 [update_mode], Exynos5800 does not
support the PHY initiated update. And it is recommanded to
set this field to 1'b1 during initialization. This patch sets this bit.
Applying MC-initiated mode makes DDL tracking ON, that helps in
compensate MIF voltage variation.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This adds following things :
- New config and defconfig for Peach-Pi board.
- Alterations in Kconfig and MAINTAINERS.
- Addition of CONFIG_EXYNOS5800.
- ADdition of exynos5800-peach-pi in dts list.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
We have a new board Peach-Pi similar to Peach-Pit. Peach-Pi
differs from Peach-Pit in configuration factors like display
resolution, memory size, SoC version etc.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch intends to add a new proid for Exynos5800 which is a
variant of Exynos5420. Product id for Exynos5800 is 0x5422.
Both Exynos5420 and Exynos5800 are pin to pin compitable. This
gives us an advantage of reusing Exynos5420 clock, pinmux, memory
and other settings.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add pinmux settings, implement board_ehci_hcd_init, board_usb_phy_mode
There are two usb port on mx6slevk board:
1. otg port
2. host port
The following are the connection between usb controller and board usb
interface, host port has not ID pin set:
otg1 core <---> board otg port
otg2 core <---> board host port
In order to make host port work, board_usb_phy_mode return USB_INIT_HOST
to let host port work in host mode.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye Li <B37916@freescale.com>
The argument boot_flags of board_init_f() is not used at all in the
powerpc specific board.c init sequence. Now with the generic init
sequence, this boot_flags arg is used by board_init_f().
This patch sets the r3 register that is used to pass the boot_flags
argument from the start.S board_init_f() call to 0 prior to the function
call to avoid unknown content to end up in gd->flags.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Reviewed-by: York Sun <yorksun@freescale.com>
IFC registers can be of type Little Endian or big Endian depending upon
Freescale SoC. Here SoC defines the register type of IFC IP.
So use IFC acessor functions instead of in_be32().
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
LIODN entry for B4860/B4420 mentions USB controller as "mph"
insread of "dr". This results in PAMU not permitting bus
transactions for USB DR controller on B4860 resulting in
USB function failure. Replacing "fsl-usb2-mph" with
"fsl-usb2-dr" allows USB DR controller bus transactions
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Reviewed-by: Sethi Varun-B16395 <Varun.Sethi@freescale.com>
Reviewed-by: Sun Yusong-R58495 <yorksun@freescale.com>
NEG bit default is '1' for external MDIOs as per FMAN-v3 RM, but on some
platforms, e.g. T2080QDS, this bit is '0', which leads to MDIO failure
on XAUI PHY, so set this bit definitely to align with the RM.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
1. use Payload length check disable when enable MAC;
2. add XGMII support for setting MAC interface mode;
3. only enable auto negotiation for Non-XGMII mode;
4. return 0xffff if clause 22 is used to read 10G phy_id;
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Acked-By: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Add initial support for TBS2910 Matrix ARM miniPC.
Support includes MMC, Ethernet, UARTs, HDMI, USB, SATA, PCI, I2C, RTC.
Signed-off-by: Soeren Moch <smoch@web.de>
Add two missing Kconfig options for Novena and drop the SPL
from the Novena config.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Sean Cross <xobs@kosagi.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Add support for the 2 ehci controllers found on the sun6i (A31) soc.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Marek Vasut <marex@denx.de>
Without this the cache will only work in write-through mode, and as soon as
it is put in write-back mode things break.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add full support for dram initialization, using a fixed clock and autodetection
of the memory organization (numbers of channels, bus-width, etc.).
This is based on dram_sun6i.c and dram.h from u-boot in the Allwinner A31 SDK,
extended with extra initialization sequences and the autodetect algorithm
from boot0.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add clock_init_safe and clockset_pll5 functions, as these are needed for
SPL support resp. DRAM init (which is needed for SPL too).
Also add some extra clock register constant defines.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The A31 uses a new push-pull two wire interface, which features higher
transfer speeds (upto 6 MHz) in theory. While the hardware can burst 8
bytes each time, this driver will only see very little use and thus is
limited to single byte transmission only.
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Commit 2e07c249a6 (kconfig: arm: introduce symbol for ARM CPUs)
collected the default values of CONFIG_SYS_CPU into arch/arm/Kconfig.
This commit moves "armv8" to there for consistency.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Georges Savoundararadj <savoundg@gmail.com>
This commit adds "select CPU_V7" for some new boards that were not
covered by commit 2e07c249a6
(kconfig: arm: introduce symbol for ARM CPUs).
Redundant "SYS_CPU" defines and "string" directives should be removed.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Georges Savoundararadj <savoundg@gmail.com>
Precisely, these boards are SH4A rather than SH4.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Now each board selects one of CONFIG_CPU_SH2, CONFIG_CPU_SH3,
CONFIG_CPU_SH4, so let's move CONFIG_SYS_CPU definition to
arch/sh/Kconfig.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The current prompts were added by a conversion tool
based on board directory names when switching to Kconfig.
Use better prompts mostly taken from from arch/sh/boards/*
of Linux Kernel.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
mcc200 and prs200 are old and have no maintainer. Remove the boards.
This also removes the mcc200 specific 1bpp BMP support from
common/lcd.c
Cc: Wolfgang Denk <wd@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: York Sun <yorksun@freescale.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
The bmode command forces the SoC to use a specific boot device
by writing its boot mode into SRC_GPR9, and notifying the SoC of
the change using SRC_GPR10[28] bit: if the bit is on, bootROM
uses the value in SRC_GPR9 instead of SRC_SMBR1 to determine
the boot device.
SPL on the other hand is oblivious to this distinction, so once
the bootROM loads SPL from the device configured in SRC_GPR10,
SPL will attempt to load U-Boot from the device configured in
SRC_SMBR1, which is not updated by the bootROM to the value in
SRC_GPR9.
The result is that the selected boot device is not used across all
the boot stages.
Update spl_boot_device() to look at gpr9 when necessary.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Heiko Schocher <hs@denx.de>
size_t is the canonical type to represent variables that contain a size.
Use it instead of signed integer. Physical addresses can be larger than
32-bit, so use a more appropriate type for them as well. phys_addr_t is
a type that is 32-bit on systems that use 32-bit addresses and 64-bit if
the system is 64-bit or uses a form of physical address extension to use
a larger address space on 32-bit systems. Using these types the same API
can be implemented on a wider range of systems.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Remove two gratuituous blank lines, uses u32 (instead of int) as the
type for values that will be written to a register, moves the beginning
of the variable declaration section to a separate line (rather than the
one with the opening brace) and keeps the function signature on a single
line where possible.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
This is a MIME GnuPG-signed message. If you see this text, it means that
your E-mail or Usenet software does not support MIME signed messages.
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software that supports modern Internet standards.
This reverts commit 1e96220a56.
Remove duplicated vxworks.h header.
The same change was done by
"ARM: prevent compiler warnings from bootm.c"
(sha1: 8d196e52b5)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
CONFIG_UNIPHIER_SERIAL has been moved to Kconfig and
it is defined in ./.config but not in spl/.config,
so pin_init() should be called from the normal image
so that UART works correctly.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This commit merges
arch/arm/cpu/armv7/uniphier/ph1-*/board_postclk_init.c
to
arch/arm/cpu/armv7/uniphier/board_postclk_init.c
Because PH1-Pro4 does not have the BCU block, add __weak to
bcu_init().
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
The function sg_set_pinsel is useful for switching I/O pins
but it can be only used in C code. This commit adds a simple
macro that is available in asm code.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Support EHCI host driver used on Panasonic UniPhier platform.
Since Device Tree is not supported on UniPhier yet, the base address
of USB cores are passed from board files (platdevice.c).
TODO for me:
Move the base address to device trees.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Marek Vasut <marex@denx.de>
This commit adds register defines of MIO (Media I/O) block
of UniPhier platform. This file is necessary to control
the reset signals of the USB cores.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
If a support card is attached to the main board, the on-board
SMSC9118 LAN controller is available. It must be kept in reset
state for a while on start-up.
When the board is kicked via a debbuger rather than pushing the
hardware reset button, on-board chips are not reset; in this case
the reset signals should be asserted by software.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Add a defconfig and Kconfigury for the Digilent ZYBO board.
Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
It's a Zynq board similar in design to the currently supported ones.
512MB of RAM and UART1 is used.
Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
cppcheck reports:
[arch/arm/cpu/arm926ejs/mxs/timer.c:96]: (error) Uninitialized
variable: now
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
ppc4xx i2c master gets stuck on errors while repeated start is
active. Can be easily reproduced by "i2c md" on an unpopulated
i2c address. There is not stop condition given, scl remains
pulled low.
The only way out seems to be doing a stop manually and then a
soft reset.
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
R-Car SoCs of rmobile have same IP of rcar-i2c, and have same address.
This moves rcar-i2c of the address defined to rcar-base.h as common header of
R-Car SoCs.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
R-Car SoCs of rmobile have same IP of sh-i2c, and have same address.
This moves sh-i2c of the address defined to rcar-base.h as common header of
R-Car SoCs, and headers of each SoCs.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Renesas R8A7793 is CPU with Cortex-A15. This supports the basic register
definition and GPIO and framework of PFC.
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
There are a number of places where U-Boot intentionally and legally
accesses physical address 0x0000, for example when installing
exception vectors on systems where these are located in low memory.
Add "cppcheck-suppress nullPointer" comments to silence cppcheck
where this is intentional and legal.
Signed-off-by: Wolfgang Denk <wd@denx.de>
sandbox crashes if a variable is set in the -c command, because
hush's top_vars is not allocated. Call cli_init() from sandbox
to ensure this is done before we execute the -c command.
$ ./u-boot -c 'a=1'
...
Segmentation fault (core dumped)
Signed-off-by: Rabin Vincent <rabin@rab.in>
Acked-by: Simon Glass <sjg@chromium.org)
Tested-by: Simon Glass <sjg@chromium.org)
This function will be needed by the upcoming Designware master SPI
driver. As the SPI master controller is held in reset by the current
Preloader implementation. So we need to release the reset for the
driver to communicate with the controller.
This function is called from arch_early_init_r() if the SPI
driver is enabled.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
This function will be needed by the upcoming Designware master SPI
driver.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
This patch includes the latest DT sources for socfpga from the current
Linux kernel. And enables CONFIG_OF_CONTROL for the new build target
"socfpga_socrates" (the EBV SoCrates board) to make use of this new DT
support.
Until this patch, the only SoCFPGA U-Boot target in mainline is
"socfpga_cyclone5". This build target is not (yet) changed to support
DT. So nothing changes for this target. Even though the long-term
goal should be to move all SoCFPGA targets over to DT.
One of the reasons to enable DT support in SoCFPGA is, that I need to
support multiple different SPI controllers for this platform. This is
the QSPI Cadence controller and the Designware SPI master controller.
Both are implemented in the SoCFPGA. And enabling both controllers is
only possible by using the new driver model (DM). The DM SPI code
only supports DT based probing. So it was easier to move SoCFPGA to
DT than to add the (deprecated) platform-data based probing to the
DM SPI suport.
Note that the image with the dtb embedded is u-boot-dtb.img. This needs
to be used now for those DT enabled boards instead of u-boot.img.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Pavel Machek <pavel@denx.de>
Cc: Simon Glass <sjg@chromium.org>
CompuLab cm-t3517 is Computer on Module (CoM) based on AM3517 SoC.
Features: up to 256MB DDR2, up to 512MB NAND, USB hub, mUSB, WiFi, BT,
Analog audio codec, touch screen controller, LED.
Add basic support including:
LED, Serial console, NAND, MMC, GPIO, I2C, 256MB DRAM.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Current get_board_rev() function returns a hard coded value which is
obviously incorrect for the majority of boards.
Allow boards to provide a correct implementation by making this
function weak.
In addition open code the trivial and useless BOARD_REV_ID define and
adjust the comment.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@ti.com>
The Keystone2 Lamar SoC uses the same keystone net driver.
This patch adds opportunity to use it by K2L SoCs.
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Keystone2 Lamar SoC uses the same keystone SerDes driver.
All Keystone2 EVM boards currently use SerDes driver, so move
CONFIG_TI_KEYSTONE_SERDES to common configuration file.
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
The Keystone2 Lamar SoC uses the same keystone navigator.
Move queue numbers to common hardware file, as all Keystone2 SoCs
have the same ones.
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Add a driver for the designware serial UART used on sunxi. This just
redirects to the normal ns16550 driver.
Add a stdout-path to the device tree so that the correct UART is chosen.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
With driver model we will have access to a bank pointer, so we want to
use it rather than converting back to a number, and then back to a
bank pointer. Add functions to provide this feature.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
For now we won't want to mess with the existing configurations. Create a
new one which will enable device tree and driver model. Note that this
brings the device tree binary into u-boot-sunxi-with-spl.bin.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
These are from Linux 3.17-rc7 (commit fe82dcec). U-Boot only uses a small
portion of these, but we may as well have something to look forward to.
The total compiled size is about 25KB.
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Mostly automatic with:
sed -i -e 's/CONFIG_\(SUN[45678]I\)/CONFIG_MACH_\1/g' $(git grep -l CONFIG_SUN[45678]I)
followed by removing the relevant #defines from include/configs/sun?i.h by
hand.
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
And make TARGET_SUN[45678]I a choice variable under this.
configs updated with:
sed -i -e 's/^\(\+S:\)\?CONFIG_TARGET_SUN.I=y/\1CONFIG_ARCH_SUNXI=y\n&/g' configs/*
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
I realized that with v2014.10 u-boot is not starting up on
ppc4xx boards with CONFIG_SYS_GENERIC_BOARD set.
I bisected it down to this:
d54d7eb support blackfin board initialization in generic board_f
With
d29437a ppc: Make ppc4xx ready for CONFIG_SYS_GENERIC_BOARD
I set gd to a defined value for ppc4xx in cpu_init_f().
I did not realize that the gd struct has also to be memset()
to zero at this point.
But at least commit d54d7eb assumes it is:
@@ -516,11 +528,13 @@ static int reserve_malloc(void)
/* (permanently) allocate a Board Info struct */
static int reserve_board(void)
{
- gd->start_addr_sp -= sizeof(bd_t);
- gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t));
- memset(gd->bd, '\0', sizeof(bd_t));
- debug("Reserving %zu Bytes for Board Info at: %08lx\n",
- sizeof(bd_t), gd->start_addr_sp);
+ if (!gd->bd) {
+ gd->start_addr_sp -= sizeof(bd_t);
+ gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t));
+ memset(gd->bd, '\0', sizeof(bd_t));
+ debug("Reserving %zu Bytes for Board Info at: %08lx\n",
+ sizeof(bd_t), gd->start_addr_sp);
+ }
return 0;
}
#endif
This might also be an issue on other architectures, so maintainers should
check.
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
For now, all the SPARC boards in U-Boot are provided by Gaisler.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Daniel Hellstrom <daniel@gaisler.com>
Remove arch/sparc/cpu/{leon2,leon3}/config.mk and move duplicated
defines of -fPIC to arch/sparc/config.mk.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Daniel Hellstrom <daniel@gaisler.com>
The Board names in the board select menu were simply taken from the
board directory name by a conversion tool when switching to Kconfig.
Let's use more descriptive prompts taken from
include/configs/gr*.h and board/gaisler/*/config.mk.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Daniel Hellstrom <daniel@gaisler.com>
If CONFIG_RMOBILE_EXTRAM_BOOT is enabled, U-Boot is booted from External RAM.
The default boot address is 0x70000000.
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
If CONFIG_RMOBILE_EXTRAM_BOOT is enabled, U-Boot is booted from External RAM.
The default boot address is 0x70000000.
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
If CONFIG_RMOBILE_EXTRAM_BOOT is enabled, U-Boot is booted from External RAM.
The default boot address is 0xB0000000.
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The change of the CPU frequency is waited for until PLL0ST of the PLLECR is
set to 1.
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Initialization of L2CTLR[5] was set only as R8A7790 by commit
237faf095f.
However, initialization of cash needs to be performed continuously.
This changes into the processing which continues initialization of
L2CTLR[5] into L2CTLR cash and performs it.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
On mx6 sabreauto board, there are two USB ports:
0: OTG
1: HOST
The EHCI driver is enabled for this board, but the IOMUX and VBUS power
control is not implemented, which cause both USB port failed to work.
This patch fix the problem by adding the board support codes.
Since the power control uses the GPIO pin from port expander MAX7310,
the PCA953X driver is enabled for accessing the MAX7310.
The ID pin of OTG Port needs to configure the GPR1 bit 13 for selecting
its daisy chain. Add a new function "imx_iomux_set_gpr_register" to
handle GPR register setting.
Signed-off-by: Ye.Li <B37916@freescale.com>
For MX6SL and MX6SX, the perclk can come from OSC 24Mhz source. Fix
the get_ipg_per_clk function to support it.
Signed-off-by: Ye.Li <B37916@freescale.com>
Introduce a new configuration "CONFIG_MXC_GPT_HCLK". When it is set,
the GPT will select a high frequency clock as clock source.
Otherwise, the GPT will stay to use 32Khz OSC as clock source.
In the implementation, since only the GPT on i.MX6 series provide the
clock source option for 24Mhz OSC. For others (only i.MX5 and i.MX6
compile the driver), if the configuration is set, the perclk will be
selected as clock source.
MX6Q/D Rev 1.0 and MX6SL are special in the implementation, because they
don't have the 24Mhz OSC clock source option, so also select the perclk
for them. For MX6SL, we will set the OSC 24Mhz to perclk in CCM, so
eventually the clock comes from OSC 24Mhz.
Signed-off-by: Ye.Li <B37916@freescale.com>
Commit 79fd7e649e
MIPS: always keep all sections in u-boot ELF binary.
Always keep all sections in u-boot ELF binary. Move all unneeded
sections after _end to avoid allocating space in the final binary.
Also remove .deadcode section which is now obsolete.
removed section .deadcode because the original symptoms were not
visible anymore. Unfortuneatly the binutils bug still exists.
The size of .rel.dyn section is often bigger than needed for all
entries. But objcopy only allocates space as much as required for all
reloc entries. Thus there is a gap between the last entry and
__rel_dyn_end in u-boot.bin. If u-boot is booted from RAM (e.g. in
SPL scenarios) that area could contain garbage data which could lead
to CPU exceptions during relocation.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Refactor and unify all compiler settings in arch/mips/config.mk.
Also add tune flags for each supported CPU type.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Now the user can separately select the CPU type. Thus the
targets qemu_mips and qemu_mips64 can be merged to a single
target.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Now the user can select the CPU type for each target. Thus
CONFIG_SYS_CPU could be set globally.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Add new Kconfig option to let the user select the targets
CPU type. Each target have to select SUPPORTS_CPU_MIPS[32,64]_R[1,2]
to indicate which CPU types are supported.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Add new Kconfig option to let the user select the targets
endianess. Each target have to select SUPPORTS_BIG_ENDIAN
and/or SUPPORTS_LITTLE_ENDIAN to indicate which endianess
is supported.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Commit d58a9451e7 (ppc/arm: zap EMK boards) removed
TOP* boards support but missed to remove entries in Kconfig.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
[1] arch/arm/include/asm/arch-at91/at91_shdwn.h
The top9000 was the last board to use this header file.
It was removed by commit d58a9451e7 (ppc/arm: zap EMK boards).
[2] board/matrix_vision/common/*
Some Matrix Vision boards were dropped by commit e7a565638a
(powerpc: mpc83xx: remove board support for MERGERBOX and MVBLM7)
and commit af55e35d33
(powerpc: mpc5xxx: remove board support for MVBC_P and MVSMR).
Since then these files have been unused.
[3] include/usb/omap1510_udc.h
The omap5912osk was the last board to use this header file.
It was removed by commit 62d636aa2a
(omap: remove omap5912osk board support).
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-By: Wolfgang Denk <wd@denx.de>
This patch adds extra gpio part addresses to exynos4
and exynos4x12_gpio_data arrays, which are required
since the gpio enum lists are linear
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
After remove the offsets in Exynos4/4x12 gpio enums,
an additional gpio base addresses are required.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add support for the Kosagi Novena board. Currently supported are:
- I2C busses
- FEC Ethernet
- MMC0, MMC1, Booting from MMC
- SATA
- USB ports
- USB Ethernet
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Sean Cross <xobs@kosagi.com>
Cc: Nikolay Dimitrov <picmaster@mail.bg>
Reviewed-by: Nikolay Dimitrov <picmaster@mail.bg>
Add CONFIG_CMD_PINMON to UniPhier-specific Kconfig and make the
"pinmon" command user-configurable. This command can be disabled
via the configuration if users do not need it.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Before this commit, the stack addresses for IRQ and FIQ modes,
IRQ_STACK_START and FIQ_STACK_START, were computed in interrupt_init but
they were not used.
This commit sets the stack pointers for IRQ and FIQ modes.
Signed-off-by: Georges Savoundararadj <savoundg@gmail.com>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
This commit relocates the exception vectors.
As ARM1176 and ARMv7 have the security extensions, it uses VBAR. For
the other ARM processors, it copies the relocated exception vectors to
the correct address: 0x00000000 or 0xFFFF0000.
Signed-off-by: Georges Savoundararadj <savoundg@gmail.com>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Tom Warren <twarren@nvidia.com>
A regression was introduced in commit 41623c91. The consequence of that
is the non-relocation of the section .vectors symbols :
_undefined_instruction, _software_interrupt, _prefetch_abort,
_data_abort, _not_used, _irq and _fiq.
Before commit 41623c91, the exception vectors were in a .text section.
The .text section has the attributes allocatable and executable [1].
In commit 41623c91, a specific section is created, called .vectors, with
the attribute executable only.
What have changed between commit 41623c91^ and 41623c91 is the attribute
of the section which contains the exception vectors.
An allocatable section is "a section [that] occupies memory during
process execution" [1] which is the case of the section .vectors.
Adding the lacking attribute (SHF_ALLOC or "a") for the definition of
the section .vectors fixed the issue.
To summarize, the fix has to mark .vectors as allocatable because the
exception vectors reside in "memory during execution" and they need to
be relocated.
[1] http://man7.org/linux/man-pages/man5/elf.5.html
Signed-off-by: Georges Savoundararadj <savoundg@gmail.com>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
This commit introduces a Kconfig symbol for each ARM CPU:
CPU_ARM720T, CPU_ARM920T, CPU_ARM926EJS, CPU_ARM946ES, CPU_ARM1136,
CPU_ARM1176, CPU_V7, CPU_PXA, CPU_SA1100.
Also, it adds the CPU feature Kconfig symbol HAS_VBAR which is selected
for CPU_ARM1176 and CPU_V7.
For each target, the corresponding CPU is selected and the definition of
SYS_CPU in the corresponding Kconfig file is removed.
Also, it removes redundant "string" type in some Kconfig files.
Signed-off-by: Georges Savoundararadj <savoundg@gmail.com>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
In preparation for the SoCFPGA support of the designware I2C driver,
convert this driver to the common CONFIG_SYS_I2C framework.
This patch converts all users of this driver, this is:
- ST spearxxx boards
- AXS101 (ARC700 platform)
I couldn't test this patch on those boards. Only compile tested for all
spear boards. And tested on SoCFPGA.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Tested-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Vipin Kumar <vk.vipin@gmail.com>
Cc: Jeroen Hofstee <jeroen@myspectrum.nl>
The boot_zimage() function is badly named it can also boot a raw kernel.
Rename it, and try to avoid pointers for memory addresses as it involves
lots of casting.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add code to jump to a 64-bit Linux kernel. We need to set up a flat page
table structure, a new GDT and then go through a few hoops in the right
order.
Signed-off-by: Simon Glass <sjg@chromium.org>
The following bard configurations have been without active maintenance
for a long time, and the board maintainer agrees to have them removed:
MPC5200: TOP5200, MINI5200, EVAL5200
MPC860: TOP860
at91sam9xeXXX: top9000eval_xe, top9000su_xe
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
[trini: Add missing Kconfig removals]
Signed-off-by: Tom Rini <trini@ti.com>
There is no gaps in exynos gpio enum after rework, so the gpio
numbers should be adjusted to the new numbering.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
There is no gaps in exynos gpio enum after rework, so the gpio
numbers should be adjusted to the new numbering.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
There is no gaps in exynos gpio enum after rework, so the gpio
numbers should be adjusted to the new numbering.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
There is no gaps in exynos gpio enum after rework, so the gpio
numbers should be adjusted to the new numbering.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
The gpy0 don't need any additional register offset,
but the gpx0 does, so now it is fixed.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
The gpf0 offset was bad and it's now fixed.
After fix gpio order in *pinctrl.dts , the gpy0 offset is not required now.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
The pinctrl dts was imported from the kernel, but the order
of GPM and GPY is wrong. The gpio enum in: asm/arch/gpio.h
is proper.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
CONFIG_TPL should not be enabled for boards that do not have TPL.
CONFIG_SUPPORT_TPL introduced by this commit should be "select"ed
by boards with TPL support and CONFIG_TPL should depend on it.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
CONFIG_SPL should not be enabled for boards that do not have SPL.
CONFIG_SUPPORT_SPL introduced by this commit should be "select"ed
by boards with SPL support and CONFIG_SPL should depend on it.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
Rename some defines containing FAT in their name to be filesystem generic:
MMCSD_MODE_FAT => MMCSD_MODE_FS
CONFIG_SPL_FAT_LOAD_ARGS_NAME => CONFIG_SPL_FS_LOAD_ARGS_NAME
CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME => CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION => CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION
Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Tom Rini <trini@ti.com>
There's a definition in stdint.h (provided by gcc) which will be more correct
if available.
Define CONFIG_USE_STDINT to use this feature, or USE_STDINT=1 on the 'make'
commmand.
This adjusts the settings for x86 and sandbox, with both have 64-bit options.
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@google.com>
Rewritten to be an option, since stdint.h is often available only in glibc.
Changed to preserve a clear boundary between stdint and non-stdint
Signed-off-by: Simon Glass <sjg@chromium.org>
This board is old and is using CONFIG_I2C_X, which is wrong.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
This board is old and is using CONFIG_I2C_X, which is wrong.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
This board is old and is using CONFIG_I2C_X, which is wrong.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
This is the only used of CONFIG_SPI_X macro, just zap this.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Remove this board as this is the only one last user of eeprom_probe(),
which is pretty non-standard stuff.
This patch also removes all the PHP, SQL and CSS stuff from U-Boot,
which probably makes U-Boot a bit less IoT ;-)
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
This board uses eeprom accessors in an incorrect way. The board
is old and unsupported, just zap it.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
This board is the only user of CONFIG_SYS_EEPROM_X40430 , remove
it so the EEPROM command code can be cleansed of the related code
as well.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
The file board/Marvell/include/mv_gen_reg.h is incompatible with
the GPL (see for example the "MARVELL RESERVES THE RIGHT AT ITS SOLE
DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO
MARVELL" clause). As this cannot be fixed, we remove the file and all
code that depends on it. Fortunately this only affects some very old
boards that have long reached EOL:
CPCI750
DB64360
DB64460
p3m750
p3m7448
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Roger Meier <r.meier@siemens.com>
Commit d6b11fd1 (powerpc: remove MBX and MBX860T boards support)
removed mbxbar field in "struct sysconf512x" by mistake and broke
booting on mpc5121 boards. Fix it.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Switch to the common spl.h file and zap the arch/spl.h . Since the arch/spl.h
contained various ad-hoc symbols, zap those symbols as well and rework the
board configuration a little so it doesn't depend on them.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Acked-by: Pavel Machek <pavel@denx.de>
Move this initialization code to proper place. The misc_init_r()
function is called way too late and the platform initialization
code should be executed much earlier.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Acked-by: Pavel Machek <pavel@denx.de>
Because CONFIG_MMU is never defined in U-Boot,
the non-MMU code in debug.S is always used.
Unfortunately, the number of arguments of the addruart macro
in Linux is different between MMU and non-MMU.
This causes a build error when importing some debug macros
using the third argument. (For ex. arch/arm/include/debug/exynos.S)
Pass the third argument to the non-MMU addruart to avoid such a problem.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
We have not had a good method to debug the early boot stage such as
lowlevel_init function. I guess developers generally use dedicated
debuggers for that, but it is difficult in some cases.
(For example, my debugger cannot connect to the ARM processor when
it is in the secure state. It sometimes happens when I need to
debug the early boot stage on ARM SoCs with secure extension.)
The low level debug feature in Linux would be also helpful for U-boot
when we are stucking in nasty problems where the console is not
available yet.
You have to enable CONFIG_DEBUG_LL to use this feature.
For now, only 8250-compatible UART devices are supported.
You can add a header file under arch/arm/include/debug/ directory
to support your UART device if necessary.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
U-Boot does not have arch/arm/kernel, include/uapi directories,
This commit copies files as follows:
Location in Linux -> Location in U-Boot
arch/arm/kernel/debug.S -> arch/arm/lib/debug.S
arch/arm/include/debug/8250.S -> arch/arm/include/debug/8250.S
include/uapi/linux/serial_reg.h -> include/linux/serial_reg.h
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Add a Kconfig option which users can select when they want to boot older
kernels, e.g. the linux-sunxi 3.4 kernels. For now this just forces the pll5
"p" value to 1 (divide by 2) as that is what those kernels are hardcoded too,
in the future this may enable further workarounds.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Tom Rini <trini@ti.com>
--
Changes in v2:
-s/CONFIG_OLD_KERNEL_COMPAT/CONFIG_OLD_SUNXI_KERNEL_COMPAT.
-Move the code block setting P(1) for old kernels to where P gets cleared
This is a preparation patch for making the pll5 "p" divisor configurable
through Kconfig.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This is a preparation patch for making the pll5 "p" divisor configurable
through Kconfig.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The A23 only has UART0 muxed with MMC0. Some of the boards we
encountered expose R_UART as a set of pads.
Add support for R_UART so we can have a console while using mmc.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The prcm apb0 controls multiple modules. Allow specifying which
modules to enable clocks and de-assert resets so the function
can be reused.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The A31, A23 and later SoCs have an extra pin controller, called CPUs_PIO
or R_PIO, which handles pin banks L and beyond.
Also add a clear description about SUNXI_GPIO_BANKS, stating it only
counts the number of pin banks in the _main_ pin controller.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens@csie.org: expanded commit message]
[wens@csie.org: add pin bank M and expand comments]
[wens@csie.org: add comment on SUNXI_GPIO_BANKS macro]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The basic blocks of the A23 are similar to the A31 (sun6i). Re-use
sun6i code for initial clock, gpio, and uart setup.
There is no SPL support for A23, as we do not have any documentation
or sample code for DRAM initialization.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The Allwinner A23 SoC has reset controls like the A31 (sun6i).
The FIFO address is also the same as sun6i.
Re-use code added for sun6i.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Allwinner SoCs provide uart0 muxed with mmc0, which can then be used
with a micro SD breakout board. On the A23, this is the only way to
use uart0.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The watchdog on sun6i/sun8i has a different layout.
Add the new layout and fix up the setup functions so that reset works.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
[ ijc -- removed sun5i workaround from sun6i/sun8i codepath as discussed ]
The RTC hardware has been moved out of the timer block on sun6i/sun8i.
In addition, there are more watchdogs available.
Also note that the timer block definition is not completely accurate
for sun5i/sun7i. Various blocks are missing or have been moved out.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
On later Allwinner SoCs, the watchdog hardware is by all means a
separate hardware block, with its own address range and interrupt
line.
Move the register definitions to a separate file to facilitate
supporting newer SoCs.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
