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arch/powerpc: Add SGMII support for the L2 Switch ports
Some Freescale SoCs like T1020 and T1040 have an integrated L2 Switch. The L2 Switch ports may be connected to Ethernet PHYs over SGMII and QSGMII. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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3 changed files with 16 additions and 4 deletions
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@ -78,6 +78,12 @@ static const char *serdes_prtcl_str[] = {
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[INTERLAKEN] = "INTERLAKEN",
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[QSGMII_SW1_A] = "QSGMII_SW1_A",
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[QSGMII_SW1_B] = "QSGMII_SW1_B",
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[SGMII_SW1_MAC1] = "SGMII_SW1_MAC1",
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[SGMII_SW1_MAC2] = "SGMII_SW1_MAC2",
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[SGMII_SW1_MAC3] = "SGMII_SW1_MAC3",
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[SGMII_SW1_MAC4] = "SGMII_SW1_MAC4",
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[SGMII_SW1_MAC5] = "SGMII_SW1_MAC5",
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[SGMII_SW1_MAC6] = "SGMII_SW1_MAC6",
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};
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#endif
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@ -33,10 +33,10 @@ static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
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PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
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[0x87] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
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[0x89] = {PCIE1, QSGMII_SW1_A, QSGMII_SW1_A, QSGMII_SW1_A,
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PCIE2, PCIE3, QSGMII_SW1_B, SATA1},
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[0x8D] = {PCIE1, QSGMII_SW1_A, QSGMII_SW1_A, QSGMII_SW1_A,
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PCIE2, QSGMII_SW1_B, QSGMII_SW1_B, QSGMII_SW1_B},
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[0x89] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2,
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PCIE2, PCIE3, SGMII_SW1_MAC4, SATA1},
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[0x8D] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2,
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PCIE2, SGMII_SW1_MAC6, SGMII_SW1_MAC4, SGMII_SW1_MAC5},
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[0x8F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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AURORA, NONE, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
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[0xA5] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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@ -87,6 +87,12 @@ enum srds_prtcl {
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SGMII_2500_FM2_DTSEC6,
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SGMII_2500_FM2_DTSEC9,
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SGMII_2500_FM2_DTSEC10,
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SGMII_SW1_MAC1,
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SGMII_SW1_MAC2,
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SGMII_SW1_MAC3,
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SGMII_SW1_MAC4,
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SGMII_SW1_MAC5,
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SGMII_SW1_MAC6,
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SERDES_PRCTL_COUNT /* Keep this item the last one */
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};
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