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ARM: ls102xa: allow all the peripheral access permission as R/W.
The Central Security Unit (CSU) allows secure world software to change the default access control policies of peripherals/bus slaves, determining which bus masters may access them. This allows peripherals to be separated into distinct security domains. Combined with SMMU configuration of the system masters privileges, these features provide protection against indirect unauthorized access to data. For now we configure all the peripheral access permissions as R/W. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
This commit is contained in:
parent
1a2826f6e0
commit
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8 changed files with 335 additions and 0 deletions
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@ -21,6 +21,7 @@
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#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
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#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
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#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
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#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
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#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
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#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
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118
arch/arm/include/asm/arch-ls102xa/ns_access.h
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118
arch/arm/include/asm/arch-ls102xa/ns_access.h
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@ -0,0 +1,118 @@
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/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __FSL_NS_ACCESS_H_
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#define __FSL_NS_ACCESS_H_
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enum csu_cslx_access {
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CSU_NS_SUP_R = 0x08,
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CSU_NS_SUP_W = 0x80,
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CSU_NS_SUP_RW = 0x88,
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CSU_NS_USER_R = 0x04,
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CSU_NS_USER_W = 0x40,
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CSU_NS_USER_RW = 0x44,
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CSU_S_SUP_R = 0x02,
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CSU_S_SUP_W = 0x20,
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CSU_S_SUP_RW = 0x22,
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CSU_S_USER_R = 0x01,
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CSU_S_USER_W = 0x10,
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CSU_S_USER_RW = 0x11,
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CSU_ALL_RW = 0xff,
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};
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enum csu_cslx_ind {
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CSU_CSLX_PCIE2_IO = 0,
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CSU_CSLX_PCIE1_IO,
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CSU_CSLX_MG2TPR_IP,
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CSU_CSLX_IFC_MEM,
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CSU_CSLX_OCRAM,
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CSU_CSLX_GIC,
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CSU_CSLX_PCIE1,
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CSU_CSLX_OCRAM2,
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CSU_CSLX_QSPI_MEM,
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CSU_CSLX_PCIE2,
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CSU_CSLX_SATA,
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CSU_CSLX_USB3,
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CSU_CSLX_SERDES = 32,
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CSU_CSLX_QDMA,
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CSU_CSLX_LPUART2,
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CSU_CSLX_LPUART1,
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CSU_CSLX_LPUART4,
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CSU_CSLX_LPUART3,
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CSU_CSLX_LPUART6,
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CSU_CSLX_LPUART5,
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CSU_CSLX_DSPI2 = 40,
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CSU_CSLX_DSPI1,
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CSU_CSLX_QSPI,
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CSU_CSLX_ESDHC,
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CSU_CSLX_2D_ACE,
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CSU_CSLX_IFC,
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CSU_CSLX_I2C1,
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CSU_CSLX_USB2,
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CSU_CSLX_I2C3,
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CSU_CSLX_I2C2,
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CSU_CSLX_DUART2 = 50,
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CSU_CSLX_DUART1,
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CSU_CSLX_WDT2,
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CSU_CSLX_WDT1,
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CSU_CSLX_EDMA,
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CSU_CSLX_SYS_CNT,
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CSU_CSLX_DMA_MUX2,
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CSU_CSLX_DMA_MUX1,
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CSU_CSLX_DDR,
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CSU_CSLX_QUICC,
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CSU_CSLX_DCFG_CCU_RCPM = 60,
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CSU_CSLX_SECURE_BOOTROM,
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CSU_CSLX_SFP,
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CSU_CSLX_TMU,
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CSU_CSLX_SECURE_MONITOR,
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CSU_CSLX_RESERVED0,
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CSU_CSLX_ETSEC1,
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CSU_CSLX_SEC5_5,
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CSU_CSLX_ETSEC3,
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CSU_CSLX_ETSEC2,
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CSU_CSLX_GPIO2 = 70,
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CSU_CSLX_GPIO1,
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CSU_CSLX_GPIO4,
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CSU_CSLX_GPIO3,
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CSU_CSLX_PLATFORM_CONT,
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CSU_CSLX_CSU,
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CSU_CSLX_ASRC,
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CSU_CSLX_SPDIF,
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CSU_CSLX_FLEXCAN2,
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CSU_CSLX_FLEXCAN1,
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CSU_CSLX_FLEXCAN4 = 80,
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CSU_CSLX_FLEXCAN3,
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CSU_CSLX_SAI2,
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CSU_CSLX_SAI1,
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CSU_CSLX_SAI4,
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CSU_CSLX_SAI3,
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CSU_CSLX_FTM2,
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CSU_CSLX_FTM1,
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CSU_CSLX_FTM4,
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CSU_CSLX_FTM3,
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CSU_CSLX_FTM6 = 90,
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CSU_CSLX_FTM5,
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CSU_CSLX_FTM8,
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CSU_CSLX_FTM7,
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CSU_CSLX_COP_DCSR,
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CSU_CSLX_EPU,
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CSU_CSLX_GDI,
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CSU_CSLX_DDI,
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CSU_CSLX_RESERVED1,
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CSU_CSLX_USB3_PHY = 117,
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CSU_CSLX_RESERVED2,
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CSU_CSLX_MAX,
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};
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struct csu_ns_dev {
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unsigned long ind;
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uint32_t val;
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};
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void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num);
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#endif
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@ -68,4 +68,6 @@ obj-$(CONFIG_P3041DS) += p_corenet/
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obj-$(CONFIG_P4080DS) += p_corenet/
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obj-$(CONFIG_P5020DS) += p_corenet/
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obj-$(CONFIG_P5040DS) += p_corenet/
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obj-$(CONFIG_LS102XA_NS_ACCESS) += ns_access.o
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endif
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30
board/freescale/common/ns_access.c
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30
board/freescale/common/ns_access.c
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@ -0,0 +1,30 @@
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/*
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* Copyright 2014 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/ns_access.h>
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void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num)
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{
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u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR;
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u32 *reg;
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uint32_t val;
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int i;
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for (i = 0; i < num; i++) {
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reg = base + ns_dev[i].ind / 2;
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val = in_be32(reg);
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if (ns_dev[i].ind % 2 == 0) {
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val &= 0x0000ffff;
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val |= ns_dev[i].val << 16;
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} else {
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val &= 0xffff0000;
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val |= ns_dev[i].val;
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}
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out_be32(reg, val);
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}
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}
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@ -8,6 +8,7 @@
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#include <i2c.h>
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#include <asm/io.h>
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#include <asm/arch/immap_ls102xa.h>
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#include <asm/arch/ns_access.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/pcie_layerscape.h>
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return 0;
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}
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#ifdef CONFIG_LS102XA_NS_ACCESS
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static struct csu_ns_dev ns_dev[] = {
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{ CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
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{ CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
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{ CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
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{ CSU_CSLX_IFC_MEM, CSU_ALL_RW },
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{ CSU_CSLX_OCRAM, CSU_ALL_RW },
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{ CSU_CSLX_GIC, CSU_ALL_RW },
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{ CSU_CSLX_PCIE1, CSU_ALL_RW },
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{ CSU_CSLX_OCRAM2, CSU_ALL_RW },
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{ CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
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{ CSU_CSLX_PCIE2, CSU_ALL_RW },
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{ CSU_CSLX_SATA, CSU_ALL_RW },
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{ CSU_CSLX_USB3, CSU_ALL_RW },
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{ CSU_CSLX_SERDES, CSU_ALL_RW },
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{ CSU_CSLX_QDMA, CSU_ALL_RW },
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{ CSU_CSLX_LPUART2, CSU_ALL_RW },
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{ CSU_CSLX_LPUART1, CSU_ALL_RW },
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{ CSU_CSLX_LPUART4, CSU_ALL_RW },
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{ CSU_CSLX_LPUART3, CSU_ALL_RW },
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{ CSU_CSLX_LPUART6, CSU_ALL_RW },
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{ CSU_CSLX_LPUART5, CSU_ALL_RW },
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{ CSU_CSLX_DSPI2, CSU_ALL_RW },
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{ CSU_CSLX_DSPI1, CSU_ALL_RW },
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{ CSU_CSLX_QSPI, CSU_ALL_RW },
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{ CSU_CSLX_ESDHC, CSU_ALL_RW },
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{ CSU_CSLX_2D_ACE, CSU_ALL_RW },
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{ CSU_CSLX_IFC, CSU_ALL_RW },
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{ CSU_CSLX_I2C1, CSU_ALL_RW },
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{ CSU_CSLX_USB2, CSU_ALL_RW },
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{ CSU_CSLX_I2C3, CSU_ALL_RW },
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{ CSU_CSLX_I2C2, CSU_ALL_RW },
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{ CSU_CSLX_DUART2, CSU_ALL_RW },
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{ CSU_CSLX_DUART1, CSU_ALL_RW },
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{ CSU_CSLX_WDT2, CSU_ALL_RW },
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{ CSU_CSLX_WDT1, CSU_ALL_RW },
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{ CSU_CSLX_EDMA, CSU_ALL_RW },
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{ CSU_CSLX_SYS_CNT, CSU_ALL_RW },
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{ CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
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{ CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
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{ CSU_CSLX_DDR, CSU_ALL_RW },
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{ CSU_CSLX_QUICC, CSU_ALL_RW },
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{ CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
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{ CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
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{ CSU_CSLX_SFP, CSU_ALL_RW },
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{ CSU_CSLX_TMU, CSU_ALL_RW },
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{ CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
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{ CSU_CSLX_RESERVED0, CSU_ALL_RW },
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{ CSU_CSLX_ETSEC1, CSU_ALL_RW },
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{ CSU_CSLX_SEC5_5, CSU_ALL_RW },
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{ CSU_CSLX_ETSEC3, CSU_ALL_RW },
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{ CSU_CSLX_ETSEC2, CSU_ALL_RW },
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{ CSU_CSLX_GPIO2, CSU_ALL_RW },
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{ CSU_CSLX_GPIO1, CSU_ALL_RW },
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{ CSU_CSLX_GPIO4, CSU_ALL_RW },
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{ CSU_CSLX_GPIO3, CSU_ALL_RW },
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{ CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
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{ CSU_CSLX_CSU, CSU_ALL_RW },
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{ CSU_CSLX_ASRC, CSU_ALL_RW },
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{ CSU_CSLX_SPDIF, CSU_ALL_RW },
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{ CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
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{ CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
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{ CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
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{ CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
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{ CSU_CSLX_SAI2, CSU_ALL_RW },
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{ CSU_CSLX_SAI1, CSU_ALL_RW },
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{ CSU_CSLX_SAI4, CSU_ALL_RW },
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{ CSU_CSLX_SAI3, CSU_ALL_RW },
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{ CSU_CSLX_FTM2, CSU_ALL_RW },
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{ CSU_CSLX_FTM1, CSU_ALL_RW },
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{ CSU_CSLX_FTM4, CSU_ALL_RW },
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{ CSU_CSLX_FTM3, CSU_ALL_RW },
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{ CSU_CSLX_FTM6, CSU_ALL_RW },
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{ CSU_CSLX_FTM5, CSU_ALL_RW },
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{ CSU_CSLX_FTM8, CSU_ALL_RW },
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{ CSU_CSLX_FTM7, CSU_ALL_RW },
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{ CSU_CSLX_COP_DCSR, CSU_ALL_RW },
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{ CSU_CSLX_EPU, CSU_ALL_RW },
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{ CSU_CSLX_GDI, CSU_ALL_RW },
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{ CSU_CSLX_DDI, CSU_ALL_RW },
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{ CSU_CSLX_RESERVED1, CSU_ALL_RW },
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{ CSU_CSLX_USB3_PHY, CSU_ALL_RW },
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{ CSU_CSLX_RESERVED2, CSU_ALL_RW },
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};
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#endif
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int board_init(void)
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{
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struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
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config_serdes_mux();
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#endif
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#ifdef CONFIG_LS102XA_NS_ACCESS
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enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
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#endif
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#ifdef CONFIG_U_QE
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u_qe_init();
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#endif
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#include <i2c.h>
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#include <asm/io.h>
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#include <asm/arch/immap_ls102xa.h>
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#include <asm/arch/ns_access.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/pcie_layerscape.h>
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}
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#endif
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#ifdef CONFIG_LS102XA_NS_ACCESS
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static struct csu_ns_dev ns_dev[] = {
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{ CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
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{ CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
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{ CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
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{ CSU_CSLX_IFC_MEM, CSU_ALL_RW },
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{ CSU_CSLX_OCRAM, CSU_ALL_RW },
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{ CSU_CSLX_GIC, CSU_ALL_RW },
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{ CSU_CSLX_PCIE1, CSU_ALL_RW },
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{ CSU_CSLX_OCRAM2, CSU_ALL_RW },
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{ CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
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{ CSU_CSLX_PCIE2, CSU_ALL_RW },
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{ CSU_CSLX_SATA, CSU_ALL_RW },
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{ CSU_CSLX_USB3, CSU_ALL_RW },
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{ CSU_CSLX_SERDES, CSU_ALL_RW },
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{ CSU_CSLX_QDMA, CSU_ALL_RW },
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{ CSU_CSLX_LPUART2, CSU_ALL_RW },
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{ CSU_CSLX_LPUART1, CSU_ALL_RW },
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{ CSU_CSLX_LPUART4, CSU_ALL_RW },
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{ CSU_CSLX_LPUART3, CSU_ALL_RW },
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{ CSU_CSLX_LPUART6, CSU_ALL_RW },
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{ CSU_CSLX_LPUART5, CSU_ALL_RW },
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{ CSU_CSLX_DSPI2, CSU_ALL_RW },
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{ CSU_CSLX_DSPI1, CSU_ALL_RW },
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{ CSU_CSLX_QSPI, CSU_ALL_RW },
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{ CSU_CSLX_ESDHC, CSU_ALL_RW },
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{ CSU_CSLX_2D_ACE, CSU_ALL_RW },
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{ CSU_CSLX_IFC, CSU_ALL_RW },
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{ CSU_CSLX_I2C1, CSU_ALL_RW },
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{ CSU_CSLX_USB2, CSU_ALL_RW },
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{ CSU_CSLX_I2C3, CSU_ALL_RW },
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{ CSU_CSLX_I2C2, CSU_ALL_RW },
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{ CSU_CSLX_DUART2, CSU_ALL_RW },
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{ CSU_CSLX_DUART1, CSU_ALL_RW },
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{ CSU_CSLX_WDT2, CSU_ALL_RW },
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{ CSU_CSLX_WDT1, CSU_ALL_RW },
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{ CSU_CSLX_EDMA, CSU_ALL_RW },
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{ CSU_CSLX_SYS_CNT, CSU_ALL_RW },
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{ CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
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{ CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
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{ CSU_CSLX_DDR, CSU_ALL_RW },
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{ CSU_CSLX_QUICC, CSU_ALL_RW },
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{ CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
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{ CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
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{ CSU_CSLX_SFP, CSU_ALL_RW },
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{ CSU_CSLX_TMU, CSU_ALL_RW },
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{ CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
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{ CSU_CSLX_RESERVED0, CSU_ALL_RW },
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{ CSU_CSLX_ETSEC1, CSU_ALL_RW },
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{ CSU_CSLX_SEC5_5, CSU_ALL_RW },
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{ CSU_CSLX_ETSEC3, CSU_ALL_RW },
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{ CSU_CSLX_ETSEC2, CSU_ALL_RW },
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{ CSU_CSLX_GPIO2, CSU_ALL_RW },
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{ CSU_CSLX_GPIO1, CSU_ALL_RW },
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{ CSU_CSLX_GPIO4, CSU_ALL_RW },
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{ CSU_CSLX_GPIO3, CSU_ALL_RW },
|
||||
{ CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
|
||||
{ CSU_CSLX_CSU, CSU_ALL_RW },
|
||||
{ CSU_CSLX_ASRC, CSU_ALL_RW },
|
||||
{ CSU_CSLX_SPDIF, CSU_ALL_RW },
|
||||
{ CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
|
||||
{ CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
|
||||
{ CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
|
||||
{ CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
|
||||
{ CSU_CSLX_SAI2, CSU_ALL_RW },
|
||||
{ CSU_CSLX_SAI1, CSU_ALL_RW },
|
||||
{ CSU_CSLX_SAI4, CSU_ALL_RW },
|
||||
{ CSU_CSLX_SAI3, CSU_ALL_RW },
|
||||
{ CSU_CSLX_FTM2, CSU_ALL_RW },
|
||||
{ CSU_CSLX_FTM1, CSU_ALL_RW },
|
||||
{ CSU_CSLX_FTM4, CSU_ALL_RW },
|
||||
{ CSU_CSLX_FTM3, CSU_ALL_RW },
|
||||
{ CSU_CSLX_FTM6, CSU_ALL_RW },
|
||||
{ CSU_CSLX_FTM5, CSU_ALL_RW },
|
||||
{ CSU_CSLX_FTM8, CSU_ALL_RW },
|
||||
{ CSU_CSLX_FTM7, CSU_ALL_RW },
|
||||
{ CSU_CSLX_COP_DCSR, CSU_ALL_RW },
|
||||
{ CSU_CSLX_EPU, CSU_ALL_RW },
|
||||
{ CSU_CSLX_GDI, CSU_ALL_RW },
|
||||
{ CSU_CSLX_DDI, CSU_ALL_RW },
|
||||
{ CSU_CSLX_RESERVED1, CSU_ALL_RW },
|
||||
{ CSU_CSLX_USB3_PHY, CSU_ALL_RW },
|
||||
{ CSU_CSLX_RESERVED2, CSU_ALL_RW },
|
||||
};
|
||||
#endif
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
|
||||
|
@ -320,6 +407,10 @@ int board_init(void)
|
|||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LS102XA_NS_ACCESS
|
||||
enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_U_QE
|
||||
u_qe_init();
|
||||
#endif
|
||||
|
|
|
@ -496,6 +496,7 @@ unsigned long get_board_ddr_clk(void);
|
|||
#define CONFIG_ARMV7_NONSEC
|
||||
#define CONFIG_ARMV7_VIRT
|
||||
#define CONFIG_PEN_ADDR_BIG_ENDIAN
|
||||
#define CONFIG_LS102XA_NS_ACCESS
|
||||
#define CONFIG_SMP_PEN_ADDR 0x01ee0200
|
||||
#define CONFIG_TIMER_CLK_FREQ 12500000
|
||||
#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
|
||||
|
|
|
@ -315,6 +315,7 @@
|
|||
#define CONFIG_ARMV7_NONSEC
|
||||
#define CONFIG_ARMV7_VIRT
|
||||
#define CONFIG_PEN_ADDR_BIG_ENDIAN
|
||||
#define CONFIG_LS102XA_NS_ACCESS
|
||||
#define CONFIG_SMP_PEN_ADDR 0x01ee0200
|
||||
#define CONFIG_TIMER_CLK_FREQ 12500000
|
||||
#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
|
||||
|
|
Loading…
Reference in a new issue