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armv8/fsl-lsch3: Add support for second DDR clock
FSL-LSCH3 platforms can have multiple DDR clocks. LS2085A has one clock for general DDR controlers, and another clock for DP-DDR. DDR driver needs to change to support multiple clocks. Signed-off-by: York Sun <yorksun@freescale.com>
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parent
49fd1f3f26
commit
b87e6f88e9
4 changed files with 21 additions and 2 deletions
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@ -367,6 +367,7 @@ int print_cpuinfo(void)
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printf("\n Bus: %-4s MHz ",
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strmhz(buf, sysinfo.freq_systembus));
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printf("DDR: %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus));
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printf(" DP-DDR: %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus2));
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puts("\n");
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return 0;
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@ -77,8 +77,10 @@ void get_sys_info(struct sys_info *sys_info)
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sys_info->freq_systembus = sysclk;
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#ifdef CONFIG_DDR_CLK_FREQ
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sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
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sys_info->freq_ddrbus2 = CONFIG_DDR_CLK_FREQ;
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#else
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sys_info->freq_ddrbus = sysclk;
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sys_info->freq_ddrbus2 = sysclk;
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#endif
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sys_info->freq_systembus *= (in_le32(&gur->rcwsr[0]) >>
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@ -87,6 +89,9 @@ void get_sys_info(struct sys_info *sys_info)
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sys_info->freq_ddrbus *= (in_le32(&gur->rcwsr[0]) >>
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FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
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FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
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sys_info->freq_ddrbus2 *= (in_le32(&gur->rcwsr[0]) >>
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FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) &
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FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK;
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for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
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/*
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@ -129,7 +134,7 @@ int get_clocks(void)
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gd->cpu_clk = sys_info.freq_processor[0];
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gd->bus_clk = sys_info.freq_systembus;
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gd->mem_clk = sys_info.freq_ddrbus;
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gd->arch.mem2_clk = sys_info.freq_ddrbus2;
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#if defined(CONFIG_FSL_ESDHC)
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gd->arch.sdhc_clk = gd->bus_clk / 2;
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#endif /* defined(CONFIG_FSL_ESDHC) */
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@ -156,11 +161,18 @@ ulong get_bus_freq(ulong dummy)
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* get_ddr_freq
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* return ddr bus freq in Hz
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*********************************************/
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ulong get_ddr_freq(ulong dummy)
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ulong get_ddr_freq(ulong ctrl_num)
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{
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if (!gd->mem_clk)
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get_clocks();
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/*
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* DDR controller 0 & 1 are on memory complex 0
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* DDR controler 2 is on memory complext 1
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*/
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if (ctrl_num >= 2)
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return gd->arch.mem2_clk;
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return gd->mem_clk;
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}
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@ -15,6 +15,7 @@ struct sys_info {
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unsigned long freq_processor[CONFIG_MAX_CPUS];
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unsigned long freq_systembus;
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unsigned long freq_ddrbus;
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unsigned long freq_ddrbus2;
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unsigned long freq_localbus;
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unsigned long freq_qe;
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#ifdef CONFIG_SYS_DPAA_FMAN
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@ -60,6 +61,8 @@ struct ccsr_gur {
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#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f
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#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10
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#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f
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#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18
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#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f
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u8 res_180[0x200-0x180];
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u32 scratchrw[32]; /* Scratch Read/Write */
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u8 res_280[0x300-0x280];
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@ -48,6 +48,9 @@ struct arch_global_data {
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#ifdef CONFIG_OMAP
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struct omap_boot_parameters omap_boot_params;
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#endif
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#ifdef CONFIG_FSL_LSCH3
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unsigned long mem2_clk;
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#endif
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};
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#include <asm-generic/global_data.h>
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