mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 15:14:43 +00:00
mpc8xx: remove SPD823TS board support
This board is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Masahiro Yamada
Tom Rini
parent
4317d070db
commit
72ba368f45
15 changed files with 2 additions and 1003 deletions
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@ -34,9 +34,6 @@ config TARGET_R360MPI
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config TARGET_RRVISION
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bool "Support RRvision"
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config TARGET_SPD823TS
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bool "Support SPD823TS"
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config TARGET_TQM823L
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bool "Support TQM823L"
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@ -83,7 +80,6 @@ source "board/ivm/Kconfig"
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source "board/lwmon/Kconfig"
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source "board/netvia/Kconfig"
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source "board/r360mpi/Kconfig"
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source "board/spd8xx/Kconfig"
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source "board/tqc/tqm8xx/Kconfig"
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endmenu
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@ -130,8 +130,7 @@ void cpu_init_f (volatile immap_t * immr)
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defined(CONFIG_IVMS8) || \
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defined(CONFIG_LWMON) || \
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defined(CONFIG_R360MPI) || \
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defined(CONFIG_RMU) || \
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defined(CONFIG_SPD823TS)
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defined(CONFIG_RMU)
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memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM;
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#endif
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@ -1,9 +0,0 @@
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if TARGET_SPD823TS
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config SYS_BOARD
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default "spd8xx"
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config SYS_CONFIG_NAME
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default "SPD823TS"
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endif
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@ -1,6 +0,0 @@
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SPD8XX BOARD
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M: Wolfgang Denk <wd@denx.de>
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S: Maintained
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F: board/spd8xx/
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F: include/configs/SPD823TS.h
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F: configs/SPD823TS_defconfig
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@ -1,8 +0,0 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = spd8xx.o flash.o
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@ -1,41 +0,0 @@
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/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <mpc8xx.h>
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flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
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/*-----------------------------------------------------------------------
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*/
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unsigned long flash_init (void)
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{
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/* All Speech Design board memory (DRAM and EPROM) initialisation is
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done in dram_init().
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The caller of ths function here expects the total size and will hang,
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if we give here back 0. So we return the EPROM size. */
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return (1024 * 1024); /* 1 MB */
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}
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/*-----------------------------------------------------------------------
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*/
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void flash_print_info (flash_info_t *info)
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{
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printf("no FLASH memory in MPC823TS board\n");
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return;
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}
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int flash_erase (flash_info_t *info, int s_first, int s_last)
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{
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return 1;
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}
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/*-----------------------------------------------------------------------
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*/
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@ -1,278 +0,0 @@
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/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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* Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <mpc8xx.h>
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#include <commproc.h>
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/* ------------------------------------------------------------------------- */
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static long int dram_size (long int, long int *, long int);
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/* ------------------------------------------------------------------------- */
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#define _NOT_USED_ 0xFFFFFFFF
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const uint sharc_table[] = {
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/*
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* Single Read. (Offset 0 in UPM RAM)
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*/
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0x0FF3FC04, 0x0FF3EC00, 0x7FFFEC04, 0xFFFFEC04,
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0xFFFFEC05, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Burst Read. (Offset 8 in UPM RAM)
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*/
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/* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Single Write. (Offset 18 in UPM RAM)
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*/
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0x0FAFFC04, 0x0FAFEC00, 0x7FFFEC04, 0xFFFFEC04,
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0xFFFFEC05, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Burst Write. (Offset 20 in UPM RAM)
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*/
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/* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Refresh (Offset 30 in UPM RAM)
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*/
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/* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Exception. (Offset 3c in UPM RAM)
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*/
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0x7FFFFC07, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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};
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const uint sdram_table[] = {
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/*
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* Single Read. (Offset 0 in UPM RAM)
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*/
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0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
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0x1FF77C47, /* last */
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/*
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* SDRAM Initialization (offset 5 in UPM RAM)
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*
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* This is no UPM entry point. The following definition uses
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* the remaining space to establish an initialization
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* sequence, which is executed by a RUN command.
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*
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*/
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0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
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/*
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* Burst Read. (Offset 8 in UPM RAM)
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*/
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0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
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0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Single Write. (Offset 18 in UPM RAM)
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*/
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0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Burst Write. (Offset 20 in UPM RAM)
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*/
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0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
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0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
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_NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Refresh (Offset 30 in UPM RAM)
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*/
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0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
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0xFFFFFC84, 0xFFFFFC07, /* last */
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_NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Exception. (Offset 3c in UPM RAM)
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*/
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0x7FFFFC07, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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};
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/* ------------------------------------------------------------------------- */
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/*
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* Check Board Identity:
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*
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*/
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int checkboard (void)
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{
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puts ("Board: SPD823TS\n");
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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phys_size_t initdram (int board_type)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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long int size_b0;
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#if 0
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/*
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* Map controller bank 2 to the SRAM bank at preliminary address.
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*/
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memctl->memc_or2 = CONFIG_SYS_OR2;
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memctl->memc_br2 = CONFIG_SYS_BR2;
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#endif
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/*
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* Map controller bank 4 to the PER8 bank.
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*/
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memctl->memc_or4 = CONFIG_SYS_OR4;
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memctl->memc_br4 = CONFIG_SYS_BR4;
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#if 0
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/* Configure SHARC at UMA */
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upmconfig (UPMA, (uint *) sharc_table,
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sizeof (sharc_table) / sizeof (uint));
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/* Map controller bank 5 to the SHARC */
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memctl->memc_or5 = CONFIG_SYS_OR5;
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memctl->memc_br5 = CONFIG_SYS_BR5;
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#endif
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memctl->memc_mamr = 0x00001000;
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/* Configure SDRAM at UMB */
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upmconfig (UPMB, (uint *) sdram_table,
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sizeof (sdram_table) / sizeof (uint));
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memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K;
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memctl->memc_mar = 0x00000088;
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/*
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* Map controller bank 3 to the SDRAM bank at preliminary address.
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*/
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memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
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memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
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memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL; /* refresh not enabled yet */
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udelay (200);
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memctl->memc_mcr = 0x80806105;
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udelay (1);
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memctl->memc_mcr = 0x80806130;
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udelay (1);
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memctl->memc_mcr = 0x80806130;
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udelay (1);
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memctl->memc_mcr = 0x80806106;
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memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */
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/*
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* Check Bank 0 Memory Size for re-configuration
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*/
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size_b0 =
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dram_size (CONFIG_SYS_MBMR_8COL, SDRAM_BASE3_PRELIM,
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SDRAM_MAX_SIZE);
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memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL | MBMR_PTBE;
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return (size_b0);
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Check memory range for valid RAM. A simple memory test determines
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* the actually available RAM size between addresses `base' and
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* `base + maxsize'. Some (not all) hardware errors are detected:
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* - short between address lines
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* - short between data lines
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*/
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static long int dram_size (long int mamr_value, long int *base,
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long int maxsize)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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memctl->memc_mbmr = mamr_value;
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return (get_ram_size (base, maxsize));
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}
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/* ------------------------------------------------------------------------- */
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void reset_phy (void)
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{
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immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
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ushort sreg;
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/* Configure extra port pins for NS DP83843 PHY */
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immr->im_ioport.iop_papar &= ~(PA_ENET_MDC | PA_ENET_MDIO);
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sreg = immr->im_ioport.iop_padir;
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sreg |= PA_ENET_MDC; /* Mgmt. Data Clock is Output */
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sreg &= ~(PA_ENET_MDIO); /* Mgmt. Data I/O is bidirect. => Input */
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immr->im_ioport.iop_padir = sreg;
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immr->im_ioport.iop_padat &= ~(PA_ENET_MDC); /* set MDC = 0 */
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/*
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* RESET in implemented by a positive pulse of at least 1 us
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* at the reset pin.
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*
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* Configure RESET pins for NS DP83843 PHY, and RESET chip.
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*
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* Note: The RESET pin is high active, but there is an
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* inverter on the SPD823TS board...
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*/
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immr->im_ioport.iop_pcpar &= ~(PC_ENET_RESET);
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immr->im_ioport.iop_pcdir |= PC_ENET_RESET;
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/* assert RESET signal of PHY */
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immr->im_ioport.iop_pcdat &= ~(PC_ENET_RESET);
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udelay (10);
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/* de-assert RESET signal of PHY */
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immr->im_ioport.iop_pcdat |= PC_ENET_RESET;
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udelay (10);
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}
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/* ------------------------------------------------------------------------- */
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void ide_set_reset (int on)
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{
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volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
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/*
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* Configure PC for IDE Reset Pin
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*/
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if (on) { /* assert RESET */
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immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_IDE_RESET);
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} else { /* release RESET */
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immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_IDE_RESET;
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}
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/* program port pin as GPIO output */
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immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_IDE_RESET);
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immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_IDE_RESET);
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immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_IDE_RESET;
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}
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/* ------------------------------------------------------------------------- */
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@ -1,91 +0,0 @@
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/*
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* (C) Copyright 2000-2010
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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OUTPUT_ARCH(powerpc)
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SECTIONS
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{
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/* Read-only sections, merged into text segment: */
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. = + SIZEOF_HEADERS;
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.text :
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{
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/* WARNING - the following is hand-optimized to fit within */
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/* the sector layout of our flash chips! XXX FIXME XXX */
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arch/powerpc/cpu/mpc8xx/start.o (.text*)
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arch/powerpc/cpu/mpc8xx/traps.o (.text*)
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net/built-in.o (.text*)
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arch/powerpc/cpu/mpc8xx/built-in.o (.text*)
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*(.text.v*printf)
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. = DEFINED(env_offset) ? env_offset : .;
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common/env_embedded.o (.ppcenv*)
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*(.text*)
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}
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_etext = .;
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PROVIDE (etext = .);
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.rodata :
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{
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*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
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}
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/* Read-write section, merged into data segment: */
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. = (. + 0x0FF) & 0xFFFFFF00;
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_erotext = .;
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PROVIDE (erotext = .);
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.reloc :
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{
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_GOT2_TABLE_ = .;
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KEEP(*(.got2))
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KEEP(*(.got))
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PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
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_FIXUP_TABLE_ = .;
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KEEP(*(.fixup))
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}
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__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
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__fixup_entries = (. - _FIXUP_TABLE_)>>2;
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.data :
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{
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*(.data*)
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*(.sdata*)
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}
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_edata = .;
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PROVIDE (edata = .);
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. = .;
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. = ALIGN(4);
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.u_boot_list : {
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KEEP(*(SORT(.u_boot_list*)));
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}
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. = .;
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__start___ex_table = .;
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__ex_table : { *(__ex_table) }
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__stop___ex_table = .;
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. = ALIGN(256);
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__init_begin = .;
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.text.init : { *(.text.init) }
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.data.init : { *(.data.init) }
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. = ALIGN(256);
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__init_end = .;
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__bss_start = .;
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.bss (NOLOAD) :
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{
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*(.bss*)
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*(.sbss*)
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*(COMMON)
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. = ALIGN(4);
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}
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__bss_end = . ;
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PROVIDE (end = .);
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}
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|
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@ -1,122 +0,0 @@
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/*
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* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
arch/powerpc/cpu/mpc8xx/start.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib/vsprintf.o (.text)
|
||||
lib/crc32.o (.text)
|
||||
arch/powerpc/lib/extable.o (.text)
|
||||
|
||||
. = env_offset;
|
||||
common/env_embedded.o(.text)
|
||||
|
||||
*(.text)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
*(.eh_frame)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x0FFF) & 0xFFFFF000;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
.u_boot_list : {
|
||||
KEEP(*(SORT(.u_boot_list*)));
|
||||
}
|
||||
|
||||
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(4096);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(4096);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
__bss_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
|
@ -88,7 +88,6 @@ flash_protect (int flag, ulong from, ulong to, flash_info_t *info)
|
|||
flash_info_t *
|
||||
addr2info (ulong addr)
|
||||
{
|
||||
#ifndef CONFIG_SPD823TS
|
||||
flash_info_t *info;
|
||||
int i;
|
||||
|
||||
|
|
@ -104,7 +103,6 @@ addr2info (ulong addr)
|
|||
return (info);
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_SPD823TS */
|
||||
|
||||
return (NULL);
|
||||
}
|
||||
|
|
@ -125,9 +123,6 @@ addr2info (ulong addr)
|
|||
int
|
||||
flash_write (char *src, ulong addr, ulong cnt)
|
||||
{
|
||||
#ifdef CONFIG_SPD823TS
|
||||
return (ERR_TIMOUT); /* any other error codes are possible as well */
|
||||
#else
|
||||
int i;
|
||||
ulong end = addr + cnt - 1;
|
||||
flash_info_t *info_first = addr2info (addr);
|
||||
|
|
@ -181,7 +176,6 @@ flash_write (char *src, ulong addr, ulong cnt)
|
|||
#endif /* CONFIG_SYS_FLASH_VERIFY_AFTER_WRITE */
|
||||
|
||||
return (ERR_OK);
|
||||
#endif /* CONFIG_SPD823TS */
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
|
|
|
|||
|
|
@ -1,3 +0,0 @@
|
|||
CONFIG_PPC=y
|
||||
CONFIG_8xx=y
|
||||
CONFIG_TARGET_SPD823TS=y
|
||||
|
|
@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
|
|||
|
||||
Board Arch CPU Commit Removed Last known maintainer/contact
|
||||
=================================================================================================
|
||||
SPD823TS powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
|
||||
KUP4K powerpc mpc8xx - - Klaus Heydeck <heydeck@kieback-peter.de>
|
||||
KUP4X powerpc mpc8xx - - Klaus Heydeck <heydeck@kieback-peter.de>
|
||||
ELPT860 powerpc mpc8xx - - The LEOX team <team@leox.org>
|
||||
|
|
|
|||
|
|
@ -627,35 +627,6 @@ typedef struct scc_enet {
|
|||
|
||||
#endif /* CONFIG_NETVIA */
|
||||
|
||||
/*** SPD823TS ******************************************************/
|
||||
|
||||
#ifdef CONFIG_SPD823TS
|
||||
/* Bits in parallel I/O port registers that have to be set/cleared
|
||||
* to configure the pins for SCC2 use.
|
||||
*/
|
||||
#define PROFF_ENET PROFF_SCC2 /* Ethernet on SCC2 */
|
||||
#define CPM_CR_ENET CPM_CR_CH_SCC2
|
||||
#define SCC_ENET 1
|
||||
#define PA_ENET_MDC ((ushort)0x0001) /* PA 15 !!! */
|
||||
#define PA_ENET_MDIO ((ushort)0x0002) /* PA 14 !!! */
|
||||
#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
|
||||
#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
|
||||
#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
|
||||
#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
|
||||
|
||||
#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
|
||||
|
||||
#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
|
||||
#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
|
||||
#define PC_ENET_RESET ((ushort)0x0100) /* PC 7 !!! */
|
||||
|
||||
/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
|
||||
* SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
|
||||
*/
|
||||
#define SICR_ENET_MASK ((uint)0x0000ff00)
|
||||
#define SICR_ENET_CLKRT ((uint)0x00002E00)
|
||||
#endif /* CONFIG_SPD823TS */
|
||||
|
||||
/*** MVS1, TQM823L/M, TQM850L/M, TQM885D, R360MPI **********/
|
||||
|
||||
#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
|
||||
|
|
|
|||
|
|
@ -1,402 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
|
||||
#define CONFIG_SPD823TS 1 /* ...on a SPD823TS board */
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFF000000
|
||||
|
||||
#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
|
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
|
||||
#undef CONFIG_8xx_CONS_SMC2
|
||||
#undef CONFIG_8xx_CONS_NONE
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#if 0
|
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
|
||||
#else
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
#endif
|
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
|
||||
|
||||
#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
|
||||
|
||||
#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
|
||||
"nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
|
||||
"nfsaddrs=10.0.0.99:10.0.0.2"
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_IDE
|
||||
|
||||
#undef CONFIG_CMD_SAVEENV
|
||||
#undef CONFIG_CMD_FLASH
|
||||
|
||||
|
||||
#define CONFIG_MAC_PARTITION
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_SUBNETMASK
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
#define CONFIG_ETHADDR 00:D0:93:00:01:CB
|
||||
#define CONFIG_IPADDR 10.0.0.98
|
||||
#define CONFIG_SERVERIP 10.0.0.1
|
||||
#undef CONFIG_BOOTCOMMAND
|
||||
#define CONFIG_BOOTCOMMAND "tftp 200000 uImage;bootm 200000"
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
|
||||
|
||||
#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
|
||||
|
||||
#define CONFIG_SYS_PC_IDE_RESET ((ushort)0x0008) /* PC 12 */
|
||||
|
||||
/*
|
||||
* Low Level Configuration Settings
|
||||
* (address mappings, register initial values, etc.)
|
||||
* You should know what you are doing if you make changes here.
|
||||
*/
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register
|
||||
*/
|
||||
#define CONFIG_SYS_IMMR 0xFFF00000 /* was: 0xFF000000 */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_FLASH_BASE 0xFF000000
|
||||
#ifdef DEBUG
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
|
||||
#else
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||
#endif
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 0 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 0 /* max number of sectors on one chip */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 0 /* Timeout for Flash Erase (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 0 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
|
||||
#define CONFIG_ENV_SIZE 0x0800 /* Total Size of Environment Sector */
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9
|
||||
* SYPCR can only be written once after reset!
|
||||
*-----------------------------------------------------------------------
|
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
|
||||
*/
|
||||
#if defined(CONFIG_WATCHDOG)
|
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
|
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
|
||||
#else
|
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6
|
||||
*-----------------------------------------------------------------------
|
||||
* PCMCIA config., multi-function pin tri-state
|
||||
*/
|
||||
/* 0x00000040 */
|
||||
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_GB5E)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Reference Interrupt Status, Timebase freezing enabled
|
||||
*/
|
||||
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
|
||||
*/
|
||||
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
|
||||
*-----------------------------------------------------------------------
|
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer
|
||||
* interrupt status bit, set PLL multiplication factor !
|
||||
*/
|
||||
/* 0x00b0c0c0 */
|
||||
#define CONFIG_SYS_PLPRCR \
|
||||
( (11 << PLPRCR_MF_SHIFT) | \
|
||||
PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \
|
||||
/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
|
||||
PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
|
||||
)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
*-----------------------------------------------------------------------
|
||||
* Set clock output, timebase and RTC source and divider,
|
||||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK SCCR_EBDF11
|
||||
/* 0x01800014 */
|
||||
#define CONFIG_SYS_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \
|
||||
SCCR_RTDIV | SCCR_RTSEL | \
|
||||
/*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
|
||||
SCCR_EBDF00 | SCCR_DFSYNC00 | \
|
||||
SCCR_DFBRG00 | SCCR_DFNL000 | \
|
||||
SCCR_DFNH000 | SCCR_DFLCD101 | \
|
||||
SCCR_DFALCD00)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
/* 0x00C3 */
|
||||
#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RCCR - RISC Controller Configuration Register
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
/* TIMEP=2 */
|
||||
#define CONFIG_SYS_RCCR 0x0200
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RMDS - RISC Microcode Development Support Control Register
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_SYS_RMDS 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SDSR - SDMA Status Register
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_SYS_SDSR ((u_char)0x83)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SDMR - SDMA Mask Register
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_SYS_SDMR ((u_char)0x00)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*
|
||||
* Interrupt Levels
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
|
||||
#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
|
||||
#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
|
||||
#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
|
||||
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
|
||||
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
|
||||
#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
|
||||
#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
|
||||
#define CONFIG_IDE_INIT_POSTRESET 1 /* Use postreset IDE hook */
|
||||
#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */
|
||||
#define CONFIG_IDE_LED 1 /* LED for ide supported */
|
||||
#define CONFIG_IDE_RESET 1 /* reset for ide supported */
|
||||
|
||||
#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
|
||||
#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
|
||||
|
||||
#define CONFIG_SYS_ATA_BASE_ADDR 0xFE100000
|
||||
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
|
||||
#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0C00
|
||||
|
||||
#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
|
||||
#define CONFIG_SYS_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */
|
||||
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*
|
||||
*-----------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
#define CONFIG_SYS_DER 0
|
||||
|
||||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* BR0/1 and OR0/1 (FLASH)
|
||||
*/
|
||||
|
||||
#define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */
|
||||
#define FLASH_BASE1_PRELIM 0xFF080000 /* FLASH bank #1 */
|
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any)
|
||||
* but not too much to meddle with FLASH accesses
|
||||
*/
|
||||
/* EPROMs are 512kb */
|
||||
#define CONFIG_SYS_REMAP_OR_AM 0xFFF80000 /* OR addr mask */
|
||||
#define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */
|
||||
|
||||
/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
|
||||
#define CONFIG_SYS_OR_TIMING_FLASH (/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \
|
||||
OR_SCY_5_CLK | OR_EHTR)
|
||||
|
||||
#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
|
||||
#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
|
||||
/* 16 bit, bank valid */
|
||||
#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
|
||||
|
||||
#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
|
||||
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
|
||||
/* 16 bit, bank valid */
|
||||
#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
|
||||
|
||||
/*
|
||||
* BR2-5 and OR2-5 (SRAM/SDRAM/PER8/SHARC)
|
||||
*
|
||||
*/
|
||||
#define SRAM_BASE 0xFE200000 /* SRAM bank */
|
||||
#define SRAM_OR_AM 0xFFE00000 /* SRAM is 2 MB */
|
||||
|
||||
#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
|
||||
#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
|
||||
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
|
||||
|
||||
#define PER8_BASE 0xFE000000 /* PER8 bank */
|
||||
#define PER8_OR_AM 0xFFF00000 /* PER8 is 1 MB */
|
||||
|
||||
#define SHARC_BASE 0xFE400000 /* SHARC bank */
|
||||
#define SHARC_OR_AM 0xFFC00000 /* SHARC is 4 MB */
|
||||
|
||||
/* SRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
|
||||
|
||||
#define CONFIG_SYS_OR_TIMING_SRAM 0x00000D42 /* SRAM-Timing */
|
||||
#define CONFIG_SYS_OR2 (SRAM_OR_AM | CONFIG_SYS_OR_TIMING_SRAM )
|
||||
#define CONFIG_SYS_BR2 ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V )
|
||||
|
||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
|
||||
|
||||
#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 /* SDRAM-Timing */
|
||||
#define CONFIG_SYS_OR3_PRELIM (SDRAM_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
|
||||
#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )
|
||||
|
||||
#define CONFIG_SYS_OR_TIMING_PER8 0x00000F32 /* PER8-Timing */
|
||||
#define CONFIG_SYS_OR4 (PER8_OR_AM | CONFIG_SYS_OR_TIMING_PER8 )
|
||||
#define CONFIG_SYS_BR4 ((PER8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
|
||||
|
||||
#define CONFIG_SYS_OR_TIMING_SHARC 0x00000700 /* SHARC-Timing */
|
||||
#define CONFIG_SYS_OR5 (SHARC_OR_AM | CONFIG_SYS_OR_TIMING_SHARC )
|
||||
#define CONFIG_SYS_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler
|
||||
*/
|
||||
|
||||
/* periodic timer for refresh */
|
||||
#define CONFIG_SYS_MBMR_PTB 204
|
||||
|
||||
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
|
||||
#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
|
||||
#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
|
||||
|
||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
|
||||
#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
|
||||
#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
|
||||
|
||||
/*
|
||||
* MBMR settings for SDRAM
|
||||
*/
|
||||
|
||||
/* 8 column SDRAM */
|
||||
#define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
|
||||
MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \
|
||||
MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -23,8 +23,6 @@
|
|||
|
||||
#if defined(CONFIG_TQM8xxL)
|
||||
# define CONFIG_PCMCIA_SLOT_B /* The TQM8xxL use SLOT_B */
|
||||
#elif defined(CONFIG_SPD823TS) /* The SPD8xx use SLOT_B */
|
||||
# define CONFIG_PCMCIA_SLOT_B
|
||||
#elif defined(CONFIG_IVMS8) || defined(CONFIG_IVML24) /* The IVM* use SLOT_A */
|
||||
# define CONFIG_PCMCIA_SLOT_A
|
||||
#elif defined(CONFIG_LWMON) /* The LWMON use SLOT_B */
|
||||
|
|
|
|||
Loading…
Reference in a new issue