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https://github.com/AsahiLinux/u-boot
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arm: socfpga: Add Altera Arria V DK support
Add support for the Altera Arria V development kit. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com>
This commit is contained in:
Marek Vasut
parent
d7a73038f5
commit
c115a0d4e7
7 changed files with 1043 additions and 0 deletions
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@ -567,6 +567,11 @@ config TARGET_CM_FX6
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select CPU_V7
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select SUPPORT_SPL
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config TARGET_SOCFPGA_ARRIA5
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bool "Support socfpga_arria5"
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select CPU_V7
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select SUPPORT_SPL
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config TARGET_SOCFPGA_CYCLONE5
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bool "Support socfpga_cyclone5"
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select CPU_V7
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@ -13,3 +13,19 @@ config SYS_CONFIG_NAME
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default "socfpga_cyclone5"
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endif
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if TARGET_SOCFPGA_ARRIA5
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config SYS_BOARD
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default "socfpga"
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config SYS_VENDOR
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default "altera"
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config SYS_SOC
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default "socfpga"
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config SYS_CONFIG_NAME
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default "socfpga_arria5"
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endif
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@ -8,6 +8,7 @@
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#include <iocsr_config.h>
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#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5
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const unsigned long iocsr_scan_chain0_table[((
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CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
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0x00000000,
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@ -655,3 +656,690 @@ const unsigned long iocsr_scan_chain3_table[((
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0x0000001F,
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0x00004100,
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};
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#endif /* CONFIG_TARGET_SOCFPGA_CYCLONE5 */
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#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5
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const unsigned long iocsr_scan_chain0_table[((
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CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00008000,
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0x00060180,
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0x18060000,
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0x18000060,
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0x00018060,
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0x06018060,
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0x00004000,
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0x0C0300C0,
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0x0C030000,
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0x00000030,
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0x00000000,
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0x00000000,
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0x00002000,
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0x00000000,
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0x00000000,
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0x06000000,
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0x00006018,
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0x01806018,
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0x00001000,
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0x0000C030,
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0x04000000,
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0x03000000,
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0x0000300C,
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0x00000000,
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0x00000800,
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0x00006018,
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0x01806000,
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0x01800000,
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0x00000006,
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0x00001806,
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0x00000400,
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0x0000300C,
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0x00C03000,
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0x00C00000,
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0x00000003,
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0x00000C03,
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0x00000200,
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};
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const unsigned long iocsr_scan_chain1_table[((
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CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = {
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0x00100000,
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0x300C0000,
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0x300000C0,
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0x000000C0,
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0x000300C0,
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0x00008000,
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0x00060180,
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0x18060000,
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0x18000000,
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0x00000060,
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0x00018060,
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0x00004000,
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0x000300C0,
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0x10000000,
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0x0C000000,
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0x00000030,
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0x0000C030,
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0x00002000,
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0x06018060,
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0x06018000,
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0x01FE0000,
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0xF8000000,
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0x00000007,
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0x00001000,
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0x0000C030,
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0x0300C000,
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0x03000000,
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0x0000300C,
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0x0000300C,
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0x00000800,
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0x00006018,
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0x01806000,
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0x01800000,
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0x00000006,
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0x00002000,
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0x00000400,
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0x0000300C,
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0x01000000,
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0x00000000,
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0x00000004,
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0x00000C03,
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0x00000200,
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0x00001806,
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0x00800000,
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0x00000000,
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0x00000002,
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0x00000800,
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0x00000100,
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0x00001000,
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0x00400000,
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0xC0300000,
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0x00000000,
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0x00000400,
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0x00000080,
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};
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const unsigned long iocsr_scan_chain2_table[((
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CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = {
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0x00100000,
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0x40000000,
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0x00000000,
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0x00000100,
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0x00040000,
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0x00008000,
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0x18060180,
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0x20000000,
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0x00000000,
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0x00000080,
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0x00020000,
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0x00004000,
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0x00040000,
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0x10000000,
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0x00000000,
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0x00000000,
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0x00010000,
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0x00002000,
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0x10038060,
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0x00000000,
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0x00000000,
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0x00000020,
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0x01806018,
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0x00001000,
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0x00010000,
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0x04000000,
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0x03000000,
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0x0000801C,
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0x00004000,
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0x00000800,
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0x01806018,
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0x02000000,
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0x00000000,
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0x00000008,
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0x00002000,
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0x00000400,
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0x00C0300C,
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0x00C03000,
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0x00C00003,
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0x00000C03,
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0x00300C03,
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0x00000200,
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0x00601806,
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0x80601800,
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0x80600001,
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0x80000601,
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0x00180601,
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0x00000100,
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};
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const unsigned long iocsr_scan_chain3_table[((
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CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = {
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0x2C820D80,
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0x082000FF,
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0x0A804001,
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0x07900000,
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0x08020000,
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0x00100000,
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0x0A800000,
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0x07900000,
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0x08020000,
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0x00100000,
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0xC8800000,
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0x00003001,
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0x00C00722,
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0x00000000,
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0x00000021,
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0x82000004,
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0x05400000,
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0x03C80000,
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0x04010000,
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0x00080000,
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0x05400000,
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0x03C80000,
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0x05400000,
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0x03C80000,
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0xE4400000,
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0x00001800,
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0x00600391,
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0x800E4400,
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0x00000001,
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0x40000002,
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0x02A00000,
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0x01E40000,
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0x02A00000,
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0x01E40000,
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0x02A00000,
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0x01E40000,
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0x02A00000,
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0x01E40000,
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0x72200000,
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0x80000C00,
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0x003001C8,
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0xC0072200,
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0x1C880000,
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0x20000300,
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0x00040000,
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0x50670000,
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0x00000050,
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0x24590000,
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0x00001000,
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0xA0000034,
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0x0D000001,
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0x906808A2,
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0xA2834024,
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0x05141A00,
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0x808A20D0,
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0x34024906,
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0x01A00A28,
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0xA20D0000,
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0x24906808,
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0x00A28340,
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0xD000001A,
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0x06808A20,
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0x10040000,
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0x00200000,
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0x10040000,
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0x00200000,
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0x15000000,
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0x0F200000,
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0x15000000,
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0x0F200000,
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0x01FE0000,
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0x00000000,
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0x01800E44,
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0x00391000,
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0x007F8006,
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0x00000000,
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0x0A800001,
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0x07900000,
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0x0A800000,
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0x07900000,
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0x0A800000,
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0x07900000,
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0x08020000,
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0x00100000,
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0xC8800000,
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0x00003001,
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0x00C00722,
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0x00000FF0,
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0x72200000,
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0x80000C00,
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0x05400000,
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0x02480000,
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0x04000000,
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0x00080000,
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0x05400000,
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0x03C80000,
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0x05400000,
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0x03C80000,
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0x6A1C0000,
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0x00001800,
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0x00600391,
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0x800E4400,
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0x1A870001,
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0x40000600,
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0x02A00040,
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0x01E40000,
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0x02A00000,
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0x01E40000,
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0x02A00000,
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0x01E40000,
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0x02A00000,
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0x01E40000,
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0x72200000,
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0x80000C00,
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0x003001C8,
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0xC0072200,
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0x1C880000,
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0x20000300,
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0x00040000,
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0x50670000,
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0x00000050,
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0x24590000,
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0x00001000,
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0xA0000034,
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0x0D000001,
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0x906808A2,
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0xA2834024,
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0x05141A00,
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0x808A20D0,
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0x34024906,
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0x01A00040,
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0xA20D0002,
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0x24906808,
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0x00A28340,
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0xD005141A,
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0x06808A20,
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0x10040000,
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0x00200000,
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0x10040000,
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0x00200000,
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0x15000000,
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0x0F200000,
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0x15000000,
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0x0F200000,
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0x01FE0000,
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0x00000000,
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0x01800E44,
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0x00391000,
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0x007F8006,
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0x00000000,
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0x99300001,
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0x34343400,
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0xAA0D4000,
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0x01C3A810,
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0xAA0D4000,
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0x01C3A808,
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0xAA0D4000,
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0x01C3A810,
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0x00040100,
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0x00000800,
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0x00000000,
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0x00001208,
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0x00482000,
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0x01000000,
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0x00000000,
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0x00410482,
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0x0006A000,
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0x0001B400,
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0x00020000,
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0x00000400,
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0x0002A000,
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0x0001E400,
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0x5506A000,
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0x00E1D404,
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0x00000000,
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0xC880090C,
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0x00003001,
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0x90400000,
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0x00000000,
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0x2020C243,
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0x2A835000,
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0x0070EA04,
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0x2A835000,
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0x0070EA02,
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0x2A835000,
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0x0070EA04,
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0x00010040,
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0x00000200,
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0x00000000,
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0x00000482,
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0x00120800,
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0x00002000,
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0x80000000,
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0x00104120,
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0x00000200,
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0xAC055F80,
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0xFFFFFFFF,
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0x14F3690D,
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0x1A041414,
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0x00D00000,
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0x14864000,
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0x59647A05,
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0xBA28A3D8,
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0xF511451E,
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0x0341D348,
|
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0x821A0000,
|
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0x0000D000,
|
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0x04510680,
|
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0xD859647A,
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0x1EBA28A3,
|
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0x48F51145,
|
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0x000341D3,
|
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0x00080200,
|
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0x00001000,
|
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0x00080200,
|
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0x00001000,
|
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0x000A8000,
|
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0x00075000,
|
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0x541A8000,
|
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0x03875011,
|
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0x10000000,
|
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0x00000000,
|
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0x0080C000,
|
||||
0x41000000,
|
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0x00003FC2,
|
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0x00820000,
|
||||
0xAA0D4000,
|
||||
0x01C3A810,
|
||||
0xAA0D4000,
|
||||
0x01C3A808,
|
||||
0xAA0D4000,
|
||||
0x01C3A810,
|
||||
0x00040100,
|
||||
0x00000800,
|
||||
0x00000000,
|
||||
0x00001208,
|
||||
0x00482000,
|
||||
0x00008000,
|
||||
0x00000000,
|
||||
0x00410482,
|
||||
0x0006A000,
|
||||
0x0001B400,
|
||||
0x00020000,
|
||||
0x00000400,
|
||||
0x00020080,
|
||||
0x00000400,
|
||||
0x5506A000,
|
||||
0x00E1D404,
|
||||
0x00000000,
|
||||
0x0000090C,
|
||||
0x00000010,
|
||||
0x90400000,
|
||||
0x00000000,
|
||||
0x2020C243,
|
||||
0x2A835000,
|
||||
0x0070EA04,
|
||||
0x2A835000,
|
||||
0x0070EA02,
|
||||
0x2A835000,
|
||||
0x0070EA04,
|
||||
0x00015000,
|
||||
0x0000F200,
|
||||
0x00000000,
|
||||
0x00000482,
|
||||
0x00120800,
|
||||
0x00600391,
|
||||
0x80000000,
|
||||
0x00104120,
|
||||
0x00000200,
|
||||
0xAC055F80,
|
||||
0xFFFFFFFF,
|
||||
0x14F3690D,
|
||||
0x1A041414,
|
||||
0x00D00000,
|
||||
0x14864000,
|
||||
0x59647A05,
|
||||
0xBA28A3D8,
|
||||
0xF511451E,
|
||||
0x8341D348,
|
||||
0x821A0124,
|
||||
0x0000D000,
|
||||
0x00000680,
|
||||
0xD859647A,
|
||||
0x1EBA28A3,
|
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0x48F51145,
|
||||
0x000341D3,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x000A8000,
|
||||
0x00075000,
|
||||
0x541A8000,
|
||||
0x03875011,
|
||||
0x10000000,
|
||||
0x00000000,
|
||||
0x0080C000,
|
||||
0x41000000,
|
||||
0x04000002,
|
||||
0x00820000,
|
||||
0xAA0D4000,
|
||||
0x01C3A810,
|
||||
0xAA0D4000,
|
||||
0x01C3A808,
|
||||
0xAA0D4000,
|
||||
0x01C3A810,
|
||||
0x00040100,
|
||||
0x00000800,
|
||||
0x00000000,
|
||||
0x00001208,
|
||||
0x00482000,
|
||||
0x00008000,
|
||||
0x00000000,
|
||||
0x00410482,
|
||||
0x0006A000,
|
||||
0x0001B400,
|
||||
0x00020000,
|
||||
0x00000400,
|
||||
0x0002A000,
|
||||
0x0001E400,
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||||
0x5506A000,
|
||||
0x00E1D404,
|
||||
0x00000000,
|
||||
0xC880090C,
|
||||
0x00003001,
|
||||
0x90400000,
|
||||
0x00000000,
|
||||
0x2020C243,
|
||||
0x2A835000,
|
||||
0x0070EA04,
|
||||
0x2A835000,
|
||||
0x0070EA02,
|
||||
0x2A835000,
|
||||
0x0070EA04,
|
||||
0x00010040,
|
||||
0x00000200,
|
||||
0x00000000,
|
||||
0x00000482,
|
||||
0x00120800,
|
||||
0x00002000,
|
||||
0x80000000,
|
||||
0x00104120,
|
||||
0x00000200,
|
||||
0xAC055F80,
|
||||
0xFFFFFFFF,
|
||||
0x14F3690D,
|
||||
0x1A041414,
|
||||
0x00D00000,
|
||||
0x14864000,
|
||||
0x59647A05,
|
||||
0xBA28A3D8,
|
||||
0xF511451E,
|
||||
0x0341D348,
|
||||
0x821A0000,
|
||||
0x0000D000,
|
||||
0x00000680,
|
||||
0xD859647A,
|
||||
0x1EBA28A3,
|
||||
0x48F51145,
|
||||
0x000341D3,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x000A8000,
|
||||
0x00075000,
|
||||
0x541A8000,
|
||||
0x03875011,
|
||||
0x10000000,
|
||||
0x00000000,
|
||||
0x0080C000,
|
||||
0x41000000,
|
||||
0x04000002,
|
||||
0x00820000,
|
||||
0xAA0D4000,
|
||||
0x01C3A810,
|
||||
0xAA0D4000,
|
||||
0x01C3A808,
|
||||
0xAA0D4000,
|
||||
0x01C3A810,
|
||||
0x00040100,
|
||||
0x00000800,
|
||||
0x00000000,
|
||||
0x00001208,
|
||||
0x00482000,
|
||||
0x00008000,
|
||||
0x00000000,
|
||||
0x00410482,
|
||||
0x0006A000,
|
||||
0x0001B400,
|
||||
0x00020000,
|
||||
0x00000400,
|
||||
0x00020080,
|
||||
0x00000400,
|
||||
0x5506A000,
|
||||
0x00E1D404,
|
||||
0x00000000,
|
||||
0x0000090C,
|
||||
0x00000010,
|
||||
0x90400000,
|
||||
0x00000000,
|
||||
0x2020C243,
|
||||
0x2A835000,
|
||||
0x0070EA04,
|
||||
0x2A835000,
|
||||
0x0070EA02,
|
||||
0x2A835000,
|
||||
0x0070EA04,
|
||||
0x00010040,
|
||||
0x00000200,
|
||||
0x00000000,
|
||||
0x00000482,
|
||||
0x00120800,
|
||||
0x00400000,
|
||||
0x80000000,
|
||||
0x00104120,
|
||||
0x00000200,
|
||||
0xAC055F80,
|
||||
0xFFFFFFFF,
|
||||
0x14F1690D,
|
||||
0x1A041414,
|
||||
0x00D00000,
|
||||
0x14864000,
|
||||
0x59647A05,
|
||||
0xBA28A3D8,
|
||||
0xF511451E,
|
||||
0x0341D348,
|
||||
0x821A0000,
|
||||
0x0000D000,
|
||||
0x00000680,
|
||||
0xD859647A,
|
||||
0x1EBA28A3,
|
||||
0x48F51145,
|
||||
0x000341D3,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x000A8000,
|
||||
0x00075000,
|
||||
0x541A8000,
|
||||
0x03875011,
|
||||
0x10000000,
|
||||
0x00000000,
|
||||
0x0080C000,
|
||||
0x41000000,
|
||||
0x04000002,
|
||||
0x00820000,
|
||||
0x00481800,
|
||||
0x001A1A1A,
|
||||
0x085506A0,
|
||||
0x0000E1D4,
|
||||
0x045506A0,
|
||||
0x0000E1D4,
|
||||
0x085506A0,
|
||||
0x8000E1D4,
|
||||
0x00000200,
|
||||
0x00000004,
|
||||
0x04000000,
|
||||
0x00000009,
|
||||
0x00002410,
|
||||
0x00000040,
|
||||
0x41000000,
|
||||
0x00002082,
|
||||
0x00000350,
|
||||
0x000000DA,
|
||||
0x00000100,
|
||||
0x40000002,
|
||||
0x00000100,
|
||||
0x00000002,
|
||||
0x022A8350,
|
||||
0x000070EA,
|
||||
0x86000000,
|
||||
0x08000004,
|
||||
0x00000000,
|
||||
0x00482000,
|
||||
0x21800000,
|
||||
0x00101061,
|
||||
0x021541A8,
|
||||
0x00003875,
|
||||
0x011541A8,
|
||||
0x00003875,
|
||||
0x021541A8,
|
||||
0x20003875,
|
||||
0x00000080,
|
||||
0x00000001,
|
||||
0x41000000,
|
||||
0x00000002,
|
||||
0x00FF0904,
|
||||
0x00000000,
|
||||
0x90400000,
|
||||
0x00000820,
|
||||
0xC0000001,
|
||||
0xFFD602AF,
|
||||
0x86FFFFFF,
|
||||
0x0A0A78B4,
|
||||
0x000D020A,
|
||||
0x00006800,
|
||||
0x028A4320,
|
||||
0xEC2CB23D,
|
||||
0x8F5D1451,
|
||||
0xA47A88A2,
|
||||
0x0001A0E9,
|
||||
0x00410D00,
|
||||
0x40000068,
|
||||
0x3D000003,
|
||||
0x51EC2CB2,
|
||||
0xA28F5D14,
|
||||
0xE9A47A88,
|
||||
0x000001A0,
|
||||
0x00000401,
|
||||
0x00000008,
|
||||
0x00000401,
|
||||
0x00000008,
|
||||
0x00000540,
|
||||
0x000003A8,
|
||||
0x08AA0D40,
|
||||
0x8001C3A8,
|
||||
0x0000007F,
|
||||
0x00000000,
|
||||
0x00004060,
|
||||
0xE1208000,
|
||||
0x0000001F,
|
||||
0x00004100,
|
||||
};
|
||||
#endif /* CONFIG_TARGET_SOCFPGA_ARRIA5 */
|
||||
|
|
|
|||
|
|
@ -9,9 +9,18 @@
|
|||
#ifndef _PRELOADER_IOCSR_CONFIG_H_
|
||||
#define _PRELOADER_IOCSR_CONFIG_H_
|
||||
|
||||
#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (764)
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719)
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (955)
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (1337)
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719)
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (1528)
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766)
|
||||
#endif
|
||||
|
||||
#endif /*_PRELOADER_IOCSR_CONFIG_H_*/
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@
|
|||
|
||||
#include "pinmux_config.h"
|
||||
|
||||
#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5
|
||||
/* pin mux configuration data */
|
||||
unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {
|
||||
3, /* EMACIO0 */
|
||||
|
|
@ -212,3 +213,217 @@ unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {
|
|||
0, /* USB0USEFPGA */
|
||||
0 /* SPIM0USEFPGA */
|
||||
};
|
||||
#endif /* CONFIG_TARGET_SOCFPGA_CYCLONE5 */
|
||||
|
||||
#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5
|
||||
/* pin mux configuration data */
|
||||
unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {
|
||||
0, /* EMACIO0 */
|
||||
2, /* EMACIO1 */
|
||||
2, /* EMACIO2 */
|
||||
2, /* EMACIO3 */
|
||||
2, /* EMACIO4 */
|
||||
2, /* EMACIO5 */
|
||||
2, /* EMACIO6 */
|
||||
2, /* EMACIO7 */
|
||||
2, /* EMACIO8 */
|
||||
0, /* EMACIO9 */
|
||||
2, /* EMACIO10 */
|
||||
2, /* EMACIO11 */
|
||||
2, /* EMACIO12 */
|
||||
2, /* EMACIO13 */
|
||||
3, /* EMACIO14 */
|
||||
3, /* EMACIO15 */
|
||||
3, /* EMACIO16 */
|
||||
3, /* EMACIO17 */
|
||||
3, /* EMACIO18 */
|
||||
3, /* EMACIO19 */
|
||||
3, /* FLASHIO0 */
|
||||
0, /* FLASHIO1 */
|
||||
3, /* FLASHIO2 */
|
||||
3, /* FLASHIO3 */
|
||||
0, /* FLASHIO4 */
|
||||
0, /* FLASHIO5 */
|
||||
0, /* FLASHIO6 */
|
||||
0, /* FLASHIO7 */
|
||||
0, /* FLASHIO8 */
|
||||
3, /* FLASHIO9 */
|
||||
3, /* FLASHIO10 */
|
||||
3, /* FLASHIO11 */
|
||||
3, /* GENERALIO0 */
|
||||
3, /* GENERALIO1 */
|
||||
3, /* GENERALIO2 */
|
||||
3, /* GENERALIO3 */
|
||||
3, /* GENERALIO4 */
|
||||
3, /* GENERALIO5 */
|
||||
3, /* GENERALIO6 */
|
||||
3, /* GENERALIO7 */
|
||||
3, /* GENERALIO8 */
|
||||
0, /* GENERALIO9 */
|
||||
0, /* GENERALIO10 */
|
||||
0, /* GENERALIO11 */
|
||||
0, /* GENERALIO12 */
|
||||
0, /* GENERALIO13 */
|
||||
0, /* GENERALIO14 */
|
||||
3, /* GENERALIO15 */
|
||||
3, /* GENERALIO16 */
|
||||
2, /* GENERALIO17 */
|
||||
2, /* GENERALIO18 */
|
||||
0, /* GENERALIO19 */
|
||||
0, /* GENERALIO20 */
|
||||
0, /* GENERALIO21 */
|
||||
0, /* GENERALIO22 */
|
||||
3, /* GENERALIO23 */
|
||||
3, /* GENERALIO24 */
|
||||
0, /* GENERALIO25 */
|
||||
0, /* GENERALIO26 */
|
||||
0, /* GENERALIO27 */
|
||||
0, /* GENERALIO28 */
|
||||
0, /* GENERALIO29 */
|
||||
0, /* GENERALIO30 */
|
||||
0, /* GENERALIO31 */
|
||||
0, /* MIXED1IO0 */
|
||||
0, /* MIXED1IO1 */
|
||||
0, /* MIXED1IO2 */
|
||||
0, /* MIXED1IO3 */
|
||||
0, /* MIXED1IO4 */
|
||||
0, /* MIXED1IO5 */
|
||||
0, /* MIXED1IO6 */
|
||||
0, /* MIXED1IO7 */
|
||||
0, /* MIXED1IO8 */
|
||||
0, /* MIXED1IO9 */
|
||||
0, /* MIXED1IO10 */
|
||||
0, /* MIXED1IO11 */
|
||||
0, /* MIXED1IO12 */
|
||||
0, /* MIXED1IO13 */
|
||||
0, /* MIXED1IO14 */
|
||||
3, /* MIXED1IO15 */
|
||||
3, /* MIXED1IO16 */
|
||||
3, /* MIXED1IO17 */
|
||||
3, /* MIXED1IO18 */
|
||||
3, /* MIXED1IO19 */
|
||||
3, /* MIXED1IO20 */
|
||||
0, /* MIXED1IO21 */
|
||||
3, /* MIXED2IO0 */
|
||||
3, /* MIXED2IO1 */
|
||||
3, /* MIXED2IO2 */
|
||||
3, /* MIXED2IO3 */
|
||||
3, /* MIXED2IO4 */
|
||||
3, /* MIXED2IO5 */
|
||||
3, /* MIXED2IO6 */
|
||||
3, /* MIXED2IO7 */
|
||||
0, /* GPLINMUX48 */
|
||||
0, /* GPLINMUX49 */
|
||||
0, /* GPLINMUX50 */
|
||||
0, /* GPLINMUX51 */
|
||||
0, /* GPLINMUX52 */
|
||||
0, /* GPLINMUX53 */
|
||||
0, /* GPLINMUX54 */
|
||||
0, /* GPLINMUX55 */
|
||||
0, /* GPLINMUX56 */
|
||||
0, /* GPLINMUX57 */
|
||||
0, /* GPLINMUX58 */
|
||||
0, /* GPLINMUX59 */
|
||||
0, /* GPLINMUX60 */
|
||||
0, /* GPLINMUX61 */
|
||||
0, /* GPLINMUX62 */
|
||||
0, /* GPLINMUX63 */
|
||||
0, /* GPLINMUX64 */
|
||||
0, /* GPLINMUX65 */
|
||||
0, /* GPLINMUX66 */
|
||||
0, /* GPLINMUX67 */
|
||||
0, /* GPLINMUX68 */
|
||||
0, /* GPLINMUX69 */
|
||||
0, /* GPLINMUX70 */
|
||||
1, /* GPLMUX0 */
|
||||
1, /* GPLMUX1 */
|
||||
1, /* GPLMUX2 */
|
||||
1, /* GPLMUX3 */
|
||||
1, /* GPLMUX4 */
|
||||
1, /* GPLMUX5 */
|
||||
1, /* GPLMUX6 */
|
||||
1, /* GPLMUX7 */
|
||||
1, /* GPLMUX8 */
|
||||
1, /* GPLMUX9 */
|
||||
1, /* GPLMUX10 */
|
||||
1, /* GPLMUX11 */
|
||||
1, /* GPLMUX12 */
|
||||
1, /* GPLMUX13 */
|
||||
1, /* GPLMUX14 */
|
||||
1, /* GPLMUX15 */
|
||||
1, /* GPLMUX16 */
|
||||
1, /* GPLMUX17 */
|
||||
1, /* GPLMUX18 */
|
||||
1, /* GPLMUX19 */
|
||||
1, /* GPLMUX20 */
|
||||
1, /* GPLMUX21 */
|
||||
1, /* GPLMUX22 */
|
||||
1, /* GPLMUX23 */
|
||||
1, /* GPLMUX24 */
|
||||
1, /* GPLMUX25 */
|
||||
1, /* GPLMUX26 */
|
||||
1, /* GPLMUX27 */
|
||||
1, /* GPLMUX28 */
|
||||
1, /* GPLMUX29 */
|
||||
1, /* GPLMUX30 */
|
||||
1, /* GPLMUX31 */
|
||||
1, /* GPLMUX32 */
|
||||
1, /* GPLMUX33 */
|
||||
1, /* GPLMUX34 */
|
||||
1, /* GPLMUX35 */
|
||||
1, /* GPLMUX36 */
|
||||
1, /* GPLMUX37 */
|
||||
1, /* GPLMUX38 */
|
||||
1, /* GPLMUX39 */
|
||||
1, /* GPLMUX40 */
|
||||
1, /* GPLMUX41 */
|
||||
1, /* GPLMUX42 */
|
||||
1, /* GPLMUX43 */
|
||||
1, /* GPLMUX44 */
|
||||
1, /* GPLMUX45 */
|
||||
1, /* GPLMUX46 */
|
||||
1, /* GPLMUX47 */
|
||||
1, /* GPLMUX48 */
|
||||
1, /* GPLMUX49 */
|
||||
1, /* GPLMUX50 */
|
||||
1, /* GPLMUX51 */
|
||||
1, /* GPLMUX52 */
|
||||
1, /* GPLMUX53 */
|
||||
1, /* GPLMUX54 */
|
||||
1, /* GPLMUX55 */
|
||||
1, /* GPLMUX56 */
|
||||
1, /* GPLMUX57 */
|
||||
1, /* GPLMUX58 */
|
||||
1, /* GPLMUX59 */
|
||||
1, /* GPLMUX60 */
|
||||
1, /* GPLMUX61 */
|
||||
1, /* GPLMUX62 */
|
||||
1, /* GPLMUX63 */
|
||||
1, /* GPLMUX64 */
|
||||
1, /* GPLMUX65 */
|
||||
1, /* GPLMUX66 */
|
||||
1, /* GPLMUX67 */
|
||||
1, /* GPLMUX68 */
|
||||
1, /* GPLMUX69 */
|
||||
1, /* GPLMUX70 */
|
||||
0, /* NANDUSEFPGA */
|
||||
0, /* UART0USEFPGA */
|
||||
0, /* RGMII1USEFPGA */
|
||||
0, /* SPIS0USEFPGA */
|
||||
0, /* CAN0USEFPGA */
|
||||
0, /* I2C0USEFPGA */
|
||||
0, /* SDMMCUSEFPGA */
|
||||
0, /* QSPIUSEFPGA */
|
||||
0, /* SPIS1USEFPGA */
|
||||
0, /* RGMII0USEFPGA */
|
||||
0, /* UART1USEFPGA */
|
||||
0, /* CAN1USEFPGA */
|
||||
0, /* USB1USEFPGA */
|
||||
0, /* I2C3USEFPGA */
|
||||
0, /* I2C2USEFPGA */
|
||||
0, /* I2C1USEFPGA */
|
||||
0, /* SPIM1USEFPGA */
|
||||
0, /* USB0USEFPGA */
|
||||
0 /* SPIM0USEFPGA */
|
||||
};
|
||||
#endif /* CONFIG_TARGET_SOCFPGA_ARRIA5 */
|
||||
|
|
|
|||
3
configs/socfpga_arria5_defconfig
Normal file
3
configs/socfpga_arria5_defconfig
Normal file
|
|
@ -0,0 +1,3 @@
|
|||
CONFIG_SPL=y
|
||||
+S:CONFIG_ARM=y
|
||||
+S:CONFIG_TARGET_SOCFPGA_ARRIA5=y
|
||||
107
include/configs/socfpga_arria5.h
Normal file
107
include/configs/socfpga_arria5.h
Normal file
|
|
@ -0,0 +1,107 @@
|
|||
/*
|
||||
* Copyright (C) 2014 Marek Vasut <marex@denx.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef __CONFIG_SOCFPGA_ARRIA5_H__
|
||||
#define __CONFIG_SOCFPGA_ARRIA5_H__
|
||||
|
||||
#include <asm/arch/socfpga_base_addrs.h>
|
||||
#include "../../board/altera/socfpga/pinmux_config.h"
|
||||
#include "../../board/altera/socfpga/iocsr_config.h"
|
||||
#include "../../board/altera/socfpga/pll_config.h"
|
||||
|
||||
/* U-Boot Commands */
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
#include <config_cmd_default.h>
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_FAT_WRITE
|
||||
#define CONFIG_HW_WATCHDOG
|
||||
|
||||
#define CONFIG_CMD_ASKENV
|
||||
#define CONFIG_CMD_BOOTZ
|
||||
#define CONFIG_CMD_CACHE
|
||||
#define CONFIG_CMD_DFU
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_EXT4
|
||||
#define CONFIG_CMD_EXT4_WRITE
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_FPGA
|
||||
#define CONFIG_CMD_FS_GENERIC
|
||||
#define CONFIG_CMD_GREPENV
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_SETEXPR
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_CMD_USB_MASS_STORAGE
|
||||
|
||||
#define CONFIG_REGEX /* Enable regular expression support */
|
||||
|
||||
/* Memory configurations */
|
||||
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
|
||||
|
||||
/* Booting Linux */
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
#define CONFIG_BOOTFILE "zImage"
|
||||
#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
|
||||
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
|
||||
#define CONFIG_BOOTCOMMAND "run ramboot"
|
||||
#else
|
||||
#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
|
||||
#endif
|
||||
#define CONFIG_LOADADDR 0x8000
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
|
||||
/* Ethernet on SoC (EMAC) */
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
#define CONFIG_EMAC_BASE SOCFPGA_EMAC1_ADDRESS
|
||||
#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
|
||||
|
||||
/* PHY */
|
||||
#define CONFIG_PHY_MICREL
|
||||
#define CONFIG_PHY_MICREL_KSZ9021
|
||||
#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
|
||||
#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
|
||||
#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
|
||||
#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
|
||||
|
||||
#endif
|
||||
|
||||
/* USB */
|
||||
#ifdef CONFIG_CMD_USB
|
||||
#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
|
||||
#endif
|
||||
#define CONFIG_G_DNL_MANUFACTURER "Altera"
|
||||
|
||||
/* Extra Environment */
|
||||
#define CONFIG_HOSTNAME socfpga_arria5
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"verify=n\0" \
|
||||
"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
|
||||
"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
|
||||
"bootm ${loadaddr} - ${fdt_addr}\0" \
|
||||
"bootimage=zImage\0" \
|
||||
"fdt_addr=100\0" \
|
||||
"fdtimage=socfpga.dtb\0" \
|
||||
"fsloadcmd=ext2load\0" \
|
||||
"bootm ${loadaddr} - ${fdt_addr}\0" \
|
||||
"mmcroot=/dev/mmcblk0p2\0" \
|
||||
"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
|
||||
" root=${mmcroot} rw rootwait;" \
|
||||
"bootz ${loadaddr} - ${fdt_addr}\0" \
|
||||
"mmcload=mmc rescan;" \
|
||||
"load mmc 0:1 ${loadaddr} ${bootimage};" \
|
||||
"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
|
||||
"qspiroot=/dev/mtdblock0\0" \
|
||||
"qspirootfstype=jffs2\0" \
|
||||
"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
|
||||
" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
|
||||
"bootm ${loadaddr} - ${fdt_addr}\0"
|
||||
|
||||
/* The rest of the configuration is shared */
|
||||
#include <configs/socfpga_common.h>
|
||||
|
||||
#endif /* __CONFIG_SOCFPGA_ARRIA5_H__ */
|
||||
Loading…
Reference in a new issue