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ARM: OMAP5 / DRA7: Setup L2 Aux Control Register with recommended configuration

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Update to existing recommendation for L2ACTLR configuration to prevent
system instability and optimize performance.

These apply to both OMAP5 and DRA7.

Reported-by: Vivek Chengalvala <vchengalvala@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Nishanth Menon 2015-03-09 17:12:07 -05:00 committed by Tom Rini
parent 5f603761c3
commit fc7368ec85
1 changed files with 16 additions and 0 deletions
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16
arch/arm/cpu/armv7/omap5/hwinit.c
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@ -304,6 +304,21 @@ void config_data_eye_leveling_samples(u32 emif_base)
(*ctrl)->control_emif2_sdram_config_ext);
}
void init_cpu_configuration(void)
{
u32 l2actlr;
asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r"(l2actlr));
/*
* L2ACTLR: Ensure to enable the following:
* 3: Disable clean/evict push to external
* 4: Disable WriteUnique and WriteLineUnique transactions from master
* 8: Disable DVM/CMO message broadcast
*/
l2actlr |= 0x118;
omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2actlr);
}
void init_omap_revision(void)
{
/*
@ -342,6 +357,7 @@ void init_omap_revision(void)
default:
*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
}
init_cpu_configuration();
}
void reset_cpu(ulong ignored)