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x86: ivybridge: Drop support for ROM caching
This is set up along with CAR (Cache-as-RAM) anyway. When we relocate we don't really need ROM caching (we read the VGA BIOS from ROM but that is about it) Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
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1 changed files with 0 additions and 25 deletions
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@ -49,27 +49,6 @@ static void enable_spi_prefetch(struct pci_controller *hose, pci_dev_t dev)
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pci_hose_write_config_byte(hose, dev, 0xdc, reg8);
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}
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static void set_var_mtrr(
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unsigned reg, unsigned base, unsigned size, unsigned type)
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{
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/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
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/* FIXME: It only support 4G less range */
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wrmsr(MTRRphysBase_MSR(reg), base | type, 0);
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wrmsr(MTRRphysMask_MSR(reg), ~(size - 1) | MTRRphysMaskValid,
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(1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1);
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}
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static void enable_rom_caching(void)
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{
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disable_caches();
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set_var_mtrr(1, 0xffc00000, 4 << 20, MTRR_TYPE_WRPROT);
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enable_caches();
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/* Enable Variable MTRRs */
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wrmsr(MTRRdefType_MSR, 0x800, 0);
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}
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static int set_flex_ratio_to_tdp_nominal(void)
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{
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msr_t flex_ratio, msr;
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@ -165,10 +144,6 @@ int arch_cpu_init(void)
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/* This is already done in start.S, but let's do it in C */
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enable_port80_on_lpc(hose, PCH_LPC_DEV);
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/* already done in car.S */
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if (false)
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enable_rom_caching();
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set_spi_speed();
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/*
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