mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-11 07:34:31 +00:00
ARM: UniPhier: support 1CS support card for all the UniPhier SoCs
Two support card variants are used with UniPhier reference boards: - 1 chip select support card (original CPLD) - 3 chip selects support card (ARIMA-compatible CPLD) Currently, the former is only supported on PH1-Pro4, but it can be expanded to PH1-LD4, PH1-sLD8 with a little code change. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This commit is contained in:
Masahiro Yamada
parent
53c45d4e1e
commit
ea6de4ac80
9 changed files with 188 additions and 120 deletions
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@ -4,8 +4,10 @@
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ifdef CONFIG_SPL_BUILD
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obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
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obj-y += bcu_init.o sbc_init.o sg_init.o pll_init.o early_clkrst_init.o \
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obj-y += bcu_init.o sg_init.o pll_init.o early_clkrst_init.o \
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pll_spectrum.o umc_init.o ddrphy_init.o
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obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
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obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
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else
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obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
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obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
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@ -19,32 +19,32 @@ void sbc_init(void)
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tmp &= 0xfffffcff;
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writel(tmp, PC0CTRL);
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/* XECS1: sub/boot memory (boot swap = off/on) */
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writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
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writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
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writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
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writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
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/*
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* Only CS1 is connected to support card.
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* BKSZ[1:0] should be set to "01".
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*/
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writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
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writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
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writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
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writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
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/* XECS0: boot/sub memory (boot swap = off/on) */
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writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
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writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
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writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
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writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
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/* XECS3: peripherals */
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writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
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writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
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writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
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writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
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/* base address regsiters */
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writel(0x0000bc01, SBBASE0);
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writel(0x0400bc01, SBBASE1);
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writel(0x0800bf01, SBBASE3);
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/* enable access to sub memory when boot swap is on */
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if (boot_is_swapped())
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sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */
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sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */
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if (boot_is_swapped()) {
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/*
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* Boot Swap On: boot from external NOR/SRAM
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* 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff.
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*
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* 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank
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* 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals
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*/
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writel(0x0000bc01, SBBASE0);
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} else {
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/*
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* Boot Swap Off: boot from mask ROM
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* 0x00000000-0x01ffffff: mask ROM
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* 0x02000000-0x03efffff: memory bank (31MB)
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* 0x03f00000-0x03ffffff: peripherals (1MB)
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*/
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writel(0x0000be01, SBBASE0); /* dummy */
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writel(0x0200be01, SBBASE1);
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}
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}
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50
arch/arm/mach-uniphier/ph1-ld4/sbc_init_3cs.c
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50
arch/arm/mach-uniphier/ph1-ld4/sbc_init_3cs.c
Normal file
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@ -0,0 +1,50 @@
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/*
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* Copyright (C) 2011-2015 Panasonic Corporation
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* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <mach/sbc-regs.h>
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#include <mach/sg-regs.h>
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void sbc_init(void)
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{
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u32 tmp;
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/* system bus output enable */
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tmp = readl(PC0CTRL);
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tmp &= 0xfffffcff;
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writel(tmp, PC0CTRL);
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/* XECS1: sub/boot memory (boot swap = off/on) */
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writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
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writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
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writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
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writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
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/* XECS0: boot/sub memory (boot swap = off/on) */
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writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
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writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
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writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
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writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
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/* XECS3: peripherals */
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writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
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writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
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writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
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writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
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/* base address regsiters */
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writel(0x0000bc01, SBBASE0);
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writel(0x0400bc01, SBBASE1);
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writel(0x0800bf01, SBBASE3);
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/* enable access to sub memory when boot swap is on */
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if (boot_is_swapped())
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sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */
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sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */
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}
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@ -4,8 +4,10 @@
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ifdef CONFIG_SPL_BUILD
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obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
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obj-y += sbc_init.o sg_init.o pll_init.o early_clkrst_init.o \
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obj-y += sg_init.o pll_init.o early_clkrst_init.o \
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pll_spectrum.o umc_init.o ddrphy_init.o
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obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
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obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
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else
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obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
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obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
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@ -12,7 +12,6 @@
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void sbc_init(void)
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{
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#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
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/*
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* Only CS1 is connected to support card.
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* BKSZ[1:0] should be set to "01".
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@ -41,35 +40,4 @@ void sbc_init(void)
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writel(0x0000be01, SBBASE0); /* dummy */
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writel(0x0200be01, SBBASE1);
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}
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#elif defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
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/* XECS0: boot/sub memory (boot swap = off/on) */
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writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
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writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
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writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
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writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
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/* XECS1: sub/boot memory (boot swap = off/on) */
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writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
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writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
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writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
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writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
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/* XECS3: peripherals */
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writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
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writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
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writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
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writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
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writel(0x0000bc01, SBBASE0); /* boot memory */
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writel(0x0400bc01, SBBASE1); /* sub memory */
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writel(0x0800bf01, SBBASE3); /* peripherals */
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/* enable access to sub memory when boot swap is on */
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if (boot_is_swapped())
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sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */
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sg_set_pinsel(313, 5); /* PORT15 -> XECS3 */
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writel(0x00000001, SG_LOADPINCTRL);
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#endif /* CONFIG_XXX_MICRO_SUPPORT_CARD */
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}
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43
arch/arm/mach-uniphier/ph1-pro4/sbc_init_3cs.c
Normal file
43
arch/arm/mach-uniphier/ph1-pro4/sbc_init_3cs.c
Normal file
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@ -0,0 +1,43 @@
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/*
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* Copyright (C) 2011-2015 Panasonic Corporation
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* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <mach/sbc-regs.h>
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#include <mach/sg-regs.h>
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void sbc_init(void)
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{
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/* XECS0: boot/sub memory (boot swap = off/on) */
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writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
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writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
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writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
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writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
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/* XECS1: sub/boot memory (boot swap = off/on) */
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writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
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writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
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writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
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writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
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/* XECS3: peripherals */
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writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
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writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
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writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
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writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
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writel(0x0000bc01, SBBASE0); /* boot memory */
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writel(0x0400bc01, SBBASE1); /* sub memory */
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writel(0x0800bf01, SBBASE3); /* peripherals */
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/* enable access to sub memory when boot swap is on */
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if (boot_is_swapped())
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sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */
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sg_set_pinsel(313, 5); /* PORT15 -> XECS3 */
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writel(0x00000001, SG_LOADPINCTRL);
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}
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@ -4,8 +4,10 @@
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ifdef CONFIG_SPL_BUILD
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obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
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obj-y += bcu_init.o sbc_init.o sg_init.o pll_init.o early_clkrst_init.o \
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obj-y += bcu_init.o sg_init.o pll_init.o early_clkrst_init.o \
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pll_spectrum.o umc_init.o ddrphy_init.o
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obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
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obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
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else
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obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
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obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
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@ -1,58 +1 @@
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/*
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* Copyright (C) 2011-2015 Panasonic Corporation
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* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <mach/sbc-regs.h>
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#include <mach/sg-regs.h>
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void sbc_init(void)
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{
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u32 tmp;
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/* system bus output enable */
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tmp = readl(PC0CTRL);
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tmp &= 0xfffffcff;
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writel(tmp, PC0CTRL);
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/*
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* SBCTRL0* does not need settings because PH1-sLD8 has no support for
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* XECS0. The boot swap must be enabled to boot from the support card.
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*/
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if (boot_is_swapped()) {
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/* XECS1 : boot memory if boot swap is on */
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writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
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writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
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writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
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writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
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}
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/* XECS4 : sub memory */
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writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL40);
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writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL41);
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writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL42);
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writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL44);
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/* XECS5 : peripherals */
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writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL50);
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writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL51);
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writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL52);
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writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL54);
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/* base address regsiters */
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writel(0x0000bc01, SBBASE0); /* boot memory */
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writel(0x0900bfff, SBBASE1); /* dummy */
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writel(0x0400bc01, SBBASE4); /* sub memory */
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writel(0x0800bf01, SBBASE5); /* peripherals */
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sg_set_pinsel(134, 16); /* XIRQ6 -> XECS4 */
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sg_set_pinsel(135, 16); /* XIRQ7 -> XECS5 */
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/* dummy read to assure write process */
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readl(SG_PINCTRL(0));
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}
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#include "../ph1-ld4/sbc_init.c"
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58
arch/arm/mach-uniphier/ph1-sld8/sbc_init_3cs.c
Normal file
58
arch/arm/mach-uniphier/ph1-sld8/sbc_init_3cs.c
Normal file
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@ -0,0 +1,58 @@
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/*
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* Copyright (C) 2011-2015 Panasonic Corporation
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* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <mach/sbc-regs.h>
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#include <mach/sg-regs.h>
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void sbc_init(void)
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{
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u32 tmp;
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/* system bus output enable */
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tmp = readl(PC0CTRL);
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tmp &= 0xfffffcff;
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writel(tmp, PC0CTRL);
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/*
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* SBCTRL0* does not need settings because PH1-sLD8 has no support for
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* XECS0. The boot swap must be enabled to boot from the support card.
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*/
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if (boot_is_swapped()) {
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/* XECS1 : boot memory if boot swap is on */
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writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
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writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
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writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
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writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
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}
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/* XECS4 : sub memory */
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writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL40);
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writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL41);
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writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL42);
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writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL44);
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/* XECS5 : peripherals */
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writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL50);
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writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL51);
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writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL52);
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writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL54);
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/* base address regsiters */
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writel(0x0000bc01, SBBASE0); /* boot memory */
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writel(0x0900bfff, SBBASE1); /* dummy */
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writel(0x0400bc01, SBBASE4); /* sub memory */
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writel(0x0800bf01, SBBASE5); /* peripherals */
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sg_set_pinsel(134, 16); /* XIRQ6 -> XECS4 */
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sg_set_pinsel(135, 16); /* XIRQ7 -> XECS5 */
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/* dummy read to assure write process */
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readl(SG_PINCTRL(0));
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}
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