mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-25 06:00:43 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-arm
This commit is contained in:
Tom Rini
commit
3ad207a2bf
9 changed files with 16 additions and 143 deletions
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@ -1,9 +0,0 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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extra-y = start.o
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obj-y = cpu.o
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@ -1,8 +0,0 @@
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#
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# (C) Copyright 2002
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# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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PLATFORM_CPPFLAGS += -march=armv4
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@ -1,36 +0,0 @@
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/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* CPU specific code for an unknown cpu
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* - hence fairly empty......
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*/
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#include <common.h>
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#include <command.h>
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int cleanup_before_linux (void)
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{
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/*
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* this function is called just before we call linux
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* it prepares the processor for linux
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*
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* we turn off caches etc ...
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*/
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disable_interrupts ();
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/* Since the CM has unknown processor we do not support
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* cache operations
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*/
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return (0);
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}
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@ -1,79 +0,0 @@
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/*
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* armboot - Startup Code for ARM926EJS CPU-core
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*
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* Copyright (c) 2003 Texas Instruments
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*
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* ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
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*
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* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
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* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
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* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
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* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
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* Copyright (c) 2003 Kshitij <kshitij@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <version.h>
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/*
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*************************************************************************
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*
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* Startup Code (reset vector)
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*
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* do important init only if we don't start from memory!
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* setup memory and board specific bits prior to relocation.
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* relocate armboot to ram
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* setup stack
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*
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*************************************************************************
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*/
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.globl reset
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reset:
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/*
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* set the cpu to SVC32 mode
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*/
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mrs r0,cpsr
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bic r0,r0,#0x1f
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orr r0,r0,#0xd3
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msr cpsr,r0
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/*
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* we do sys-critical inits only at reboot,
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* not when booting from ram!
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*/
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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bl cpu_init_crit
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#endif
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bl _main
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/*------------------------------------------------------------------------------*/
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.globl c_runtime_cpu_setup
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c_runtime_cpu_setup:
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mov pc, lr
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/*
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*************************************************************************
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*
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* CPU_init_critical registers
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*
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* setup important registers
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* setup memory timing
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*
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*************************************************************************
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*/
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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cpu_init_crit:
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/* arm_int_generic assumes the ARM boot monitor, or user software,
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* has initialized the platform
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*/
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mov pc, lr /* back to my caller */
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#endif
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@ -21,7 +21,8 @@
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* to get size details from Current Cache Size ID Register(CCSIDR)
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*/
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static void set_csselr(u32 level, u32 type)
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{ u32 csselr = level << 1 | type;
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{
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u32 csselr = level << 1 | type;
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/* Write to Cache Size Selection Register(CSSELR) */
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asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr));
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@ -49,7 +50,8 @@ static void v7_inval_dcache_level_setway(u32 level, u32 num_sets,
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u32 num_ways, u32 way_shift,
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u32 log2_line_len)
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{
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int way, set, setway;
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int way, set;
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u32 setway;
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/*
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* For optimal assembly code:
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@ -73,7 +75,8 @@ static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
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u32 num_ways, u32 way_shift,
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u32 log2_line_len)
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{
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int way, set, setway;
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int way, set;
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u32 setway;
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/*
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* For optimal assembly code:
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@ -134,7 +137,6 @@ static void v7_maint_dcache_level_setway(u32 level, u32 operation)
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static void v7_maint_dcache_all(u32 operation)
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{
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u32 level, cache_type, level_start_bit = 0;
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u32 clidr = get_clidr();
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for (level = 0; level < 7; level++) {
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@ -147,8 +149,7 @@ static void v7_maint_dcache_all(u32 operation)
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}
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}
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static void v7_dcache_clean_inval_range(u32 start,
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u32 stop, u32 line_len)
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static void v7_dcache_clean_inval_range(u32 start, u32 stop, u32 line_len)
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{
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u32 mva;
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@ -256,7 +257,6 @@ void flush_dcache_all(void)
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*/
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void invalidate_dcache_range(unsigned long start, unsigned long stop)
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{
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v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE);
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v7_outer_cache_inval_range(start, stop);
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@ -201,7 +201,7 @@ enum {
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* \param size size of memory region to change
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* \param option dcache option to select
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*/
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void mmu_set_region_dcache_behaviour(u32 start, int size,
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void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
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enum dcache_option option);
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/**
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@ -47,15 +47,15 @@ __weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
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debug("%s: Warning: not implemented\n", __func__);
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}
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void mmu_set_region_dcache_behaviour(u32 start, int size,
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void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
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enum dcache_option option)
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{
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u32 *page_table = (u32 *)gd->arch.tlb_addr;
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u32 upto, end;
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unsigned long upto, end;
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end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
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start = start >> MMU_SECTION_SHIFT;
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debug("%s: start=%x, size=%x, option=%d\n", __func__, start, size,
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debug("%s: start=%pa, size=%zu, option=%d\n", __func__, &start, size,
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option);
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for (upto = start; upto < end; upto++)
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set_section_dcache(upto, option);
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@ -1533,6 +1533,9 @@ void mem_malloc_init(ulong start, ulong size)
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mem_malloc_end = start + size;
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mem_malloc_brk = start;
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debug("using memory %#lx-%#lx for malloc()\n", mem_malloc_start,
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mem_malloc_end);
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memset((void *)mem_malloc_start, 0, size);
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malloc_bin_reloc();
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@ -20,6 +20,8 @@
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#ifndef _CONFIG_KM_ARM_H
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#define _CONFIG_KM_ARM_H
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#define CONFIG_SYS_GENERIC_BOARD
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/* We got removed from Linux mach-types.h */
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#define MACH_TYPE_KM_KIRKWOOD 2255
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