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ARM: atmel: cleanup: remove at91cap9 related code
As the at91cap9adk board is removed by commit: b5508344
(ARM: remove broken "at91cap9adk" board), so the at91cap9
code is not used anymore, and also the document for
at91cap9 can not be found on www.atmel.com, so remove the
at91cap9 related code.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
This commit is contained in:
Bo Shen
Andreas Bießmann
parent
0b2a982420
commit
c6941e1203
8 changed files with 4 additions and 408 deletions
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@ -5,7 +5,6 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-$(CONFIG_AT91CAP9) += at91cap9_devices.o
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obj-$(CONFIG_AT91SAM9260) += at91sam9260_devices.o
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obj-$(CONFIG_AT91SAM9G20) += at91sam9260_devices.o
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obj-$(CONFIG_AT91SAM9XE) += at91sam9260_devices.o
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@ -1,189 +0,0 @@
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/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian@popies.net>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* (C) Copyright 2009
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* Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
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* esd electronic system design gmbh <www.esd.eu>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/io.h>
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void at91_serial0_hw_init(void)
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{
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at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
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at91_set_a_periph(AT91_PIO_PORTA, 22, 1); /* TXD0 */
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at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* RXD0 */
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writel(1 << AT91CAP9_ID_US0, &pmc->pcer);
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}
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void at91_serial1_hw_init(void)
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{
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at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
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at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* TXD1 */
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at91_set_a_periph(AT91_PIO_PORTD, 1, 0); /* RXD1 */
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writel(1 << AT91CAP9_ID_US1, &pmc->pcer);
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}
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void at91_serial2_hw_init(void)
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{
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at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
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at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* TXD2 */
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at91_set_a_periph(AT91_PIO_PORTD, 3, 0); /* RXD2 */
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writel(1 << AT91CAP9_ID_US2, &pmc->pcer);
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}
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void at91_serial3_hw_init(void)
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{
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at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
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at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* DRXD */
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at91_set_a_periph(AT91_PIO_PORTC, 31, 1); /* DTXD */
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writel(1 << AT91_ID_SYS, &pmc->pcer);
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}
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void at91_serial_hw_init(void)
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{
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#ifdef CONFIG_USART0
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at91_serial0_hw_init();
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#endif
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#ifdef CONFIG_USART1
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at91_serial1_hw_init();
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#endif
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#ifdef CONFIG_USART2
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at91_serial2_hw_init();
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#endif
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#ifdef CONFIG_USART3 /* DBGU */
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at91_serial3_hw_init();
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#endif
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}
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#ifdef CONFIG_HAS_DATAFLASH
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void at91_spi0_hw_init(unsigned long cs_mask)
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{
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at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
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at91_set_b_periph(AT91_PIO_PORTA, 0, 0); /* SPI0_MISO */
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at91_set_b_periph(AT91_PIO_PORTA, 1, 0); /* SPI0_MOSI */
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at91_set_b_periph(AT91_PIO_PORTA, 2, 0); /* SPI0_SPCK */
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/* Enable clock */
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writel(1 << AT91CAP9_ID_SPI0, &pmc->pcer);
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if (cs_mask & (1 << 0)) {
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at91_set_b_periph(AT91_PIO_PORTA, 5, 1);
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}
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if (cs_mask & (1 << 1)) {
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at91_set_b_periph(AT91_PIO_PORTA, 3, 1);
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}
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if (cs_mask & (1 << 2)) {
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at91_set_b_periph(AT91_PIO_PORTD, 0, 1);
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}
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if (cs_mask & (1 << 3)) {
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at91_set_b_periph(AT91_PIO_PORTD, 1, 1);
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}
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if (cs_mask & (1 << 4)) {
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at91_set_pio_output(AT91_PIO_PORTA, 5, 1);
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}
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if (cs_mask & (1 << 5)) {
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at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
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}
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if (cs_mask & (1 << 6)) {
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at91_set_pio_output(AT91_PIO_PORTD, 0, 1);
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}
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if (cs_mask & (1 << 7)) {
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at91_set_pio_output(AT91_PIO_PORTD, 1, 1);
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}
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}
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void at91_spi1_hw_init(unsigned long cs_mask)
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{
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at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
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at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* SPI1_MISO */
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at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* SPI1_MOSI */
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at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* SPI1_SPCK */
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/* Enable clock */
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writel(1 << AT91CAP9_ID_SPI1, &pmc->pcer);
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if (cs_mask & (1 << 0)) {
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at91_set_a_periph(AT91_PIO_PORTB, 15, 1);
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}
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if (cs_mask & (1 << 1)) {
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at91_set_a_periph(AT91_PIO_PORTB, 16, 1);
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}
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if (cs_mask & (1 << 2)) {
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at91_set_a_periph(AT91_PIO_PORTB, 17, 1);
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}
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if (cs_mask & (1 << 3)) {
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at91_set_a_periph(AT91_PIO_PORTB, 18, 1);
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}
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if (cs_mask & (1 << 4)) {
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at91_set_pio_output(AT91_PIO_PORTB, 15, 1);
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}
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if (cs_mask & (1 << 5)) {
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at91_set_pio_output(AT91_PIO_PORTB, 16, 1);
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}
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if (cs_mask & (1 << 6)) {
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at91_set_pio_output(AT91_PIO_PORTB, 17, 1);
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}
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if (cs_mask & (1 << 7)) {
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at91_set_pio_output(AT91_PIO_PORTB, 18, 1);
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}
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}
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#endif
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#ifdef CONFIG_MACB
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void at91_macb_hw_init(void)
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{
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at91_set_a_periph(AT91_PIO_PORTB, 21, 0); /* ETXCK_EREFCK */
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at91_set_a_periph(AT91_PIO_PORTB, 22, 0); /* ERXDV */
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at91_set_a_periph(AT91_PIO_PORTB, 25, 0); /* ERX0 */
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at91_set_a_periph(AT91_PIO_PORTB, 26, 0); /* ERX1 */
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at91_set_a_periph(AT91_PIO_PORTB, 27, 0); /* ERXER */
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at91_set_a_periph(AT91_PIO_PORTB, 28, 0); /* ETXEN */
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at91_set_a_periph(AT91_PIO_PORTB, 23, 0); /* ETX0 */
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at91_set_a_periph(AT91_PIO_PORTB, 24, 0); /* ETX1 */
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at91_set_a_periph(AT91_PIO_PORTB, 30, 0); /* EMDIO */
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at91_set_a_periph(AT91_PIO_PORTB, 29, 0); /* EMDC */
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#ifndef CONFIG_RMII
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at91_set_b_periph(AT91_PIO_PORTC, 25, 0); /* ECRS */
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at91_set_b_periph(AT91_PIO_PORTC, 26, 0); /* ECOL */
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at91_set_b_periph(AT91_PIO_PORTC, 22, 0); /* ERX2 */
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at91_set_b_periph(AT91_PIO_PORTC, 23, 0); /* ERX3 */
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at91_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ERXCK */
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at91_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ETX2 */
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at91_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ETX3 */
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at91_set_b_periph(AT91_PIO_PORTC, 24, 0); /* ETXER */
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#endif
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}
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#endif
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#ifdef CONFIG_AT91_CAN
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void at91_can_hw_init(void)
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{
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at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
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at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* CAN_TX */
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at91_set_a_periph(AT91_PIO_PORTA, 13, 1); /* CAN_RX */
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/* Enable clock */
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writel(1 << AT91CAP9_ID_CAN, &pmc->pcer);
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}
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#endif
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@ -157,10 +157,8 @@ typedef struct at91_pmc {
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#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
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#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
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#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
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#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [AT91CAP9 revC only] */
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#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
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#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
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#define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */
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#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
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#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
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#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
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@ -175,7 +173,7 @@ typedef struct at91_pmc {
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#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */
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#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
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#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */
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#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x] */
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#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
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#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
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@ -210,7 +208,7 @@ typedef struct at91_pmc {
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#define AT91RM9200_PMC_MDIV_2 (1 << 8)
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#define AT91RM9200_PMC_MDIV_3 (2 << 8)
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#define AT91RM9200_PMC_MDIV_4 (3 << 8)
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#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */
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#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9 only] */
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#define AT91SAM9_PMC_MDIV_2 (1 << 8)
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#define AT91SAM9_PMC_MDIV_4 (2 << 8)
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#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */
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@ -230,8 +228,7 @@ typedef struct at91_pmc {
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#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
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#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
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#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
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#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [AT91CAP9 only] */
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#define AT91_PMC_OSCSEL (1 << 7) /* Slow Clock Oscillator [AT91CAP9 revC only] */
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#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock */
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#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
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#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
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#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
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@ -1,78 +0,0 @@
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/*
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* [origin: Linux kernel include/asm-arm/arch-at91/at91cap9.h]
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*
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* Copyright (C) 2007 Stelian Pop <stelian@popies.net>
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* Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
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* Copyright (C) 2007 Atmel Corporation.
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*
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* Common definitions.
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* Based on AT91CAP9 datasheet revision B (Preliminary).
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef AT91CAP9_H
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#define AT91CAP9_H
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/*
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* Peripheral identifiers/interrupts.
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*/
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#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
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#define AT91_ID_SYS 1 /* System Peripherals */
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#define AT91CAP9_ID_PIOABCD 2 /* Parallel IO Controller A, B, C and D */
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#define AT91CAP9_ID_MPB0 3 /* MP Block Peripheral 0 */
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#define AT91CAP9_ID_MPB1 4 /* MP Block Peripheral 1 */
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#define AT91CAP9_ID_MPB2 5 /* MP Block Peripheral 2 */
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#define AT91CAP9_ID_MPB3 6 /* MP Block Peripheral 3 */
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#define AT91CAP9_ID_MPB4 7 /* MP Block Peripheral 4 */
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#define AT91CAP9_ID_US0 8 /* USART 0 */
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#define AT91CAP9_ID_US1 9 /* USART 1 */
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#define AT91CAP9_ID_US2 10 /* USART 2 */
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#define AT91CAP9_ID_MCI0 11 /* Multimedia Card Interface 0 */
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#define AT91CAP9_ID_MCI1 12 /* Multimedia Card Interface 1 */
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#define AT91CAP9_ID_CAN 13 /* CAN */
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#define AT91CAP9_ID_TWI 14 /* Two-Wire Interface */
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#define AT91CAP9_ID_SPI0 15 /* Serial Peripheral Interface 0 */
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#define AT91CAP9_ID_SPI1 16 /* Serial Peripheral Interface 0 */
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#define AT91CAP9_ID_SSC0 17 /* Serial Synchronous Controller 0 */
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#define AT91CAP9_ID_SSC1 18 /* Serial Synchronous Controller 1 */
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#define AT91CAP9_ID_AC97C 19 /* AC97 Controller */
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#define AT91CAP9_ID_TCB 20 /* Timer Counter 0, 1 and 2 */
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#define AT91CAP9_ID_PWMC 21 /* Pulse Width Modulation Controller */
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#define AT91CAP9_ID_EMAC 22 /* Ethernet */
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#define AT91CAP9_ID_AESTDES 23 /* Advanced Encryption Standard, Triple DES */
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#define AT91CAP9_ID_ADC 24 /* Analog-to-Digital Converter */
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#define AT91CAP9_ID_ISI 25 /* Image Sensor Interface */
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#define AT91CAP9_ID_LCDC 26 /* LCD Controller */
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#define AT91CAP9_ID_DMA 27 /* DMA Controller */
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#define AT91CAP9_ID_UDPHS 28 /* USB High Speed Device Port */
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#define AT91CAP9_ID_UHP 29 /* USB Host Port */
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#define AT91CAP9_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
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#define AT91CAP9_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
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#define AT91_PIO_BASE 0xfffff200
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#define AT91_PMC_BASE 0xfffffc00
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#define AT91_RSTC_BASE 0xfffffd00
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#define AT91_PIT_BASE 0xfffffd30
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/*
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* Internal Memory.
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*/
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#define AT91CAP9_SRAM_BASE 0x00100000 /* Internal SRAM base address */
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#define AT91CAP9_SRAM_SIZE (32 * SZ_1K) /* Internal SRAM size (32Kb) */
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#define AT91CAP9_ROM_BASE 0x00400000 /* Internal ROM base address */
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#define AT91CAP9_ROM_SIZE (32 * SZ_1K) /* Internal ROM size (32Kb) */
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#define AT91CAP9_LCDC_BASE 0x00500000 /* LCD Controller */
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#define AT91CAP9_UDPHS_BASE 0x00600000 /* USB High Speed Device Port */
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#define AT91CAP9_UHP_BASE 0x00700000 /* USB Host controller */
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#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6
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/*
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* Cpu Name
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*/
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#define CONFIG_SYS_AT91_CPU_NAME "AT91CAP9"
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#endif
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@ -1,129 +0,0 @@
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/*
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* [origin: Linux kernel include/asm-arm/arch-at91/at91cap9_matrix.h]
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*
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* Copyright (C) 2007 Stelian Pop <stelian@popies.net>
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* Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
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* Copyright (C) 2006 Atmel Corporation.
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*
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* Memory Controllers (MATRIX, EBI) - System peripherals registers.
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* Based on AT91CAP9 datasheet revision B (Preliminary).
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef AT91CAP9_MATRIX_H
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#define AT91CAP9_MATRIX_H
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#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
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#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
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#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
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#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
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#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
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#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
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#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */
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#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */
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#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */
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#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */
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||||
#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */
|
||||
#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */
|
||||
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
|
||||
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
|
||||
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
|
||||
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
|
||||
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
|
||||
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
|
||||
|
||||
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
|
||||
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
|
||||
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
|
||||
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
|
||||
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
|
||||
#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
|
||||
#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */
|
||||
#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */
|
||||
#define AT91_MATRIX_SCFG8 (AT91_MATRIX + 0x60) /* Slave Configuration Register 8 */
|
||||
#define AT91_MATRIX_SCFG9 (AT91_MATRIX + 0x64) /* Slave Configuration Register 9 */
|
||||
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
|
||||
#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
|
||||
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
|
||||
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
|
||||
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
|
||||
|
||||
#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
|
||||
#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */
|
||||
#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
|
||||
#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */
|
||||
#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
|
||||
#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */
|
||||
#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
|
||||
#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */
|
||||
#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
|
||||
#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */
|
||||
#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
|
||||
#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */
|
||||
#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */
|
||||
#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */
|
||||
#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */
|
||||
#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */
|
||||
#define AT91_MATRIX_PRAS8 (AT91_MATRIX + 0xC0) /* Priority Register A for Slave 8 */
|
||||
#define AT91_MATRIX_PRBS8 (AT91_MATRIX + 0xC4) /* Priority Register B for Slave 8 */
|
||||
#define AT91_MATRIX_PRAS9 (AT91_MATRIX + 0xC8) /* Priority Register A for Slave 9 */
|
||||
#define AT91_MATRIX_PRBS9 (AT91_MATRIX + 0xCC) /* Priority Register B for Slave 9 */
|
||||
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
|
||||
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
|
||||
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
|
||||
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
|
||||
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
|
||||
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
|
||||
#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
|
||||
#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
|
||||
#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
|
||||
#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */
|
||||
#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
|
||||
#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
|
||||
|
||||
#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
|
||||
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
|
||||
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
|
||||
#define AT91_MATRIX_RCB2 (1 << 2)
|
||||
#define AT91_MATRIX_RCB3 (1 << 3)
|
||||
#define AT91_MATRIX_RCB4 (1 << 4)
|
||||
#define AT91_MATRIX_RCB5 (1 << 5)
|
||||
#define AT91_MATRIX_RCB6 (1 << 6)
|
||||
#define AT91_MATRIX_RCB7 (1 << 7)
|
||||
#define AT91_MATRIX_RCB8 (1 << 8)
|
||||
#define AT91_MATRIX_RCB9 (1 << 9)
|
||||
#define AT91_MATRIX_RCB10 (1 << 10)
|
||||
#define AT91_MATRIX_RCB11 (1 << 11)
|
||||
|
||||
#define AT91_MPBS0_SFR (AT91_MATRIX + 0x114) /* MPBlock Slave 0 Special Function Register */
|
||||
#define AT91_MPBS1_SFR (AT91_MATRIX + 0x11C) /* MPBlock Slave 1 Special Function Register */
|
||||
|
||||
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */
|
||||
#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||
#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
|
||||
#define AT91_MATRIX_EBI_CS1A_BCRAMC (1 << 1)
|
||||
#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
|
||||
#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
|
||||
#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
|
||||
#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */
|
||||
#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4)
|
||||
#define AT91_MATRIX_EBI_CS4A_SMC_CF1 (1 << 4)
|
||||
#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */
|
||||
#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5)
|
||||
#define AT91_MATRIX_EBI_CS5A_SMC_CF2 (1 << 5)
|
||||
#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||
#define AT91_MATRIX_EBI_DQSPDC (1 << 9) /* Data Qualifier Strobe Pull-Down Configuration */
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
|
||||
|
||||
#define AT91_MPBS2_SFR (AT91_MATRIX + 0x12C) /* MPBlock Slave 2 Special Function Register */
|
||||
#define AT91_MPBS3_SFR (AT91_MATRIX + 0x130) /* MPBlock Slave 3 Special Function Register */
|
||||
#define AT91_APB_SFR (AT91_MATRIX + 0x134) /* APB Bridge Special Function Register */
|
||||
|
||||
#endif
|
||||
|
|
@ -15,8 +15,6 @@
|
|||
#include <asm/arch/at91sam9263_matrix.h>
|
||||
#elif defined(CONFIG_AT91SAM9RL)
|
||||
#include <asm/arch/at91sam9rl_matrix.h>
|
||||
#elif defined(CONFIG_AT91CAP9)
|
||||
#include <asm/arch/at91cap9_matrix.h>
|
||||
#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
|
||||
#include <asm/arch/at91sam9g45_matrix.h>
|
||||
#elif defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
|
||||
|
|
|
|||
|
|
@ -23,8 +23,6 @@
|
|||
# include <asm/arch/at91sam9g45.h>
|
||||
#elif defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
|
||||
# include <asm/arch/at91sam9x5.h>
|
||||
#elif defined(CONFIG_AT91CAP9)
|
||||
# include <asm/arch/at91cap9.h>
|
||||
#elif defined(CONFIG_SAMA5D3)
|
||||
# include <asm/arch/sama5d3.h>
|
||||
#elif defined(CONFIG_SAMA5D4)
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@
|
|||
#define ATMEL_LCDC_GUARD_TIME 1
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91CAP9)
|
||||
#if defined(CONFIG_AT91SAM9263)
|
||||
#define ATMEL_LCDC_FIFO_SIZE 2048
|
||||
#else
|
||||
#define ATMEL_LCDC_FIFO_SIZE 512
|
||||
|
|
|
|||
Loading…
Reference in a new issue