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ARM: cache_v7: Various minor cleanups
Remove two gratuituous blank lines, uses u32 (instead of int) as the type for values that will be written to a register, moves the beginning of the variable declaration section to a separate line (rather than the one with the opening brace) and keeps the function signature on a single line where possible. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
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1 changed files with 7 additions and 7 deletions
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@ -21,7 +21,8 @@
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* to get size details from Current Cache Size ID Register(CCSIDR)
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*/
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static void set_csselr(u32 level, u32 type)
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{ u32 csselr = level << 1 | type;
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{
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u32 csselr = level << 1 | type;
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/* Write to Cache Size Selection Register(CSSELR) */
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asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr));
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@ -49,7 +50,8 @@ static void v7_inval_dcache_level_setway(u32 level, u32 num_sets,
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u32 num_ways, u32 way_shift,
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u32 log2_line_len)
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{
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int way, set, setway;
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int way, set;
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u32 setway;
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/*
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* For optimal assembly code:
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@ -73,7 +75,8 @@ static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
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u32 num_ways, u32 way_shift,
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u32 log2_line_len)
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{
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int way, set, setway;
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int way, set;
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u32 setway;
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/*
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* For optimal assembly code:
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@ -134,7 +137,6 @@ static void v7_maint_dcache_level_setway(u32 level, u32 operation)
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static void v7_maint_dcache_all(u32 operation)
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{
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u32 level, cache_type, level_start_bit = 0;
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u32 clidr = get_clidr();
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for (level = 0; level < 7; level++) {
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@ -147,8 +149,7 @@ static void v7_maint_dcache_all(u32 operation)
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}
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}
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static void v7_dcache_clean_inval_range(u32 start,
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u32 stop, u32 line_len)
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static void v7_dcache_clean_inval_range(u32 start, u32 stop, u32 line_len)
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{
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u32 mva;
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@ -256,7 +257,6 @@ void flush_dcache_all(void)
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*/
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void invalidate_dcache_range(unsigned long start, unsigned long stop)
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{
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v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE);
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v7_outer_cache_inval_range(start, stop);
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