arc: select cache settings via menuconfig

This change allows to keep board description clean and minimalistic.
This is especially helpful if one board may house different CPUs with
different features.

It is applicable to both FPGA-based boards or those that have CPUs
mounted on interchnagable daughter-boards.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
This commit is contained in:
Alexey Brodkin 2015-02-03 13:58:13 +03:00
parent 5ff40f3d42
commit 205e7a7b77
9 changed files with 30 additions and 17 deletions

View file

@ -47,6 +47,25 @@ config ARC_MMU_V3
endchoice
config SYS_ICACHE_OFF
bool "Do not use Instruction Cache"
default n
config SYS_DCACHE_OFF
bool "Do not use Data Cache"
default n
config ARC_CACHE_LINE_SHIFT
int "Cache Line Length (as power of 2)"
range 5 7
default "6"
depends on !SYS_DCACHE_OFF || !SYS_DCACHE_OFF
help
Starting with ARC700 4.9, Cache line length is configurable,
This option specifies "N", with Line-len = 2 power N
So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
Linux only supports same line lengths for I and D caches.
choice
prompt "Target select"

View file

@ -9,15 +9,12 @@
#include <config.h>
/*
* The current upper bound for ARC L1 data cache line sizes is 128 bytes.
* We use that value for aligning DMA buffers unless the board config has
* specified an alternate cache line size.
*/
#ifdef CONFIG_SYS_CACHELINE_SIZE
#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
#ifdef CONFIG_ARC_CACHE_LINE_SHIFT
#define CONFIG_SYS_CACHELINE_SIZE (1 << CONFIG_ARC_CACHE_LINE_SHIFT)
#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
#else
#define ARCH_DMA_MINALIGN 128
/* Satisfy users of ARCH_DMA_MINALIGN */
#define ARCH_DMA_MINALIGN 128
#endif
#if defined(CONFIG_ARC_MMU_V2)

View file

@ -6,6 +6,7 @@
#include <config.h>
#include <asm/arcregs.h>
#include <asm/cache.h>
/* Bit values in IC_CTRL */
#define IC_CTRL_CACHE_DISABLE (1 << 0)

View file

@ -1,3 +1,5 @@
CONFIG_ARC=y
CONFIG_TARGET_AXS101=y
CONFIG_SYS_CLK_FREQ=750000000
CONFIG_SYS_CLK_FREQ=750000000
CONFIG_ARC_CACHE_LINE_SHIFT=5
CONFIG_SYS_DCACHE_OFF=y

View file

@ -1,3 +1,4 @@
CONFIG_ARC=y
CONFIG_TARGET_TB100=y
CONFIG_SYS_CLK_FREQ=500000000
CONFIG_SYS_CLK_FREQ=500000000
CONFIG_ARC_CACHE_LINE_SHIFT=5

View file

@ -11,7 +11,6 @@
* CPU configuration
*/
#define CONFIG_SYS_BIG_ENDIAN
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
/*

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@ -10,7 +10,6 @@
/*
* CPU configuration
*/
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
/*

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@ -10,12 +10,8 @@
/*
* CPU configuration
*/
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
/* NAND controller DMA doesn't work correctly with D$ enabled */
#define CONFIG_SYS_DCACHE_OFF
/*
* Board configuration
*/

View file

@ -12,7 +12,6 @@
/*
* CPU configuration
*/
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
/*