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Merge branch 'master' of git://www.denx.de/git/u-boot-imx

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This commit is contained in:
Tom Rini 2014-12-10 09:07:25 -05:00
commit 9b416a9f4c
20 changed files with 66 additions and 45 deletions
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1
arch/arm/Kconfig
View file

@ -654,6 +654,7 @@ config TARGET_KOSAGI_NOVENA
config TARGET_TBS2910
bool "Support tbs2910"
select CPU_V7
config TARGET_TQMA6
bool "TQ Systems TQMa6 board"

2
arch/arm/cpu/armv7/mx6/clock.c
View file

@ -443,7 +443,7 @@ int enable_fec_anatop_clock(enum enet_freq freq)
struct anatop_regs __iomem *anatop =
(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
if (freq < ENET_25MHz || freq > ENET_125MHz)
if (freq < ENET_25MHZ || freq > ENET_125MHZ)
return -EINVAL;
reg = readl(&anatop->pll_enet);

21
arch/arm/cpu/armv7/vf610/generic.c
View file

@ -265,20 +265,21 @@ static char *get_reset_cause(void)
cause = readl(&src_regs->srsr);
writel(cause, &src_regs->srsr);
cause &= 0xff;
switch (cause) {
case 0x08:
return "WDOG";
case 0x20:
if (cause & SRC_SRSR_POR_RST)
return "POWER ON RESET";
else if (cause & SRC_SRSR_WDOG_A5)
return "WDOG A5";
else if (cause & SRC_SRSR_WDOG_M4)
return "WDOG M4";
else if (cause & SRC_SRSR_JTAG_RST)
return "JTAG HIGH-Z";
case 0x80:
else if (cause & SRC_SRSR_SW_RST)
return "SW RESET";
else if (cause & SRC_SRSR_RESETB)
return "EXTERNAL RESET";
case 0xfd:
return "POR";
default:
else
return "unknown reset";
}
}
int print_cpuinfo(void)

3
arch/arm/imx-common/cpu.c
View file

@ -206,6 +206,9 @@ void arch_preboot_os(void)
{
#if defined(CONFIG_CMD_SATA)
sata_stop();
#if defined(CONFIG_MX6)
disable_sata_clock();
#endif
#endif
#if defined(CONFIG_VIDEO_IPUV3)
/* disable video before launching O/S */

8
arch/arm/include/asm/arch-mx6/clock.h
View file

@ -43,10 +43,10 @@ enum mxc_clock {
};
enum enet_freq {
ENET_25MHz,
ENET_50MHz,
ENET_100MHz,
ENET_125MHz,
ENET_25MHZ,
ENET_50MHZ,
ENET_100MHZ,
ENET_125MHZ,
};
u32 imx_get_uartclk(void);

8
arch/arm/include/asm/arch-vf610/imx-regs.h
View file

@ -256,6 +256,14 @@
#define DDRMC_CR161_TODTH_RD(v) (((v) & 0xf) << 8)
#define DDRMC_CR161_TODTH_WR(v) ((v) & 0xf)
/* System Reset Controller (SRC) */
#define SRC_SRSR_SW_RST (0x1 << 18)
#define SRC_SRSR_RESETB (0x1 << 7)
#define SRC_SRSR_JTAG_RST (0x1 << 5)
#define SRC_SRSR_WDOG_M4 (0x1 << 4)
#define SRC_SRSR_WDOG_A5 (0x1 << 3)
#define SRC_SRSR_POR_RST (0x1 << 0)
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>

2
board/aristainetos/aristainetos.c
View file

@ -301,7 +301,7 @@ int board_eth_init(bd_t *bis)
/* clear gpr1[14], gpr1[18:17] to select anatop clock */
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
ret = enable_fec_anatop_clock(ENET_50MHz);
ret = enable_fec_anatop_clock(ENET_50MHZ);
if (ret)
return ret;

2
board/freescale/mx6slevk/mx6slevk.c
View file

@ -234,7 +234,7 @@ static int setup_fec(void)
/* clear gpr1[14], gpr1[18:17] to select anatop clock */
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
return enable_fec_anatop_clock(ENET_50MHz);
return enable_fec_anatop_clock(ENET_50MHZ);
}
#endif

2
board/freescale/mx6sxsabresd/mx6sxsabresd.c
View file

@ -168,7 +168,7 @@ static int setup_fec(void)
reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
writel(reg, &anatop->pll_enet);
return enable_fec_anatop_clock(ENET_125MHz);
return enable_fec_anatop_clock(ENET_125MHZ);
}
int board_eth_init(bd_t *bis)

2
board/solidrun/hummingboard/hummingboard.c
View file

@ -146,7 +146,7 @@ int board_eth_init(bd_t *bis)
{
struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
int ret = enable_fec_anatop_clock(ENET_25MHz);
int ret = enable_fec_anatop_clock(ENET_25MHZ);
if (ret)
return ret;

8
board/tbs/tbs2910/Kconfig
View file

@ -1,23 +1,15 @@
if TARGET_TBS2910
config SYS_CPU
string
default "armv7"
config SYS_BOARD
string
default "tbs2910"
config SYS_VENDOR
string
default "tbs"
config SYS_SOC
string
default "mx6"
config SYS_CONFIG_NAME
string
default "tbs2910"
endif

14
drivers/block/dwc_ahsata.c
View file

@ -594,22 +594,24 @@ int init_sata(int dev)
int reset_sata(int dev)
{
struct ahci_probe_ent *probe_ent =
(struct ahci_probe_ent *)sata_dev_desc[dev].priv;
struct sata_host_regs *host_mmio =
(struct sata_host_regs *)probe_ent->mmio_base;
struct ahci_probe_ent *probe_ent;
struct sata_host_regs *host_mmio;
if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
printf("The sata index %d is out of ranges\n\r", dev);
return -1;
}
probe_ent = (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
if (NULL == probe_ent)
/* not initialized, so nothing to reset */
return 0;
host_mmio = (struct sata_host_regs *)probe_ent->mmio_base;
setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR);
while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR)
udelay(100);
disable_sata_clock();
return 0;
}

2
drivers/misc/mxc_ocotp.c
View file

@ -81,8 +81,6 @@ static int finish_access(struct ocotp_regs *regs, const char *caller)
err = !!(readl(&regs->ctrl) & BM_CTRL_ERROR);
clear_error(regs);
enable_ocotp_clk(0);
if (err) {
printf("mxc_ocotp %s(): Access protect error\n", caller);
return -EIO;

14
drivers/misc/mxs_ocotp.c
View file

@ -187,6 +187,8 @@ static int mxs_ocotp_write_fuse(uint32_t addr, uint32_t mask)
uint32_t hclk_val, vddio_val;
int ret;
mxs_ocotp_clear_error();
/* Make sure the banks are closed for reading. */
ret = mxs_ocotp_read_bank_open(0);
if (ret) {
@ -221,13 +223,17 @@ static int mxs_ocotp_write_fuse(uint32_t addr, uint32_t mask)
goto fail;
}
/* Check for errors */
if (readl(&ocotp_regs->hw_ocotp_ctrl) & OCOTP_CTRL_ERROR) {
puts("Failed writing fuses!\n");
ret = -EPERM;
goto fail;
}
fail:
mxs_ocotp_scale_vddio(0, &vddio_val);
ret = mxs_ocotp_scale_hclk(0, &hclk_val);
if (ret) {
if (mxs_ocotp_scale_hclk(0, &hclk_val))
puts("Failed scaling up the HCLK!\n");
return ret;
}
return ret;
}

2
drivers/thermal/imx_thermal.c
View file

@ -156,8 +156,6 @@ static int imx_thermal_probe(struct udevice *dev)
if (fuse == 0 || fuse == ~0) {
printf("CPU: Thermal invalid data, fuse: 0x%x\n", fuse);
return -EPERM;
} else {
printf("CPU: Thermal calibration data: 0x%x\n", fuse);
}
*priv = fuse;

4
include/config_fallbacks.h
View file

@ -79,6 +79,10 @@
#define CONFIG_SYS_PROMPT "=> "
#endif
#ifndef CONFIG_SYS_PBSIZE
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + 128)
#endif
#ifndef CONFIG_FIT_SIGNATURE
#define CONFIG_IMAGE_FORMAT_LEGACY
#endif

1
include/configs/mx53loco.h
View file

@ -94,6 +94,7 @@
/* Command definition */
#include <config_cmd_default.h>
#define CONFIG_CMD_BOOTZ
#define CONFIG_SUPPORT_RAW_INITRD
#undef CONFIG_CMD_IMLS

3
include/configs/mx6sabre_common.h
View file

@ -220,9 +220,6 @@
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE 256
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE

10
include/configs/mx6sxsabresd.h
View file

@ -208,6 +208,16 @@
#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1)
#endif
#define CONFIG_DM
#define CONFIG_DM_THERMAL
#define CONFIG_SYS_MALLOC_F_LEN (1 << 10)
#define CONFIG_IMX6_THERMAL
#define CONFIG_CMD_FUSE
#if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL)
#define CONFIG_MXC_OCOTP
#endif
/* FLASH and environment organization */
#define CONFIG_SYS_NO_FLASH

2
include/configs/tbs2910.h
View file

@ -167,7 +167,7 @@
#define CONFIG_USB_STORAGE
#define CONFIG_USB_KEYBOARD
#ifdef CONFIG_USB_KEYBOARD
#define CONFIG_SYS_USB_EVENT_POLL
#define CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
#define CONFIG_SYS_STDIO_DEREGISTER
#define CONFIG_PREBOOT "if hdmidet; then usb start; fi"
#endif /* CONFIG_USB_KEYBOARD */