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ARM: UniPhier: enable STDMAC for EHCI
Deassert the reset signal and provide the clock for STDMAC core. This is necessary for the USB 2.0 host controllers. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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parent
d3384bf77e
commit
42ca6982ff
3 changed files with 10 additions and 2 deletions
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@ -39,6 +39,7 @@
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#define SC_RSTCTRL (SC_BASE_ADDR | 0x2000)
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#define SC_RSTCTRL_NRST_ETHER (0x1 << 12)
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#define SC_RSTCTRL_NRST_STDMAC (0x1 << 10)
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#define SC_RSTCTRL_NRST_UMC1 (0x1 << 5)
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#define SC_RSTCTRL_NRST_UMC0 (0x1 << 4)
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#define SC_RSTCTRL_NRST_NAND (0x1 << 2)
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@ -49,6 +50,7 @@
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#define SC_CLKCTRL (SC_BASE_ADDR | 0x2104)
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#define SC_CLKCTRL_CEN_ETHER (0x1 << 12)
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#define SC_CLKCTRL_CEN_MIO (0x1 << 11)
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#define SC_CLKCTRL_CEN_STDMAC (0x1 << 10)
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#define SC_CLKCTRL_CEN_UMC (0x1 << 4)
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#define SC_CLKCTRL_CEN_NAND (0x1 << 2)
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#define SC_CLKCTRL_CEN_SBC (0x1 << 1)
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@ -17,6 +17,9 @@ void clkrst_init(void)
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#ifdef CONFIG_UNIPHIER_ETH
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tmp |= SC_RSTCTRL_NRST_ETHER;
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#endif
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#ifdef CONFIG_USB_EHCI_UNIPHIER
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tmp |= SC_RSTCTRL_NRST_STDMAC;
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#endif
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#ifdef CONFIG_NAND_DENALI
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tmp |= SC_RSTCTRL_NRST_NAND;
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#endif
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@ -29,7 +32,7 @@ void clkrst_init(void)
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tmp |= SC_CLKCTRL_CEN_ETHER;
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#endif
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#ifdef CONFIG_USB_EHCI_UNIPHIER
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tmp |= SC_CLKCTRL_CEN_MIO;
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tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC;
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#endif
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#ifdef CONFIG_NAND_DENALI
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tmp |= SC_CLKCTRL_CEN_NAND;
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@ -17,6 +17,9 @@ void clkrst_init(void)
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#ifdef CONFIG_UNIPHIER_ETH
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tmp |= SC_RSTCTRL_NRST_ETHER;
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#endif
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#ifdef CONFIG_USB_EHCI_UNIPHIER
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tmp |= SC_RSTCTRL_NRST_STDMAC;
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#endif
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#ifdef CONFIG_NAND_DENALI
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tmp |= SC_RSTCTRL_NRST_NAND;
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#endif
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@ -29,7 +32,7 @@ void clkrst_init(void)
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tmp |= SC_CLKCTRL_CEN_ETHER;
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#endif
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#ifdef CONFIG_USB_EHCI_UNIPHIER
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tmp |= SC_CLKCTRL_CEN_MIO;
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tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC;
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#endif
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#ifdef CONFIG_NAND_DENALI
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tmp |= SC_CLKCTRL_CEN_NAND;
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