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imx:mx6sx add dram io configure for mx6sx
Define two structure mx6sx_iomux_ddr_regs and mx6sx_iomux_grp_regs. Add a new function mx6sx_dram_iocfg to configure dram io. Since mx6sx only have one channel mmdc0, define a new empty macro MMDC1 to replace mmdc1->entry=value for mx6sx. And to other mx6 soc, MMDC1 effects as "mmdc1->entry=value". Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
This commit is contained in:
Peng Fan
Stefano Babic
parent
71abf19b0f
commit
d9efd47c03
2 changed files with 128 additions and 14 deletions
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@ -12,6 +12,65 @@
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#include <asm/io.h>
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#include <asm/types.h>
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#if defined(CONFIG_MX6SX)
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/* Configure MX6SX mmdc iomux */
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void mx6sx_dram_iocfg(unsigned width,
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const struct mx6sx_iomux_ddr_regs *ddr,
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const struct mx6sx_iomux_grp_regs *grp)
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{
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struct mx6sx_iomux_ddr_regs *mx6_ddr_iomux;
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struct mx6sx_iomux_grp_regs *mx6_grp_iomux;
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mx6_ddr_iomux = (struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
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mx6_grp_iomux = (struct mx6sx_iomux_grp_regs *)MX6SX_IOM_GRP_BASE;
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/* DDR IO TYPE */
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writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
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writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
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/* CLOCK */
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writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
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/* ADDRESS */
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writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
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writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
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writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
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/* Control */
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writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
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writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
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writel(ddr->dram_sdcke0, &mx6_ddr_iomux->dram_sdcke0);
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writel(ddr->dram_sdcke1, &mx6_ddr_iomux->dram_sdcke1);
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writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
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writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
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writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
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/* Data Strobes */
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writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
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writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
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writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
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if (width >= 32) {
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writel(ddr->dram_sdqs2, &mx6_ddr_iomux->dram_sdqs2);
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writel(ddr->dram_sdqs3, &mx6_ddr_iomux->dram_sdqs3);
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}
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/* Data */
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writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
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writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
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writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
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if (width >= 32) {
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writel(grp->grp_b2ds, &mx6_grp_iomux->grp_b2ds);
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writel(grp->grp_b3ds, &mx6_grp_iomux->grp_b3ds);
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}
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writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
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writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
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if (width >= 32) {
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writel(ddr->dram_dqm2, &mx6_ddr_iomux->dram_dqm2);
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writel(ddr->dram_dqm3, &mx6_ddr_iomux->dram_dqm3);
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}
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}
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#endif
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#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
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/* Configure MX6DQ mmdc iomux */
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void mx6dq_dram_iocfg(unsigned width,
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@ -184,12 +243,19 @@ void mx6sdl_dram_iocfg(unsigned width,
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*/
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#define MR(val, ba, cmd, cs1) \
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((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
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#ifdef CONFIG_MX6SX
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#define MMDC1(entry, value) do {} while (0)
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#else
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#define MMDC1(entry, value) do { mmdc1->entry = value; } while (0)
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#endif
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void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
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const struct mx6_mmdc_calibration *calib,
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const struct mx6_ddr3_cfg *ddr3_cfg)
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{
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volatile struct mmdc_p_regs *mmdc0;
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#ifndef CONFIG_MX6SX
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volatile struct mmdc_p_regs *mmdc1;
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#endif
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u32 val;
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u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
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u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
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@ -203,7 +269,9 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
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int cs;
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mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
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#ifndef CONFIG_MX6SX
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mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
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#endif
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/* MX6D/MX6Q: 1066 MHz memory clock, clkper = 1.894ns = 1894ps */
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if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
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@ -362,12 +430,12 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
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mmdc0->mprddlctl = calib->p0_mprddlctl;
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mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
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if (sysinfo->dsize > 1) {
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mmdc1->mpwldectrl0 = calib->p1_mpwldectrl0;
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mmdc1->mpwldectrl1 = calib->p1_mpwldectrl1;
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mmdc1->mpdgctrl0 = calib->p1_mpdgctrl0;
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mmdc1->mpdgctrl1 = calib->p1_mpdgctrl1;
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mmdc1->mprddlctl = calib->p1_mprddlctl;
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mmdc1->mpwrdlctl = calib->p1_mpwrdlctl;
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MMDC1(mpwldectrl0, calib->p1_mpwldectrl0);
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MMDC1(mpwldectrl1, calib->p1_mpwldectrl1);
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MMDC1(mpdgctrl0, calib->p1_mpdgctrl0);
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MMDC1(mpdgctrl1, calib->p1_mpdgctrl1);
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MMDC1(mprddlctl, calib->p1_mprddlctl);
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MMDC1(mpwrdlctl, calib->p1_mpwrdlctl);
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}
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/* Read data DQ Byte0-3 delay */
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@ -379,23 +447,23 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
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}
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if (sysinfo->dsize > 1) {
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mmdc1->mprddqby0dl = 0x33333333;
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mmdc1->mprddqby1dl = 0x33333333;
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mmdc1->mprddqby2dl = 0x33333333;
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mmdc1->mprddqby3dl = 0x33333333;
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MMDC1(mprddqby0dl, 0x33333333);
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MMDC1(mprddqby1dl, 0x33333333);
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MMDC1(mprddqby2dl, 0x33333333);
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MMDC1(mprddqby3dl, 0x33333333);
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}
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/* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */
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val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227;
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mmdc0->mpodtctrl = val;
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if (sysinfo->dsize > 1)
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mmdc1->mpodtctrl = val;
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MMDC1(mpodtctrl, val);
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/* complete calibration */
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val = (1 << 11); /* Force measurement on delay-lines */
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mmdc0->mpmur0 = val;
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if (sysinfo->dsize > 1)
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mmdc1->mpmur0 = val;
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MMDC1(mpmur0, val);
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/* Step 1: configuration request */
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mmdc0->mdscr = (u32)(1 << 15); /* config request */
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@ -435,7 +503,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
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val = 0xa1390001; /* one-time HW ZQ calib */
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mmdc0->mpzqhwctrl = val;
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if (sysinfo->dsize > 1)
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mmdc1->mpzqhwctrl = val;
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MMDC1(mpzqhwctrl, val);
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/* Step 7: Enable MMDC with desired chip select */
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mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
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@ -477,7 +545,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
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val = 0xa1390003;
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mmdc0->mpzqhwctrl = val;
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if (sysinfo->dsize > 1)
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mmdc1->mpzqhwctrl = val;
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MMDC1(mpzqhwctrl, val);
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/* Step 12: Configure and activate periodic refresh */
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mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */
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@ -62,6 +62,49 @@ struct mmdc_p_regs {
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u32 mpmur0;
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};
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#define MX6SX_IOM_DDR_BASE 0x020e0200
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struct mx6sx_iomux_ddr_regs {
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u32 res1[59];
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u32 dram_dqm0;
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u32 dram_dqm1;
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u32 dram_dqm2;
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u32 dram_dqm3;
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u32 dram_ras;
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u32 dram_cas;
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u32 res2[2];
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u32 dram_sdwe_b;
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u32 dram_odt0;
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u32 dram_odt1;
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u32 dram_sdba0;
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u32 dram_sdba1;
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u32 dram_sdba2;
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u32 dram_sdcke0;
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u32 dram_sdcke1;
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u32 dram_sdclk_0;
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u32 dram_sdqs0;
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u32 dram_sdqs1;
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u32 dram_sdqs2;
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u32 dram_sdqs3;
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u32 dram_reset;
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};
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#define MX6SX_IOM_GRP_BASE 0x020e0500
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struct mx6sx_iomux_grp_regs {
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u32 res1[61];
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u32 grp_addds;
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u32 grp_ddrmode_ctl;
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u32 grp_ddrpke;
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u32 grp_ddrpk;
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u32 grp_ddrhys;
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u32 grp_ddrmode;
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u32 grp_b0ds;
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u32 grp_b1ds;
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u32 grp_ctlds;
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u32 grp_ddr_type;
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u32 grp_b2ds;
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u32 grp_b3ds;
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};
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/*
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* MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL)
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*/
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@ -243,6 +286,9 @@ void mx6dq_dram_iocfg(unsigned width,
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void mx6sdl_dram_iocfg(unsigned width,
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const struct mx6sdl_iomux_ddr_regs *,
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const struct mx6sdl_iomux_grp_regs *);
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void mx6sx_dram_iocfg(unsigned width,
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const struct mx6sx_iomux_ddr_regs *,
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const struct mx6sx_iomux_grp_regs *);
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/* configure mx6 mmdc registers */
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void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,
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