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Merge branch 'rmobile' of git://git.denx.de/u-boot-sh

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This commit is contained in:
Tom Rini 2014-12-10 09:07:06 -05:00
commit d51aae6423
21 changed files with 391 additions and 103 deletions
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14
arch/arm/include/asm/arch-rmobile/mmc.h Normal file
View file

@ -0,0 +1,14 @@
/*
* Renesas SuperH MMCIF driver.
*
* Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* Copyright (C) 2014 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef _RMOBILE_MMC_H_
#define _RMOBILE_MMC_H_
int mmcif_mmc_init(void);
#endif /* _RMOBILE_MMC_H_ */

13
arch/arm/include/asm/arch-rmobile/r8a7790.h
View file

@ -15,6 +15,19 @@
#define CONFIG_SYS_I2C_SH_BASE2 0xE6520000
#define CONFIG_SYS_I2C_SH_BASE3 0xE60B0000
/* Module stop control/status register bits */
#define MSTP0_BITS 0x00640801
#define MSTP1_BITS 0xDB6E9BDF
#define MSTP2_BITS 0x300DA1FC
#define MSTP3_BITS 0xF08CF831
#define MSTP4_BITS 0x80000184
#define MSTP5_BITS 0x44C00046
#define MSTP7_BITS 0x07F30718
#define MSTP8_BITS 0x01F0FF84
#define MSTP9_BITS 0xF5979FCF
#define MSTP10_BITS 0xFFFEFFE0
#define MSTP11_BITS 0x00000000
#define R8A7790_CUT_ES2X 2
#define IS_R8A7790_ES2() \
(rmobile_get_cpu_rev_integer() == R8A7790_CUT_ES2X)

13
arch/arm/include/asm/arch-rmobile/r8a7791.h
View file

@ -51,6 +51,19 @@
#define DBSC3_1_QOS_W15_BASE 0xE67A2F00
#define DBSC3_1_DBADJ2 0xE67A00C8
/* Module stop control/status register bits */
#define MSTP0_BITS 0x00640801
#define MSTP1_BITS 0x9B6C9B5A
#define MSTP2_BITS 0x100D21FC
#define MSTP3_BITS 0xF08CD810
#define MSTP4_BITS 0x800001C4
#define MSTP5_BITS 0x44C00046
#define MSTP7_BITS 0x05BFE618
#define MSTP8_BITS 0x40C0FE85
#define MSTP9_BITS 0xFF979FFF
#define MSTP10_BITS 0xFFFEFFE0
#define MSTP11_BITS 0x000001C0
#define R8A7791_CUT_ES2X 2
#define IS_R8A7791_ES2() \
(rmobile_get_cpu_rev_integer() == R8A7791_CUT_ES2X)

14
arch/arm/include/asm/arch-rmobile/r8a7793.h
View file

@ -56,6 +56,20 @@
/*
* R8A7793 I/O Product Information
*/
/* Module stop control/status register bits */
#define MSTP0_BITS 0x00640801
#define MSTP1_BITS 0x9B6C9B5A
#define MSTP2_BITS 0x100D21FC
#define MSTP3_BITS 0xF08CD810
#define MSTP4_BITS 0x800001C4
#define MSTP5_BITS 0x44C00046
#define MSTP7_BITS 0x05BFE618
#define MSTP8_BITS 0x40C0FE85
#define MSTP9_BITS 0xFF979FFF
#define MSTP10_BITS 0xFFFEFFE0
#define MSTP11_BITS 0x000001C0
#define R8A7793_CUT_ES2X 2
#define IS_R8A7793_ES2() \
(rmobile_get_cpu_rev_integer() == R8A7793_CUT_ES2X)

13
arch/arm/include/asm/arch-rmobile/r8a7794.h
View file

@ -14,4 +14,17 @@
/* SH-I2C */
#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000
/* Module stop control/status register bits */
#define MSTP0_BITS 0x00440801
#define MSTP1_BITS 0x936899DA
#define MSTP2_BITS 0x100D21FC
#define MSTP3_BITS 0xE084D810
#define MSTP4_BITS 0x800001C4
#define MSTP5_BITS 0x40C00044
#define MSTP7_BITS 0x013FE618
#define MSTP8_BITS 0x40803C05
#define MSTP9_BITS 0xFB879FEE
#define MSTP10_BITS 0xFFFEFFE0
#define MSTP11_BITS 0x000001C0
#endif /* __ASM_ARCH_R8A7794_H */

39
arch/arm/include/asm/arch-rmobile/rcar-base.h
View file

@ -29,6 +29,45 @@
#define SCIF4_BASE 0xE6EE0000
#define SCIF5_BASE 0xE6EE8000
/* Module stop status register */
#define MSTPSR0 0xE6150030
#define MSTPSR1 0xE6150038
#define MSTPSR2 0xE6150040
#define MSTPSR3 0xE6150048
#define MSTPSR4 0xE615004C
#define MSTPSR5 0xE615003C
#define MSTPSR7 0xE61501C4
#define MSTPSR8 0xE61509A0
#define MSTPSR9 0xE61509A4
#define MSTPSR10 0xE61509A8
#define MSTPSR11 0xE61509AC
/* Realtime module stop control register */
#define RMSTPCR0 0xE6150110
#define RMSTPCR1 0xE6150114
#define RMSTPCR2 0xE6150118
#define RMSTPCR3 0xE615011C
#define RMSTPCR4 0xE6150120
#define RMSTPCR5 0xE6150124
#define RMSTPCR7 0xE615012C
#define RMSTPCR8 0xE6150980
#define RMSTPCR9 0xE6150984
#define RMSTPCR10 0xE6150988
#define RMSTPCR11 0xE615098C
/* System module stop control register */
#define SMSTPCR0 0xE6150130
#define SMSTPCR1 0xE6150134
#define SMSTPCR2 0xE6150138
#define SMSTPCR3 0xE615013C
#define SMSTPCR4 0xE6150140
#define SMSTPCR5 0xE6150144
#define SMSTPCR7 0xE615014C
#define SMSTPCR8 0xE6150990
#define SMSTPCR9 0xE6150994
#define SMSTPCR10 0xE6150998
#define SMSTPCR11 0xE615099C
/*
* SH-I2C
* Ch2 and ch3 are different address. These are defined

109
arch/arm/include/asm/arch-rmobile/rcar-mstp.h Normal file
View file

@ -0,0 +1,109 @@
/*
* arch/arm/include/asm/arch-rmobile/rcar-mstp.h
*
* Copyright (C) 2013, 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* Copyright (C) 2013, 2014 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_ARCH_RCAR_MSTP_H
#define __ASM_ARCH_RCAR_MSTP_H
#define mstp_setbits(type, addr, saddr, set) \
out_##type((saddr), in_##type(addr) | (set))
#define mstp_clrbits(type, addr, saddr, clear) \
out_##type((saddr), in_##type(addr) & ~(clear))
#define mstp_setclrbits(type, addr, set, clear) \
out_##type((addr), (in_##type(addr) | (set)) & ~(clear))
#define mstp_setbits_le32(addr, saddr, set) \
mstp_setbits(le32, addr, saddr, set)
#define mstp_clrbits_le32(addr, saddr, clear) \
mstp_clrbits(le32, addr, saddr, clear)
#define mstp_setclrbits_le32(addr, set, clear) \
mstp_setclrbits(le32, addr, set, clear)
#ifndef CONFIG_SMSTP0_ENA
#define CONFIG_SMSTP0_ENA 0x00
#endif
#ifndef CONFIG_SMSTP1_ENA
#define CONFIG_SMSTP1_ENA 0x00
#endif
#ifndef CONFIG_SMSTP2_ENA
#define CONFIG_SMSTP2_ENA 0x00
#endif
#ifndef CONFIG_SMSTP3_ENA
#define CONFIG_SMSTP3_ENA 0x00
#endif
#ifndef CONFIG_SMSTP4_ENA
#define CONFIG_SMSTP4_ENA 0x00
#endif
#ifndef CONFIG_SMSTP5_ENA
#define CONFIG_SMSTP5_ENA 0x00
#endif
#ifndef CONFIG_SMSTP6_ENA
#define CONFIG_SMSTP6_ENA 0x00
#endif
#ifndef CONFIG_SMSTP7_ENA
#define CONFIG_SMSTP7_ENA 0x00
#endif
#ifndef CONFIG_SMSTP8_ENA
#define CONFIG_SMSTP8_ENA 0x00
#endif
#ifndef CONFIG_SMSTP9_ENA
#define CONFIG_SMSTP9_ENA 0x00
#endif
#ifndef CONFIG_SMSTP10_ENA
#define CONFIG_SMSTP10_ENA 0x00
#endif
#ifndef CONFIG_SMSTP11_ENA
#define CONFIG_SMSTP11_ENA 0x00
#endif
#ifndef CONFIG_RMSTP0_ENA
#define CONFIG_RMSTP0_ENA 0x00
#endif
#ifndef CONFIG_RMSTP1_ENA
#define CONFIG_RMSTP1_ENA 0x00
#endif
#ifndef CONFIG_RMSTP2_ENA
#define CONFIG_RMSTP2_ENA 0x00
#endif
#ifndef CONFIG_RMSTP3_ENA
#define CONFIG_RMSTP3_ENA 0x00
#endif
#ifndef CONFIG_RMSTP4_ENA
#define CONFIG_RMSTP4_ENA 0x00
#endif
#ifndef CONFIG_RMSTP5_ENA
#define CONFIG_RMSTP5_ENA 0x00
#endif
#ifndef CONFIG_RMSTP6_ENA
#define CONFIG_RMSTP6_ENA 0x00
#endif
#ifndef CONFIG_RMSTP7_ENA
#define CONFIG_RMSTP7_ENA 0x00
#endif
#ifndef CONFIG_RMSTP8_ENA
#define CONFIG_RMSTP8_ENA 0x00
#endif
#ifndef CONFIG_RMSTP9_ENA
#define CONFIG_RMSTP9_ENA 0x00
#endif
#ifndef CONFIG_RMSTP10_ENA
#define CONFIG_RMSTP10_ENA 0x00
#endif
#ifndef CONFIG_RMSTP11_ENA
#define CONFIG_RMSTP11_ENA 0x00
#endif
struct mstp_ctl {
u32 s_addr;
u32 s_dis;
u32 s_ena;
u32 r_addr;
u32 r_dis;
u32 r_ena;
};
#endif /* __ASM_ARCH_RCAR_MSTP_H */

2
board/renesas/alt/Makefile
View file

@ -6,4 +6,4 @@
# SPDX-License-Identifier: GPL-2.0
#
obj-y := alt.o qos.o
obj-y := alt.o qos.o ../rcar-gen2-common/common.o

46
board/renesas/alt/alt.c
View file

@ -15,6 +15,8 @@
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/rcar-mstp.h>
#include <asm/arch/mmc.h>
#include <netdev.h>
#include <miiphy.h>
#include <i2c.h>
@ -37,30 +39,11 @@ void s_init(void)
qos_init();
}
#define MSTPSR1 0xE6150038
#define SMSTPCR1 0xE6150134
#define TMU0_MSTP125 (1 << 25)
#define MSTPSR7 0xE61501C4
#define SMSTPCR7 0xE615014C
#define SCIF2_MSTP719 (1 << 19)
#define MSTPSR8 0xE61509A0
#define SMSTPCR8 0xE6150990
#define ETHER_MSTP813 (1 << 13)
#define MSTPSR3 0xE6150048
#define SMSTPCR3 0xE615013C
#define IIC1_MSTP323 (1 << 23)
#define mstp_setbits(type, addr, saddr, set) \
out_##type((saddr), in_##type(addr) | (set))
#define mstp_clrbits(type, addr, saddr, clear) \
out_##type((saddr), in_##type(addr) & ~(clear))
#define mstp_setbits_le32(addr, saddr, set) \
mstp_setbits(le32, addr, saddr, set)
#define mstp_clrbits_le32(addr, saddr, clear) \
mstp_clrbits(le32, addr, saddr, clear)
#define MMC0_MSTP315 (1 << 15)
int board_early_init_f(void)
{
@ -76,15 +59,13 @@ int board_early_init_f(void)
/* IIC1 / sh-i2c ch1 */
mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323);
#ifdef CONFIG_SH_MMCIF
/* MMC */
mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315);
#endif
return 0;
}
void arch_preboot_os(void)
{
/* Disable TMU0 */
mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
}
int board_init(void)
{
/* adress of boot parameters */
@ -145,6 +126,19 @@ int board_eth_init(bd_t *bis)
#endif
}
int board_mmc_init(bd_t *bis)
{
int ret = 0;
#ifdef CONFIG_SH_MMCIF
gpio_request(GPIO_GP_4_31, NULL);
gpio_set_value(GPIO_GP_4_31, 1);
ret = mmcif_mmc_init();
#endif
return ret;
}
int dram_init(void)
{
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;

2
board/renesas/gose/Makefile
View file

@ -6,4 +6,4 @@
# SPDX-License-Identifier: GPL-2.0
#
obj-y := gose.o qos.o
obj-y := gose.o qos.o ../rcar-gen2-common/common.o

28
board/renesas/gose/gose.c
View file

@ -15,6 +15,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/rcar-mstp.h>
#include <netdev.h>
#include <miiphy.h>
#include <i2c.h>
@ -41,27 +42,10 @@ void s_init(void)
qos_init();
}
#define MSTPSR1 0xE6150038
#define SMSTPCR1 0xE6150134
#define TMU0_MSTP125 (1 << 25)
#define MSTPSR7 0xE61501C4
#define SMSTPCR7 0xE615014C
#define SCIF0_MSTP721 (1 << 21)
#define MSTPSR8 0xE61509A0
#define SMSTPCR8 0xE6150990
#define ETHER_MSTP813 (1 << 13)
#define mstp_setbits(type, addr, saddr, set) \
out_##type((saddr), in_##type(addr) | (set))
#define mstp_clrbits(type, addr, saddr, clear) \
out_##type((saddr), in_##type(addr) & ~(clear))
#define mstp_setbits_le32(addr, saddr, set) \
mstp_setbits(le32, addr, saddr, set)
#define mstp_clrbits_le32(addr, saddr, clear) \
mstp_clrbits(le32, addr, saddr, clear)
int board_early_init_f(void)
{
/* TMU0 */
@ -76,16 +60,6 @@ int board_early_init_f(void)
return 0;
}
#define TSTR0 0x04
#define TSTR0_STR0 0x01
void arch_preboot_os(void)
{
/* stop TMU0 */
mstp_clrbits_le32(TMU_BASE + TSTR0, TMU_BASE + TSTR0, TSTR0_STR0);
/* Disable TMU0 */
mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
}
#define PUPR5 0xE6060114
#define PUPR5_ETH 0x3FFC0000
#define PUPR5_ETH_MAGIC (1 << 27)

2
board/renesas/koelsch/Makefile
View file

@ -6,4 +6,4 @@
# SPDX-License-Identifier: GPL-2.0
#
obj-y := koelsch.o qos.o
obj-y := koelsch.o qos.o ../rcar-gen2-common/common.o

24
board/renesas/koelsch/koelsch.c
View file

@ -16,6 +16,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/rcar-mstp.h>
#include <netdev.h>
#include <miiphy.h>
#include <i2c.h>
@ -43,27 +44,10 @@ void s_init(void)
qos_init();
}
#define MSTPSR1 0xE6150038
#define SMSTPCR1 0xE6150134
#define TMU0_MSTP125 (1 << 25)
#define MSTPSR7 0xE61501C4
#define SMSTPCR7 0xE615014C
#define SCIF0_MSTP721 (1 << 21)
#define MSTPSR8 0xE61509A0
#define SMSTPCR8 0xE6150990
#define ETHER_MSTP813 (1 << 13)
#define mstp_setbits(type, addr, saddr, set) \
out_##type((saddr), in_##type(addr) | (set))
#define mstp_clrbits(type, addr, saddr, clear) \
out_##type((saddr), in_##type(addr) & ~(clear))
#define mstp_setbits_le32(addr, saddr, set) \
mstp_setbits(le32, addr, saddr, set)
#define mstp_clrbits_le32(addr, saddr, clear) \
mstp_clrbits(le32, addr, saddr, clear)
int board_early_init_f(void)
{
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
@ -77,12 +61,6 @@ int board_early_init_f(void)
return 0;
}
void arch_preboot_os(void)
{
/* Disable TMU0 */
mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
}
/* LSI pin pull-up control */
#define PUPR5 0xe6060114
#define PUPR5_ETH 0x3FFC0000

2
board/renesas/lager/Makefile
View file

@ -6,4 +6,4 @@
# SPDX-License-Identifier: GPL-2.0
#
obj-y := lager.o qos.o
obj-y := lager.o qos.o ../rcar-gen2-common/common.o

51
board/renesas/lager/lager.c
View file

@ -18,8 +18,11 @@
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/rcar-mstp.h>
#include <asm/arch/mmc.h>
#include <miiphy.h>
#include <i2c.h>
#include <mmc.h>
#include "qos.h"
DECLARE_GLOBAL_DATA_PTR;
@ -50,26 +53,10 @@ void s_init(void)
qos_init();
}
#define MSTPSR1 0xE6150038
#define SMSTPCR1 0xE6150134
#define TMU0_MSTP125 (1 << 25)
#define MSTPSR7 0xE61501C4
#define SMSTPCR7 0xE615014C
#define SCIF0_MSTP721 (1 << 21)
#define MSTPSR8 0xE61509A0
#define SMSTPCR8 0xE6150990
#define ETHER_MSTP813 (1 << 13)
#define mstp_setbits(type, addr, saddr, set) \
out_##type((saddr), in_##type(addr) | (set))
#define mstp_clrbits(type, addr, saddr, clear) \
out_##type((saddr), in_##type(addr) & ~(clear))
#define mstp_setbits_le32(addr, saddr, set) \
mstp_setbits(le32, addr, saddr, set)
#define mstp_clrbits_le32(addr, saddr, clear) \
mstp_clrbits(le32, addr, saddr, clear)
#define MMC1_MSTP305 (1 << 5)
int board_early_init_f(void)
{
@ -79,16 +66,12 @@ int board_early_init_f(void)
mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
/* ETHER */
mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
/* eMMC */
mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC1_MSTP305);
return 0;
}
void arch_preboot_os(void)
{
/* Disable TMU0 */
mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
}
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
@ -163,6 +146,28 @@ int board_phy_config(struct phy_device *phydev)
return 0;
}
int board_mmc_init(bd_t *bis)
{
int ret = 0;
#ifdef CONFIG_SH_MMCIF
gpio_request(GPIO_FN_MMC1_D0, NULL);
gpio_request(GPIO_FN_MMC1_D1, NULL);
gpio_request(GPIO_FN_MMC1_D2, NULL);
gpio_request(GPIO_FN_MMC1_D3, NULL);
gpio_request(GPIO_FN_MMC1_D4, NULL);
gpio_request(GPIO_FN_MMC1_D5, NULL);
gpio_request(GPIO_FN_MMC1_D6, NULL);
gpio_request(GPIO_FN_MMC1_D7, NULL);
gpio_request(GPIO_FN_MMC1_CLK, NULL);
gpio_request(GPIO_FN_MMC1_CMD, NULL);
ret = mmcif_mmc_init();
#endif
return ret;
}
int dram_init(void)
{
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;

59
board/renesas/rcar-gen2-common/common.c Normal file
View file

@ -0,0 +1,59 @@
/*
* board/renesas/rcar-gen2-common/common.c
*
* Copyright (C) 2013 Renesas Electronics Corporation
* Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
*
* SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/rcar-mstp.h>
#define TSTR0 0x04
#define TSTR0_STR0 0x01
static struct mstp_ctl mstptbl[] = {
{ SMSTPCR0, MSTP0_BITS, CONFIG_SMSTP0_ENA,
RMSTPCR0, MSTP0_BITS, CONFIG_RMSTP0_ENA },
{ SMSTPCR1, MSTP1_BITS, CONFIG_SMSTP1_ENA,
RMSTPCR1, MSTP1_BITS, CONFIG_RMSTP1_ENA },
{ SMSTPCR2, MSTP2_BITS, CONFIG_SMSTP2_ENA,
RMSTPCR2, MSTP2_BITS, CONFIG_RMSTP2_ENA },
{ SMSTPCR3, MSTP3_BITS, CONFIG_SMSTP3_ENA,
RMSTPCR3, MSTP3_BITS, CONFIG_RMSTP3_ENA },
{ SMSTPCR4, MSTP4_BITS, CONFIG_SMSTP4_ENA,
RMSTPCR4, MSTP4_BITS, CONFIG_RMSTP4_ENA },
{ SMSTPCR5, MSTP5_BITS, CONFIG_SMSTP5_ENA,
RMSTPCR5, MSTP5_BITS, CONFIG_RMSTP5_ENA },
/* No MSTP6 */
{ SMSTPCR7, MSTP7_BITS, CONFIG_SMSTP7_ENA,
RMSTPCR7, MSTP7_BITS, CONFIG_RMSTP7_ENA },
{ SMSTPCR8, MSTP8_BITS, CONFIG_SMSTP8_ENA,
RMSTPCR8, MSTP8_BITS, CONFIG_RMSTP8_ENA },
{ SMSTPCR9, MSTP9_BITS, CONFIG_SMSTP9_ENA,
RMSTPCR9, MSTP9_BITS, CONFIG_RMSTP9_ENA },
{ SMSTPCR10, MSTP10_BITS, CONFIG_SMSTP10_ENA,
RMSTPCR10, MSTP10_BITS, CONFIG_RMSTP10_ENA },
{ SMSTPCR11, MSTP11_BITS, CONFIG_SMSTP1_ENA,
RMSTPCR11, MSTP11_BITS, CONFIG_RMSTP11_ENA },
};
void arch_preboot_os(void)
{
int i;
/* stop TMU0 */
mstp_clrbits_le32(TMU_BASE + TSTR0, TMU_BASE + TSTR0, TSTR0_STR0);
/* Stop module clock */
for (i = 0; i < ARRAY_SIZE(mstptbl); i++) {
mstp_setclrbits_le32(mstptbl[i].s_addr, mstptbl[i].s_dis,
mstptbl[i].s_ena);
mstp_setclrbits_le32(mstptbl[i].r_addr, mstptbl[i].r_dis,
mstptbl[i].r_ena);
}
}

19
include/configs/alt.h
View file

@ -95,4 +95,23 @@
#define CONFIG_USB_EHCI_RMOBILE
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
/* MMCIF */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_CMD_MMC
#define CONFIG_SH_MMCIF
#define CONFIG_SH_MMCIF_ADDR 0xee200000
#define CONFIG_SH_MMCIF_CLK 48000000
/* Module stop status bits */
/* INTC-RT */
#define CONFIG_SMSTP0_ENA 0x00400000
/* MSIF */
#define CONFIG_SMSTP2_ENA 0x00002000
/* INTC-SYS, IRQC */
#define CONFIG_SMSTP4_ENA 0x00000180
/* SCIF2 */
#define CONFIG_SMSTP7_ENA 0x00080000
#endif /* __ALT_H */

10
include/configs/gose.h
View file

@ -91,4 +91,14 @@
#define CONFIG_USB_EHCI_RMOBILE
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
/* Module stop status bits */
/* INTC-RT */
#define CONFIG_SMSTP0_ENA 0x00400000
/* MSIF */
#define CONFIG_SMSTP2_ENA 0x00002000
/* INTC-SYS, IRQC */
#define CONFIG_SMSTP4_ENA 0x00000180
/* SCIF0 */
#define CONFIG_SMSTP7_ENA 0x00200000
#endif /* __GOSE_H */

11
include/configs/koelsch.h
View file

@ -92,4 +92,15 @@
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_USB_STORAGE
/* Module stop status bits */
/* INTC-RT */
#define CONFIG_SMSTP0_ENA 0x00400000
/* MSIF*/
#define CONFIG_SMSTP2_ENA 0x00002000
/* INTC-SYS, IRQC */
#define CONFIG_SMSTP4_ENA 0x00000180
/* SCIF0 */
#define CONFIG_SMSTP7_ENA 0x00200000
#endif /* __KOELSCH_H */

19
include/configs/lager.h
View file

@ -93,4 +93,23 @@
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
#define CONFIG_USB_STORAGE
/* MMC */
#define CONFIG_MMC
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_SH_MMCIF
#define CONFIG_SH_MMCIF_ADDR 0xEE220000
#define CONFIG_SH_MMCIF_CLK 97500000
/* Module stop status bits */
/* INTC-RT */
#define CONFIG_SMSTP0_ENA 0x00400000
/* MSIF */
#define CONFIG_SMSTP2_ENA 0x00002000
/* INTC-SYS, IRQC */
#define CONFIG_SMSTP4_ENA 0x00000180
/* SCIF0 */
#define CONFIG_SMSTP7_ENA 0x00200000
#endif /* __LAGER_H */

4
include/configs/rcar-gen2-common.h
View file

@ -28,6 +28,9 @@
#define CONFIG_CMD_FAT
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_EXT4_WRITE
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_SYS_GENERIC_BOARD
@ -36,6 +39,7 @@
#define CONFIG_FAT_WRITE
#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_VFAT
#define CONFIG_FS_EXT4
#define CONFIG_EXT4_WRITE
#define CONFIG_CMDLINE_TAG