mirror of
https://github.com/AsahiLinux/u-boot
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ppc4xx: remove PMC405 board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
This commit is contained in:
Matthias Fuchs
Tom Rini
parent
dbe7bb0d21
commit
d526330479
8 changed files with 1 additions and 498 deletions
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@ -128,9 +128,6 @@ config TARGET_CPCI405DT
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config TARGET_PLU405
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bool "Support PLU405"
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config TARGET_PMC405
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bool "Support PMC405"
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config TARGET_PMC405DE
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bool "Support PMC405DE"
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@ -224,7 +221,6 @@ source "board/dave/PPChameleonEVB/Kconfig"
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source "board/esd/cpci2dp/Kconfig"
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source "board/esd/cpci405/Kconfig"
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source "board/esd/plu405/Kconfig"
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source "board/esd/pmc405/Kconfig"
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source "board/esd/pmc405de/Kconfig"
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source "board/esd/pmc440/Kconfig"
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source "board/esd/voh405/Kconfig"
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@ -1,12 +0,0 @@
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if TARGET_PMC405
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config SYS_BOARD
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default "pmc405"
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config SYS_VENDOR
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default "esd"
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config SYS_CONFIG_NAME
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default "PMC405"
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endif
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@ -1,6 +0,0 @@
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PMC405 BOARD
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M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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S: Maintained
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F: board/esd/pmc405/
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F: include/configs/PMC405.h
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F: configs/PMC405_defconfig
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@ -1,13 +0,0 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Objects for Xilinx JTAG programming (CPLD)
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CPLD = ../common/xilinx_jtag/lenval.o \
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../common/xilinx_jtag/micro.o \
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../common/xilinx_jtag/ports.o
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obj-y = pmc405.o ../common/misc.o ../common/cmd_loadpci.o $(CPLD)
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@ -1,142 +0,0 @@
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/*
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* (C) Copyright 2001-2003
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* (C) Copyright 2005-2009
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* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <command.h>
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#include <malloc.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern void lxt971_no_sleep(void);
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int board_early_init_f (void)
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{
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/*
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* IRQ 0-15 405GP internally generated; active high; level sensitive
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* IRQ 16 405GP internally generated; active low; level sensitive
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* IRQ 17-24 RESERVED
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* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
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* IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
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* IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
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* IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
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* IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
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* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
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* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
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*/
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mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
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mtdcr(UIC0ER, 0x00000000); /* disable all ints */
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mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
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mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
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mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
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mtdcr(UIC0VCR, 0x00000001); /* set vect base=0, INT0 highest priority */
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mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
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/*
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* EBC Configuration Register:
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* set ready timeout to 512 ebc-clks -> ca. 15 us
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*/
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mtebc (EBC0_CFG, 0xa8400000);
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/*
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* Setup GPIO pins
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*/
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mtdcr(CPC0_CR0, mfdcr(CPC0_CR0) | ((CONFIG_SYS_FPGA_INIT |
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CONFIG_SYS_FPGA_DONE |
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CONFIG_SYS_XEREADY |
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CONFIG_SYS_NONMONARCH |
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CONFIG_SYS_REV1_2) << 5));
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if (!(in_be32((void *)GPIO0_IR) & CONFIG_SYS_REV1_2)) {
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/* rev 1.2 boards */
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mtdcr(CPC0_CR0, mfdcr(CPC0_CR0) | ((CONFIG_SYS_INTA_FAKE |
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CONFIG_SYS_SELF_RST) << 5));
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}
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out_be32((void *)GPIO0_OR, CONFIG_SYS_VPEN);
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/* setup for output */
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out_be32((void *)GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK |
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CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY | CONFIG_SYS_VPEN);
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/*
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* - check if rev1_2 is low, then:
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* - set/reset CONFIG_SYS_INTA_FAKE/CONFIG_SYS_SELF_RST
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* in TCR to assert INTA# or SELFRST#
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*/
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return 0;
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}
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int misc_init_r (void)
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{
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/* adjust flash start and offset */
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gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
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gd->bd->bi_flashoffset = 0;
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/* deassert EREADY# */
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out_be32((void *)GPIO0_OR,
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in_be32((void *)GPIO0_OR) | CONFIG_SYS_XEREADY);
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return (0);
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}
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ushort pmc405_pci_subsys_deviceid(void)
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{
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ulong val;
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val = in_be32((void *)GPIO0_IR);
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if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */
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/* check monarch# signal */
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if (val & CONFIG_SYS_NONMONARCH)
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return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH;
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return CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH;
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}
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return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH;
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}
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/*
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* Check Board Identity
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*/
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int checkboard (void)
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{
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ulong val;
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char str[64];
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int i = getenv_f("serial#", str, sizeof(str));
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puts ("Board: ");
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if (i == -1)
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puts ("### No HW ID - assuming PMC405");
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else
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puts(str);
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val = in_be32((void *)GPIO0_IR);
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if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */
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puts(" rev1.2 (");
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if (val & CONFIG_SYS_NONMONARCH) /* monarch# signal */
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puts("non-");
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puts("monarch)");
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} else
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puts(" <=rev1.1");
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putc ('\n');
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return 0;
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}
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void reset_phy(void)
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{
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#ifdef CONFIG_LXT971_NO_SLEEP
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/*
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* Disable sleep mode in LXT971
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*/
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lxt971_no_sleep();
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#endif
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}
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@ -1,3 +0,0 @@
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CONFIG_PPC=y
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CONFIG_4xx=y
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CONFIG_TARGET_PMC405=y
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@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
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Board Arch CPU Commit Removed Last known maintainer/contact
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=================================================================================================
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PMC405 ppc4xx 405gp - - Matthias Fuchs <matthias.fuchs@esd.eu>
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PCI405 ppc4xx 405gp - - Matthias Fuchs <matthias.fuchs@esd.eu>
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OCRTC ppc4xx 405gpr - - Matthias Fuchs <matthias.fuchs@esd.eu>
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HUB405 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs@esd.eu>
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@ -1,318 +0,0 @@
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/*
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* (C) Copyright 2001-2004
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_405GP 1 /* This is a PPC405 CPU */
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#define CONFIG_PMC405 1 /* ...on a PMC405 board */
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#define CONFIG_SYS_TEXT_BASE 0xFFF80000
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
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#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
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#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
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#define CONFIG_BAUDRATE 9600
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#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
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/* Only interrupt boot if space is pressed. */
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#define CONFIG_AUTOBOOT_KEYED 1
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#define CONFIG_AUTOBOOT_PROMPT \
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"Press SPACE to abort autoboot in %d seconds\n", bootdelay
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#undef CONFIG_AUTOBOOT_DELAY_STR
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#define CONFIG_AUTOBOOT_STOP_STR " "
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#undef CONFIG_BOOTARGS
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#undef CONFIG_BOOTCOMMAND
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#define CONFIG_PREBOOT /* enable preboot variable */
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#define CFG_BOOTM_LEN 0x1000000 /* support booting of huge images */
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#undef CONFIG_HAS_ETH1
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#define CONFIG_PPC4xx_EMAC
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 0 /* PHY address */
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#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
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#define CONFIG_RESET_PHY_R 1 /* use reset_phy() */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_BSP
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_UNIVERSE
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#define CONFIG_CMD_EEPROM
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible */
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#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
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#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Sz */
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#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
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#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console info */
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#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
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#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#define CONFIG_CONS_INDEX 1 /* Use UART0 */
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_serial_clock()
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#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock */
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#define CONFIG_SYS_BASE_BAUD 806400
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/* The following table includes the supported baudrates */
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
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#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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#define CONFIG_LOOPW 1 /* enable loopw command */
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
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#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
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#define CONFIG_SYS_RX_ETH_BUFFER 16
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/*
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* PCI stuff
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*/
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#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
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#define PCI_HOST_FORCE 1 /* configure as pci host */
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#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
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#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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/* resource configuration */
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#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
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#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config */
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
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#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH 0x0408 /* PCI Device ID */
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#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH 0x0409 /* PCI Device ID */
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#define CONFIG_SYS_PCI_SUBSYS_DEVICEID pmc405_pci_subsys_deviceid()
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#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* Processor/PPC */
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#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
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#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable */
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#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
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#define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to internal regs */
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#define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable */
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#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
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#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */
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/*
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
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#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* 128 kB for malloc() */
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#define CONFIG_PRAM 0 /* use pram variable to overwrite */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*
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* FLASH organization
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*/
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#define CONFIG_SYS_FLASH_BASE 0xFE000000
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#define CONFIG_SYS_FLASH_INCREMENT 0x01000000
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#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
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#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
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#define CONFIG_SYS_FLASH_PROTECTION 1 /* don't use hardware protection */
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#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST {{0xfff80000, 0x80000}}
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (faster) */
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#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
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#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
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CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT}
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#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on fli */
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/*
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* Environment Variable setup
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*/
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#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
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/* environment starts at the beginning of the EEPROM */
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#define CONFIG_ENV_OFFSET 0x000
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#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars */
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#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
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#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
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/*
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* I2C EEPROM (CAT24WC16) for environment
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*/
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_PPC4XX
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#define CONFIG_SYS_I2C_PPC4XX_CH0
|
||||
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
|
||||
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
|
||||
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24W16 */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
|
||||
/* mask of address bits that overflow into the "EEPROM chip address" */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24W16 has */
|
||||
/* 16 byte page write mode using*/
|
||||
/* last 4 bits of the address */
|
||||
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
|
||||
|
||||
/*
|
||||
* External Bus Controller (EBC) Setup
|
||||
*/
|
||||
#define FLASH0_BA 0xFF000000 /* FLASH 0 Base Address */
|
||||
#define FLASH1_BA 0xFE000000 /* FLASH 1 Base Address */
|
||||
#define CAN_BA 0xF0000000 /* CAN Base Addres */
|
||||
#define RTC_BA 0xF0000500 /* RTC Base Address */
|
||||
#define NVRAM_BA 0xF0200000 /* NVRAM Base Address */
|
||||
|
||||
/* Memory Bank 0 (Flash Bank 0) initialization */
|
||||
#define CONFIG_SYS_EBC_PB0AP 0x92015480
|
||||
/* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */
|
||||
#define CONFIG_SYS_EBC_PB0CR (FLASH0_BA | 0x9A000)
|
||||
|
||||
/* Memory Bank 1 (Flash Bank 1) initialization */
|
||||
#define CONFIG_SYS_EBC_PB1AP 0x92015480
|
||||
/* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
|
||||
#define CONFIG_SYS_EBC_PB1CR (FLASH1_BA | 0x9A000)
|
||||
|
||||
/* Memory Bank 2 (CAN0, 1, RTC) initialization */
|
||||
/* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */
|
||||
#define CONFIG_SYS_EBC_PB2AP 0x03000440
|
||||
/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
|
||||
#define CONFIG_SYS_EBC_PB2CR (CAN_BA | 0x18000)
|
||||
|
||||
/* Memory Bank 3 -> unused */
|
||||
|
||||
/* Memory Bank 4 (NVRAM) initialization */
|
||||
/* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */
|
||||
#define CONFIG_SYS_EBC_PB4AP 0x03000440
|
||||
/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
|
||||
#define CONFIG_SYS_EBC_PB4CR (NVRAM_BA | 0x18000)
|
||||
|
||||
/*
|
||||
* FPGA stuff
|
||||
*/
|
||||
/* FPGA program pin configuration */
|
||||
#define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (output) */
|
||||
#define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (output) */
|
||||
#define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO pin (output) */
|
||||
#define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */
|
||||
#define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI pin (input) */
|
||||
|
||||
/* pass Ethernet MAC to VxWorks */
|
||||
#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000
|
||||
|
||||
/*
|
||||
* GPIOs
|
||||
*/
|
||||
#define CONFIG_SYS_VPEN (0x80000000 >> 3) /* GPIO3 */
|
||||
#define CONFIG_SYS_NONMONARCH (0x80000000 >> 14) /* GPIO14 */
|
||||
#define CONFIG_SYS_XEREADY (0x80000000 >> 15) /* GPIO15 */
|
||||
#define CONFIG_SYS_INTA_FAKE (0x80000000 >> 19) /* GPIO19 */
|
||||
#define CONFIG_SYS_SELF_RST (0x80000000 >> 21) /* GPIO21 */
|
||||
#define CONFIG_SYS_REV1_2 (0x80000000 >> 23) /* GPIO23 */
|
||||
|
||||
/*
|
||||
* Definitions for initial stack pointer and data area (in data cache)
|
||||
*/
|
||||
|
||||
/* use on chip memory (OCM) for temperary stack until sdram is tested */
|
||||
#define CONFIG_SYS_TEMP_STACK_OCM 1
|
||||
|
||||
/* On Chip Memory location */
|
||||
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
|
||||
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
|
||||
|
||||
/* inside of SDRAM */
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
|
||||
|
||||
/* End of used area in RAM */
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#define CONFIG_OF_LIBFDT
|
||||
#define CONFIG_OF_BOARD_SETUP
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Add table
Reference in a new issue