mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
This commit is contained in:
Tom Rini
commit
3bfbf32b6f
17 changed files with 1901 additions and 52 deletions
|
|
@ -38,8 +38,7 @@ void sys_mgr_frzctrl_freeze_req(void)
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|||
/* Freeze channel 0 to 2 */
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for (channel_id = 0; channel_id <= 2; channel_id++) {
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ioctrl_reg_offset = (u32)(
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&freeze_controller_base->vioctrl +
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(channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT));
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&freeze_controller_base->vioctrl + channel_id);
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/*
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* Assert active low enrnsl, plniotri
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@ -120,8 +119,7 @@ void sys_mgr_frzctrl_thaw_req(void)
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/* Thaw channel 0 to 2 */
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for (channel_id = 0; channel_id <= 2; channel_id++) {
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ioctrl_reg_offset
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= (u32)(&freeze_controller_base->vioctrl
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+ (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT));
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= (u32)(&freeze_controller_base->vioctrl + channel_id);
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/*
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* Assert active low bhniotri signal and
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|
|
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@ -110,6 +110,6 @@ void socfpga_spim_enable(void)
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{
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const void *reset = &reset_manager_base->per_mod_reset;
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clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM0_LSB);
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clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM1_LSB);
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clrbits_le32(reset, (1 << RSTMGR_PERMODRST_SPIM0_LSB) |
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(1 << RSTMGR_PERMODRST_SPIM1_LSB));
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}
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@ -1,18 +1,7 @@
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/*
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* Copyright (C) 2012 Altera <www.altera.com>
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||||
*
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||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
* SPDX-License-Identifier: GPL-2.0+
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*/
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#include "skeleton.dtsi"
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@ -639,6 +628,49 @@
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clock-names = "biu", "ciu";
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};
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qspi: spi@ff705000 {
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compatible = "cadence,qspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xff705000 0x1000>,
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<0xffa00000 0x1000>;
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interrupts = <0 151 4>;
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clocks = <&qspi_clk>;
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ext-decoder = <0>; /* external decoder */
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num-chipselect = <4>;
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fifo-depth = <128>;
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bus-num = <2>;
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status = "disabled";
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};
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spi0: spi@fff00000 {
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compatible = "snps,dw-spi-mmio";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xfff00000 0x1000>;
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interrupts = <0 154 4>;
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num-chipselect = <4>;
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bus-num = <0>;
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tx-dma-channel = <&pdma 16>;
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rx-dma-channel = <&pdma 17>;
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clocks = <&per_base_clk>;
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status = "disabled";
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};
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spi1: spi@fff01000 {
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compatible = "snps,dw-spi-mmio";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xfff01000 0x1000>;
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interrupts = <0 156 4>;
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num-chipselect = <4>;
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bus-num = <1>;
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tx-dma-channel = <&pdma 20>;
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rx-dma-channel = <&pdma 21>;
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clocks = <&per_base_clk>;
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status = "disabled";
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};
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/* Local timer */
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timer@fffec600 {
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compatible = "arm,cortex-a9-twd-timer";
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|
|
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@ -1,18 +1,7 @@
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|||
/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
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||||
* SPDX-License-Identifier: GPL-2.0+
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||||
*/
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/dts-v1/;
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|
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@ -1,18 +1,7 @@
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/*
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||||
* Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
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||||
*
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||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
* SPDX-License-Identifier: GPL-2.0+
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*/
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#include "socfpga_cyclone5.dtsi"
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@ -25,6 +14,12 @@
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bootargs = "console=ttyS0,115200";
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};
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aliases {
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spi0 = "/spi@ff705000"; /* QSPI */
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spi1 = "/spi@fff00000";
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spi2 = "/spi@fff01000";
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};
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memory {
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name = "memory";
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device_type = "memory";
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@ -48,3 +43,23 @@
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&mmc {
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status = "okay";
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};
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&qspi {
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status = "okay";
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flash0: n25q00@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "n25q00";
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reg = <0>; /* chip select */
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spi-max-frequency = <50000000>;
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m25p,fast-read;
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page-size = <256>;
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block-size = <16>; /* 2^16, 64KB */
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read-delay = <4>; /* delay value in read data capture register */
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tshsl-ns = <50>;
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tsd2d-ns = <50>;
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tchsh-ns = <4>;
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tslch-ns = <4>;
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};
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};
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|
|
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|||
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@ -14,6 +14,7 @@ unsigned long cm_get_sdram_clk_hz(void);
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|||
unsigned int cm_get_l4_sp_clk_hz(void);
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||||
unsigned int cm_get_mmc_controller_clk_hz(void);
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||||
unsigned int cm_get_qspi_controller_clk_hz(void);
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||||
unsigned int cm_get_spi_controller_clk_hz(void);
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||||
#endif
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||||
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||||
typedef struct {
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||||
|
|
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|||
|
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@ -42,7 +42,6 @@ typedef enum {
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|||
#define SYSMGR_FRZCTRL_HWCTRL_VIO1REQ_MASK 0x00000001
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||||
#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_FROZEN 0x2
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||||
#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_THAWED 0x1
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#define SYSMGR_FRZCTRL_VIOCTRL_SHIFT 0x2
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||||
void sys_mgr_frzctrl_freeze_req(void);
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void sys_mgr_frzctrl_thaw_req(void);
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@ -13,6 +13,7 @@ struct socfpga_scan_manager {
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|||
u32 padding[2];
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||||
u32 fifo_single_byte;
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||||
u32 fifo_double_byte;
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||||
u32 fifo_triple_byte;
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||||
u32 fifo_quad_byte;
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};
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|
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@ -5,3 +5,8 @@ S: Maintained
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|||
F: board/altera/socfpga/
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F: include/configs/socfpga_cyclone5.h
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F: configs/socfpga_cyclone5_defconfig
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||||
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||||
SOCRATES BOARD
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||||
M: Stefan Roese <sr@denx.de>
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||||
S: Maintained
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||||
F: configs/socfpga_socrates_defconfig
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@ -12,7 +12,9 @@
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|||
#include <usb/s3c_udc.h>
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#include <usb_mass_storage.h>
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#include <micrel.h>
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||||
#include <netdev.h>
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#include <phy.h>
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DECLARE_GLOBAL_DATA_PTR;
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@ -44,6 +46,42 @@ int board_init(void)
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return 0;
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}
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/*
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* PHY configuration
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*/
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#ifdef CONFIG_PHY_MICREL_KSZ9021
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int board_phy_config(struct phy_device *phydev)
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{
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int ret;
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/*
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* These skew settings for the KSZ9021 ethernet phy is required for ethernet
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* to work reliably on most flavors of cyclone5 boards.
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*/
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ret = ksz9021_phy_extended_write(phydev,
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MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
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0x0);
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if (ret)
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||||
return ret;
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ret = ksz9021_phy_extended_write(phydev,
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MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
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0x0);
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if (ret)
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return ret;
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ret = ksz9021_phy_extended_write(phydev,
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MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
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0xf0f0);
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if (ret)
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return ret;
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|
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if (phydev->drv->config)
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return phydev->drv->config(phydev);
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return 0;
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}
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#endif
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#ifdef CONFIG_USB_GADGET
|
||||
struct s3c_plat_otg_data socfpga_otg_data = {
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.regs_otg = CONFIG_USB_DWC2_REG_ADDR,
|
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|
|
|
|||
|
|
@ -23,9 +23,11 @@ obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
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|||
obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
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||||
obj-$(CONFIG_BFIN_SPI) += bfin_spi.o
|
||||
obj-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
|
||||
obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
|
||||
obj-$(CONFIG_CF_SPI) += cf_spi.o
|
||||
obj-$(CONFIG_CF_QSPI) += cf_qspi.o
|
||||
obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
|
||||
obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o
|
||||
obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
|
||||
obj-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o
|
||||
obj-$(CONFIG_ICH_SPI) += ich.o
|
||||
|
|
|
|||
345
drivers/spi/cadence_qspi.c
Normal file
345
drivers/spi/cadence_qspi.c
Normal file
|
|
@ -0,0 +1,345 @@
|
|||
/*
|
||||
* Copyright (C) 2012
|
||||
* Altera Corporation <www.altera.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <fdtdec.h>
|
||||
#include <malloc.h>
|
||||
#include <spi.h>
|
||||
#include <asm/errno.h>
|
||||
#include "cadence_qspi.h"
|
||||
|
||||
#define CQSPI_STIG_READ 0
|
||||
#define CQSPI_STIG_WRITE 1
|
||||
#define CQSPI_INDIRECT_READ 2
|
||||
#define CQSPI_INDIRECT_WRITE 3
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static int cadence_spi_write_speed(struct udevice *bus, uint hz)
|
||||
{
|
||||
struct cadence_spi_platdata *plat = bus->platdata;
|
||||
struct cadence_spi_priv *priv = dev_get_priv(bus);
|
||||
|
||||
cadence_qspi_apb_config_baudrate_div(priv->regbase,
|
||||
CONFIG_CQSPI_REF_CLK, hz);
|
||||
|
||||
/* Reconfigure delay timing if speed is changed. */
|
||||
cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz,
|
||||
plat->tshsl_ns, plat->tsd2d_ns,
|
||||
plat->tchsh_ns, plat->tslch_ns);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Calibration sequence to determine the read data capture delay register */
|
||||
static int spi_calibration(struct udevice *bus)
|
||||
{
|
||||
struct cadence_spi_platdata *plat = bus->platdata;
|
||||
struct cadence_spi_priv *priv = dev_get_priv(bus);
|
||||
void *base = priv->regbase;
|
||||
u8 opcode_rdid = 0x9F;
|
||||
unsigned int idcode = 0, temp = 0;
|
||||
int err = 0, i, range_lo = -1, range_hi = -1;
|
||||
|
||||
/* start with slowest clock (1 MHz) */
|
||||
cadence_spi_write_speed(bus, 1000000);
|
||||
|
||||
/* configure the read data capture delay register to 0 */
|
||||
cadence_qspi_apb_readdata_capture(base, 1, 0);
|
||||
|
||||
/* Enable QSPI */
|
||||
cadence_qspi_apb_controller_enable(base);
|
||||
|
||||
/* read the ID which will be our golden value */
|
||||
err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
|
||||
3, (u8 *)&idcode);
|
||||
if (err) {
|
||||
puts("SF: Calibration failed (read)\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
/* use back the intended clock and find low range */
|
||||
cadence_spi_write_speed(bus, plat->max_hz);
|
||||
for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
|
||||
/* Disable QSPI */
|
||||
cadence_qspi_apb_controller_disable(base);
|
||||
|
||||
/* reconfigure the read data capture delay register */
|
||||
cadence_qspi_apb_readdata_capture(base, 1, i);
|
||||
|
||||
/* Enable back QSPI */
|
||||
cadence_qspi_apb_controller_enable(base);
|
||||
|
||||
/* issue a RDID to get the ID value */
|
||||
err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
|
||||
3, (u8 *)&temp);
|
||||
if (err) {
|
||||
puts("SF: Calibration failed (read)\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
/* search for range lo */
|
||||
if (range_lo == -1 && temp == idcode) {
|
||||
range_lo = i;
|
||||
continue;
|
||||
}
|
||||
|
||||
/* search for range hi */
|
||||
if (range_lo != -1 && temp != idcode) {
|
||||
range_hi = i - 1;
|
||||
break;
|
||||
}
|
||||
range_hi = i;
|
||||
}
|
||||
|
||||
if (range_lo == -1) {
|
||||
puts("SF: Calibration failed (low range)\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
/* Disable QSPI for subsequent initialization */
|
||||
cadence_qspi_apb_controller_disable(base);
|
||||
|
||||
/* configure the final value for read data capture delay register */
|
||||
cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2);
|
||||
debug("SF: Read data capture delay calibrated to %i (%i - %i)\n",
|
||||
(range_hi + range_lo) / 2, range_lo, range_hi);
|
||||
|
||||
/* just to ensure we do once only when speed or chip select change */
|
||||
priv->qspi_calibrated_hz = plat->max_hz;
|
||||
priv->qspi_calibrated_cs = spi_chip_select(bus);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cadence_spi_set_speed(struct udevice *bus, uint hz)
|
||||
{
|
||||
struct cadence_spi_platdata *plat = bus->platdata;
|
||||
struct cadence_spi_priv *priv = dev_get_priv(bus);
|
||||
int err;
|
||||
|
||||
/* Disable QSPI */
|
||||
cadence_qspi_apb_controller_disable(priv->regbase);
|
||||
|
||||
cadence_spi_write_speed(bus, hz);
|
||||
|
||||
/* Calibration required for different SCLK speed or chip select */
|
||||
if (priv->qspi_calibrated_hz != plat->max_hz ||
|
||||
priv->qspi_calibrated_cs != spi_chip_select(bus)) {
|
||||
err = spi_calibration(bus);
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
|
||||
/* Enable QSPI */
|
||||
cadence_qspi_apb_controller_enable(priv->regbase);
|
||||
|
||||
debug("%s: speed=%d\n", __func__, hz);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cadence_spi_probe(struct udevice *bus)
|
||||
{
|
||||
struct cadence_spi_platdata *plat = bus->platdata;
|
||||
struct cadence_spi_priv *priv = dev_get_priv(bus);
|
||||
|
||||
priv->regbase = plat->regbase;
|
||||
priv->ahbbase = plat->ahbbase;
|
||||
|
||||
if (!priv->qspi_is_init) {
|
||||
cadence_qspi_apb_controller_init(plat);
|
||||
priv->qspi_is_init = 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cadence_spi_set_mode(struct udevice *bus, uint mode)
|
||||
{
|
||||
struct cadence_spi_priv *priv = dev_get_priv(bus);
|
||||
unsigned int clk_pol = (mode & SPI_CPOL) ? 1 : 0;
|
||||
unsigned int clk_pha = (mode & SPI_CPHA) ? 1 : 0;
|
||||
|
||||
/* Disable QSPI */
|
||||
cadence_qspi_apb_controller_disable(priv->regbase);
|
||||
|
||||
/* Set SPI mode */
|
||||
cadence_qspi_apb_set_clk_mode(priv->regbase, clk_pol, clk_pha);
|
||||
|
||||
/* Enable QSPI */
|
||||
cadence_qspi_apb_controller_enable(priv->regbase);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cadence_spi_xfer(struct udevice *dev, unsigned int bitlen,
|
||||
const void *dout, void *din, unsigned long flags)
|
||||
{
|
||||
struct udevice *bus = dev->parent;
|
||||
struct cadence_spi_platdata *plat = bus->platdata;
|
||||
struct cadence_spi_priv *priv = dev_get_priv(bus);
|
||||
void *base = priv->regbase;
|
||||
u8 *cmd_buf = priv->cmd_buf;
|
||||
size_t data_bytes;
|
||||
int err = 0;
|
||||
u32 mode = CQSPI_STIG_WRITE;
|
||||
|
||||
if (flags & SPI_XFER_BEGIN) {
|
||||
/* copy command to local buffer */
|
||||
priv->cmd_len = bitlen / 8;
|
||||
memcpy(cmd_buf, dout, priv->cmd_len);
|
||||
}
|
||||
|
||||
if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) {
|
||||
/* if start and end bit are set, the data bytes is 0. */
|
||||
data_bytes = 0;
|
||||
} else {
|
||||
data_bytes = bitlen / 8;
|
||||
}
|
||||
debug("%s: len=%d [bytes]\n", __func__, data_bytes);
|
||||
|
||||
/* Set Chip select */
|
||||
cadence_qspi_apb_chipselect(base, spi_chip_select(dev),
|
||||
CONFIG_CQSPI_DECODER);
|
||||
|
||||
if ((flags & SPI_XFER_END) || (flags == 0)) {
|
||||
if (priv->cmd_len == 0) {
|
||||
printf("QSPI: Error, command is empty.\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (din && data_bytes) {
|
||||
/* read */
|
||||
/* Use STIG if no address. */
|
||||
if (!CQSPI_IS_ADDR(priv->cmd_len))
|
||||
mode = CQSPI_STIG_READ;
|
||||
else
|
||||
mode = CQSPI_INDIRECT_READ;
|
||||
} else if (dout && !(flags & SPI_XFER_BEGIN)) {
|
||||
/* write */
|
||||
if (!CQSPI_IS_ADDR(priv->cmd_len))
|
||||
mode = CQSPI_STIG_WRITE;
|
||||
else
|
||||
mode = CQSPI_INDIRECT_WRITE;
|
||||
}
|
||||
|
||||
switch (mode) {
|
||||
case CQSPI_STIG_READ:
|
||||
err = cadence_qspi_apb_command_read(
|
||||
base, priv->cmd_len, cmd_buf,
|
||||
data_bytes, din);
|
||||
|
||||
break;
|
||||
case CQSPI_STIG_WRITE:
|
||||
err = cadence_qspi_apb_command_write(base,
|
||||
priv->cmd_len, cmd_buf,
|
||||
data_bytes, dout);
|
||||
break;
|
||||
case CQSPI_INDIRECT_READ:
|
||||
err = cadence_qspi_apb_indirect_read_setup(plat,
|
||||
priv->cmd_len, cmd_buf);
|
||||
if (!err) {
|
||||
err = cadence_qspi_apb_indirect_read_execute
|
||||
(plat, data_bytes, din);
|
||||
}
|
||||
break;
|
||||
case CQSPI_INDIRECT_WRITE:
|
||||
err = cadence_qspi_apb_indirect_write_setup
|
||||
(plat, priv->cmd_len, cmd_buf);
|
||||
if (!err) {
|
||||
err = cadence_qspi_apb_indirect_write_execute
|
||||
(plat, data_bytes, dout);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
err = -1;
|
||||
break;
|
||||
}
|
||||
|
||||
if (flags & SPI_XFER_END) {
|
||||
/* clear command buffer */
|
||||
memset(cmd_buf, 0, sizeof(priv->cmd_buf));
|
||||
priv->cmd_len = 0;
|
||||
}
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
|
||||
{
|
||||
struct cadence_spi_platdata *plat = bus->platdata;
|
||||
const void *blob = gd->fdt_blob;
|
||||
int node = bus->of_offset;
|
||||
int subnode;
|
||||
u32 data[4];
|
||||
int ret;
|
||||
|
||||
/* 2 base addresses are needed, lets get them from the DT */
|
||||
ret = fdtdec_get_int_array(blob, node, "reg", data, ARRAY_SIZE(data));
|
||||
if (ret) {
|
||||
printf("Error: Can't get base addresses (ret=%d)!\n", ret);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
plat->regbase = (void *)data[0];
|
||||
plat->ahbbase = (void *)data[2];
|
||||
|
||||
/* Use 500KHz as a suitable default */
|
||||
plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
|
||||
500000);
|
||||
|
||||
/* All other paramters are embedded in the child node */
|
||||
subnode = fdt_first_subnode(blob, node);
|
||||
if (!subnode) {
|
||||
printf("Error: subnode with SPI flash config missing!\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Read other parameters from DT */
|
||||
plat->page_size = fdtdec_get_int(blob, subnode, "page-size", 256);
|
||||
plat->block_size = fdtdec_get_int(blob, subnode, "block-size", 16);
|
||||
plat->tshsl_ns = fdtdec_get_int(blob, subnode, "tshsl-ns", 200);
|
||||
plat->tsd2d_ns = fdtdec_get_int(blob, subnode, "tsd2d-ns", 255);
|
||||
plat->tchsh_ns = fdtdec_get_int(blob, subnode, "tchsh-ns", 20);
|
||||
plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20);
|
||||
|
||||
debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
|
||||
__func__, plat->regbase, plat->ahbbase, plat->max_hz,
|
||||
plat->page_size);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dm_spi_ops cadence_spi_ops = {
|
||||
.xfer = cadence_spi_xfer,
|
||||
.set_speed = cadence_spi_set_speed,
|
||||
.set_mode = cadence_spi_set_mode,
|
||||
/*
|
||||
* cs_info is not needed, since we require all chip selects to be
|
||||
* in the device tree explicitly
|
||||
*/
|
||||
};
|
||||
|
||||
static const struct udevice_id cadence_spi_ids[] = {
|
||||
{ .compatible = "cadence,qspi" },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(cadence_spi) = {
|
||||
.name = "cadence_spi",
|
||||
.id = UCLASS_SPI,
|
||||
.of_match = cadence_spi_ids,
|
||||
.ops = &cadence_spi_ops,
|
||||
.ofdata_to_platdata = cadence_spi_ofdata_to_platdata,
|
||||
.platdata_auto_alloc_size = sizeof(struct cadence_spi_platdata),
|
||||
.priv_auto_alloc_size = sizeof(struct cadence_spi_priv),
|
||||
.per_child_auto_alloc_size = sizeof(struct spi_slave),
|
||||
.probe = cadence_spi_probe,
|
||||
};
|
||||
76
drivers/spi/cadence_qspi.h
Normal file
76
drivers/spi/cadence_qspi.h
Normal file
|
|
@ -0,0 +1,76 @@
|
|||
/*
|
||||
* Copyright (C) 2012
|
||||
* Altera Corporation <www.altera.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __CADENCE_QSPI_H__
|
||||
#define __CADENCE_QSPI_H__
|
||||
|
||||
#define CQSPI_IS_ADDR(cmd_len) (cmd_len > 1 ? 1 : 0)
|
||||
|
||||
#define CQSPI_NO_DECODER_MAX_CS 4
|
||||
#define CQSPI_DECODER_MAX_CS 16
|
||||
#define CQSPI_READ_CAPTURE_MAX_DELAY 16
|
||||
|
||||
struct cadence_spi_platdata {
|
||||
unsigned int max_hz;
|
||||
void *regbase;
|
||||
void *ahbbase;
|
||||
|
||||
u32 page_size;
|
||||
u32 block_size;
|
||||
u32 tshsl_ns;
|
||||
u32 tsd2d_ns;
|
||||
u32 tchsh_ns;
|
||||
u32 tslch_ns;
|
||||
};
|
||||
|
||||
struct cadence_spi_priv {
|
||||
void *regbase;
|
||||
void *ahbbase;
|
||||
size_t cmd_len;
|
||||
u8 cmd_buf[32];
|
||||
size_t data_len;
|
||||
|
||||
int qspi_is_init;
|
||||
unsigned int qspi_calibrated_hz;
|
||||
unsigned int qspi_calibrated_cs;
|
||||
};
|
||||
|
||||
/* Functions call declaration */
|
||||
void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat);
|
||||
void cadence_qspi_apb_controller_enable(void *reg_base_addr);
|
||||
void cadence_qspi_apb_controller_disable(void *reg_base_addr);
|
||||
|
||||
int cadence_qspi_apb_command_read(void *reg_base_addr,
|
||||
unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen, u8 *rxbuf);
|
||||
int cadence_qspi_apb_command_write(void *reg_base_addr,
|
||||
unsigned int cmdlen, const u8 *cmdbuf,
|
||||
unsigned int txlen, const u8 *txbuf);
|
||||
|
||||
int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
|
||||
unsigned int cmdlen, const u8 *cmdbuf);
|
||||
int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
|
||||
unsigned int rxlen, u8 *rxbuf);
|
||||
int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
|
||||
unsigned int cmdlen, const u8 *cmdbuf);
|
||||
int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
|
||||
unsigned int txlen, const u8 *txbuf);
|
||||
|
||||
void cadence_qspi_apb_chipselect(void *reg_base,
|
||||
unsigned int chip_select, unsigned int decoder_enable);
|
||||
void cadence_qspi_apb_set_clk_mode(void *reg_base_addr,
|
||||
unsigned int clk_pol, unsigned int clk_pha);
|
||||
void cadence_qspi_apb_config_baudrate_div(void *reg_base,
|
||||
unsigned int ref_clk_hz, unsigned int sclk_hz);
|
||||
void cadence_qspi_apb_delay(void *reg_base,
|
||||
unsigned int ref_clk, unsigned int sclk_hz,
|
||||
unsigned int tshsl_ns, unsigned int tsd2d_ns,
|
||||
unsigned int tchsh_ns, unsigned int tslch_ns);
|
||||
void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy);
|
||||
void cadence_qspi_apb_readdata_capture(void *reg_base,
|
||||
unsigned int bypass, unsigned int delay);
|
||||
|
||||
#endif /* __CADENCE_QSPI_H__ */
|
||||
898
drivers/spi/cadence_qspi_apb.c
Normal file
898
drivers/spi/cadence_qspi_apb.c
Normal file
|
|
@ -0,0 +1,898 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Altera Corporation <www.altera.com>
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* - Neither the name of the Altera Corporation nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/errno.h>
|
||||
#include "cadence_qspi.h"
|
||||
|
||||
#define CQSPI_REG_POLL_US (1) /* 1us */
|
||||
#define CQSPI_REG_RETRY (10000)
|
||||
#define CQSPI_POLL_IDLE_RETRY (3)
|
||||
|
||||
#define CQSPI_FIFO_WIDTH (4)
|
||||
|
||||
/* Controller sram size in word */
|
||||
#define CQSPI_REG_SRAM_SIZE_WORD (128)
|
||||
#define CQSPI_REG_SRAM_RESV_WORDS (2)
|
||||
#define CQSPI_REG_SRAM_PARTITION_WR (1)
|
||||
#define CQSPI_REG_SRAM_PARTITION_RD \
|
||||
(CQSPI_REG_SRAM_SIZE_WORD - CQSPI_REG_SRAM_RESV_WORDS)
|
||||
#define CQSPI_REG_SRAM_THRESHOLD_WORDS (50)
|
||||
|
||||
/* Transfer mode */
|
||||
#define CQSPI_INST_TYPE_SINGLE (0)
|
||||
#define CQSPI_INST_TYPE_DUAL (1)
|
||||
#define CQSPI_INST_TYPE_QUAD (2)
|
||||
|
||||
#define CQSPI_STIG_DATA_LEN_MAX (8)
|
||||
#define CQSPI_INDIRECTTRIGGER_ADDR_MASK (0xFFFFF)
|
||||
|
||||
#define CQSPI_DUMMY_CLKS_PER_BYTE (8)
|
||||
#define CQSPI_DUMMY_BYTES_MAX (4)
|
||||
|
||||
|
||||
#define CQSPI_REG_SRAM_FILL_THRESHOLD \
|
||||
((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH)
|
||||
/****************************************************************************
|
||||
* Controller's configuration and status register (offset from QSPI_BASE)
|
||||
****************************************************************************/
|
||||
#define CQSPI_REG_CONFIG 0x00
|
||||
#define CQSPI_REG_CONFIG_CLK_POL_LSB 1
|
||||
#define CQSPI_REG_CONFIG_CLK_PHA_LSB 2
|
||||
#define CQSPI_REG_CONFIG_ENABLE_MASK (1 << 0)
|
||||
#define CQSPI_REG_CONFIG_DIRECT_MASK (1 << 7)
|
||||
#define CQSPI_REG_CONFIG_DECODE_MASK (1 << 9)
|
||||
#define CQSPI_REG_CONFIG_XIP_IMM_MASK (1 << 18)
|
||||
#define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
|
||||
#define CQSPI_REG_CONFIG_BAUD_LSB 19
|
||||
#define CQSPI_REG_CONFIG_IDLE_LSB 31
|
||||
#define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF
|
||||
#define CQSPI_REG_CONFIG_BAUD_MASK 0xF
|
||||
|
||||
#define CQSPI_REG_RD_INSTR 0x04
|
||||
#define CQSPI_REG_RD_INSTR_OPCODE_LSB 0
|
||||
#define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8
|
||||
#define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12
|
||||
#define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16
|
||||
#define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20
|
||||
#define CQSPI_REG_RD_INSTR_DUMMY_LSB 24
|
||||
#define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3
|
||||
#define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3
|
||||
#define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3
|
||||
#define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F
|
||||
|
||||
#define CQSPI_REG_WR_INSTR 0x08
|
||||
#define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
|
||||
|
||||
#define CQSPI_REG_DELAY 0x0C
|
||||
#define CQSPI_REG_DELAY_TSLCH_LSB 0
|
||||
#define CQSPI_REG_DELAY_TCHSH_LSB 8
|
||||
#define CQSPI_REG_DELAY_TSD2D_LSB 16
|
||||
#define CQSPI_REG_DELAY_TSHSL_LSB 24
|
||||
#define CQSPI_REG_DELAY_TSLCH_MASK 0xFF
|
||||
#define CQSPI_REG_DELAY_TCHSH_MASK 0xFF
|
||||
#define CQSPI_REG_DELAY_TSD2D_MASK 0xFF
|
||||
#define CQSPI_REG_DELAY_TSHSL_MASK 0xFF
|
||||
|
||||
#define CQSPI_READLCAPTURE 0x10
|
||||
#define CQSPI_READLCAPTURE_BYPASS_LSB 0
|
||||
#define CQSPI_READLCAPTURE_DELAY_LSB 1
|
||||
#define CQSPI_READLCAPTURE_DELAY_MASK 0xF
|
||||
|
||||
#define CQSPI_REG_SIZE 0x14
|
||||
#define CQSPI_REG_SIZE_ADDRESS_LSB 0
|
||||
#define CQSPI_REG_SIZE_PAGE_LSB 4
|
||||
#define CQSPI_REG_SIZE_BLOCK_LSB 16
|
||||
#define CQSPI_REG_SIZE_ADDRESS_MASK 0xF
|
||||
#define CQSPI_REG_SIZE_PAGE_MASK 0xFFF
|
||||
#define CQSPI_REG_SIZE_BLOCK_MASK 0x3F
|
||||
|
||||
#define CQSPI_REG_SRAMPARTITION 0x18
|
||||
#define CQSPI_REG_INDIRECTTRIGGER 0x1C
|
||||
|
||||
#define CQSPI_REG_REMAP 0x24
|
||||
#define CQSPI_REG_MODE_BIT 0x28
|
||||
|
||||
#define CQSPI_REG_SDRAMLEVEL 0x2C
|
||||
#define CQSPI_REG_SDRAMLEVEL_RD_LSB 0
|
||||
#define CQSPI_REG_SDRAMLEVEL_WR_LSB 16
|
||||
#define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF
|
||||
#define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF
|
||||
|
||||
#define CQSPI_REG_IRQSTATUS 0x40
|
||||
#define CQSPI_REG_IRQMASK 0x44
|
||||
|
||||
#define CQSPI_REG_INDIRECTRD 0x60
|
||||
#define CQSPI_REG_INDIRECTRD_START_MASK (1 << 0)
|
||||
#define CQSPI_REG_INDIRECTRD_CANCEL_MASK (1 << 1)
|
||||
#define CQSPI_REG_INDIRECTRD_INPROGRESS_MASK (1 << 2)
|
||||
#define CQSPI_REG_INDIRECTRD_DONE_MASK (1 << 5)
|
||||
|
||||
#define CQSPI_REG_INDIRECTRDWATERMARK 0x64
|
||||
#define CQSPI_REG_INDIRECTRDSTARTADDR 0x68
|
||||
#define CQSPI_REG_INDIRECTRDBYTES 0x6C
|
||||
|
||||
#define CQSPI_REG_CMDCTRL 0x90
|
||||
#define CQSPI_REG_CMDCTRL_EXECUTE_MASK (1 << 0)
|
||||
#define CQSPI_REG_CMDCTRL_INPROGRESS_MASK (1 << 1)
|
||||
#define CQSPI_REG_CMDCTRL_DUMMY_LSB 7
|
||||
#define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12
|
||||
#define CQSPI_REG_CMDCTRL_WR_EN_LSB 15
|
||||
#define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16
|
||||
#define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19
|
||||
#define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20
|
||||
#define CQSPI_REG_CMDCTRL_RD_EN_LSB 23
|
||||
#define CQSPI_REG_CMDCTRL_OPCODE_LSB 24
|
||||
#define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F
|
||||
#define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7
|
||||
#define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3
|
||||
#define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7
|
||||
#define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF
|
||||
|
||||
#define CQSPI_REG_INDIRECTWR 0x70
|
||||
#define CQSPI_REG_INDIRECTWR_START_MASK (1 << 0)
|
||||
#define CQSPI_REG_INDIRECTWR_CANCEL_MASK (1 << 1)
|
||||
#define CQSPI_REG_INDIRECTWR_INPROGRESS_MASK (1 << 2)
|
||||
#define CQSPI_REG_INDIRECTWR_DONE_MASK (1 << 5)
|
||||
|
||||
#define CQSPI_REG_INDIRECTWRWATERMARK 0x74
|
||||
#define CQSPI_REG_INDIRECTWRSTARTADDR 0x78
|
||||
#define CQSPI_REG_INDIRECTWRBYTES 0x7C
|
||||
|
||||
#define CQSPI_REG_CMDADDRESS 0x94
|
||||
#define CQSPI_REG_CMDREADDATALOWER 0xA0
|
||||
#define CQSPI_REG_CMDREADDATAUPPER 0xA4
|
||||
#define CQSPI_REG_CMDWRITEDATALOWER 0xA8
|
||||
#define CQSPI_REG_CMDWRITEDATAUPPER 0xAC
|
||||
|
||||
#define CQSPI_REG_IS_IDLE(base) \
|
||||
((readl(base + CQSPI_REG_CONFIG) >> \
|
||||
CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
|
||||
|
||||
#define CQSPI_CAL_DELAY(tdelay_ns, tref_ns, tsclk_ns) \
|
||||
((((tdelay_ns) - (tsclk_ns)) / (tref_ns)))
|
||||
|
||||
#define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \
|
||||
(((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
|
||||
CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK)
|
||||
|
||||
#define CQSPI_GET_WR_SRAM_LEVEL(reg_base) \
|
||||
(((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
|
||||
CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK)
|
||||
|
||||
static unsigned int cadence_qspi_apb_cmd2addr(const unsigned char *addr_buf,
|
||||
unsigned int addr_width)
|
||||
{
|
||||
unsigned int addr;
|
||||
|
||||
addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2];
|
||||
|
||||
if (addr_width == 4)
|
||||
addr = (addr << 8) | addr_buf[3];
|
||||
|
||||
return addr;
|
||||
}
|
||||
|
||||
static void cadence_qspi_apb_read_fifo_data(void *dest,
|
||||
const void *src_ahb_addr, unsigned int bytes)
|
||||
{
|
||||
unsigned int temp;
|
||||
int remaining = bytes;
|
||||
unsigned int *dest_ptr = (unsigned int *)dest;
|
||||
unsigned int *src_ptr = (unsigned int *)src_ahb_addr;
|
||||
|
||||
while (remaining > 0) {
|
||||
if (remaining >= CQSPI_FIFO_WIDTH) {
|
||||
*dest_ptr = readl(src_ptr);
|
||||
remaining -= CQSPI_FIFO_WIDTH;
|
||||
} else {
|
||||
/* dangling bytes */
|
||||
temp = readl(src_ptr);
|
||||
memcpy(dest_ptr, &temp, remaining);
|
||||
break;
|
||||
}
|
||||
dest_ptr++;
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static void cadence_qspi_apb_write_fifo_data(const void *dest_ahb_addr,
|
||||
const void *src, unsigned int bytes)
|
||||
{
|
||||
unsigned int temp;
|
||||
int remaining = bytes;
|
||||
unsigned int *dest_ptr = (unsigned int *)dest_ahb_addr;
|
||||
unsigned int *src_ptr = (unsigned int *)src;
|
||||
|
||||
while (remaining > 0) {
|
||||
if (remaining >= CQSPI_FIFO_WIDTH) {
|
||||
writel(*src_ptr, dest_ptr);
|
||||
remaining -= sizeof(unsigned int);
|
||||
} else {
|
||||
/* dangling bytes */
|
||||
memcpy(&temp, src_ptr, remaining);
|
||||
writel(temp, dest_ptr);
|
||||
break;
|
||||
}
|
||||
src_ptr++;
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/* Read from SRAM FIFO with polling SRAM fill level. */
|
||||
static int qspi_read_sram_fifo_poll(const void *reg_base, void *dest_addr,
|
||||
const void *src_addr, unsigned int num_bytes)
|
||||
{
|
||||
unsigned int remaining = num_bytes;
|
||||
unsigned int retry;
|
||||
unsigned int sram_level = 0;
|
||||
unsigned char *dest = (unsigned char *)dest_addr;
|
||||
|
||||
while (remaining > 0) {
|
||||
retry = CQSPI_REG_RETRY;
|
||||
while (retry--) {
|
||||
sram_level = CQSPI_GET_RD_SRAM_LEVEL(reg_base);
|
||||
if (sram_level)
|
||||
break;
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
if (!retry) {
|
||||
printf("QSPI: No receive data after polling for %d times\n",
|
||||
CQSPI_REG_RETRY);
|
||||
return -1;
|
||||
}
|
||||
|
||||
sram_level *= CQSPI_FIFO_WIDTH;
|
||||
sram_level = sram_level > remaining ? remaining : sram_level;
|
||||
|
||||
/* Read data from FIFO. */
|
||||
cadence_qspi_apb_read_fifo_data(dest, src_addr, sram_level);
|
||||
dest += sram_level;
|
||||
remaining -= sram_level;
|
||||
udelay(1);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Write to SRAM FIFO with polling SRAM fill level. */
|
||||
static int qpsi_write_sram_fifo_push(struct cadence_spi_platdata *plat,
|
||||
const void *src_addr, unsigned int num_bytes)
|
||||
{
|
||||
const void *reg_base = plat->regbase;
|
||||
void *dest_addr = plat->ahbbase;
|
||||
unsigned int retry = CQSPI_REG_RETRY;
|
||||
unsigned int sram_level;
|
||||
unsigned int wr_bytes;
|
||||
unsigned char *src = (unsigned char *)src_addr;
|
||||
int remaining = num_bytes;
|
||||
unsigned int page_size = plat->page_size;
|
||||
unsigned int sram_threshold_words = CQSPI_REG_SRAM_THRESHOLD_WORDS;
|
||||
|
||||
while (remaining > 0) {
|
||||
retry = CQSPI_REG_RETRY;
|
||||
while (retry--) {
|
||||
sram_level = CQSPI_GET_WR_SRAM_LEVEL(reg_base);
|
||||
if (sram_level <= sram_threshold_words)
|
||||
break;
|
||||
}
|
||||
if (!retry) {
|
||||
printf("QSPI: SRAM fill level (0x%08x) not hit lower expected level (0x%08x)",
|
||||
sram_level, sram_threshold_words);
|
||||
return -1;
|
||||
}
|
||||
/* Write a page or remaining bytes. */
|
||||
wr_bytes = (remaining > page_size) ?
|
||||
page_size : remaining;
|
||||
|
||||
cadence_qspi_apb_write_fifo_data(dest_addr, src, wr_bytes);
|
||||
src += wr_bytes;
|
||||
remaining -= wr_bytes;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void cadence_qspi_apb_controller_enable(void *reg_base)
|
||||
{
|
||||
unsigned int reg;
|
||||
reg = readl(reg_base + CQSPI_REG_CONFIG);
|
||||
reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
|
||||
writel(reg, reg_base + CQSPI_REG_CONFIG);
|
||||
return;
|
||||
}
|
||||
|
||||
void cadence_qspi_apb_controller_disable(void *reg_base)
|
||||
{
|
||||
unsigned int reg;
|
||||
reg = readl(reg_base + CQSPI_REG_CONFIG);
|
||||
reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
|
||||
writel(reg, reg_base + CQSPI_REG_CONFIG);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Return 1 if idle, otherwise return 0 (busy). */
|
||||
static unsigned int cadence_qspi_wait_idle(void *reg_base)
|
||||
{
|
||||
unsigned int start, count = 0;
|
||||
/* timeout in unit of ms */
|
||||
unsigned int timeout = 5000;
|
||||
|
||||
start = get_timer(0);
|
||||
for ( ; get_timer(start) < timeout ; ) {
|
||||
if (CQSPI_REG_IS_IDLE(reg_base))
|
||||
count++;
|
||||
else
|
||||
count = 0;
|
||||
/*
|
||||
* Ensure the QSPI controller is in true idle state after
|
||||
* reading back the same idle status consecutively
|
||||
*/
|
||||
if (count >= CQSPI_POLL_IDLE_RETRY)
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Timeout, still in busy mode. */
|
||||
printf("QSPI: QSPI is still busy after poll for %d times.\n",
|
||||
CQSPI_REG_RETRY);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void cadence_qspi_apb_readdata_capture(void *reg_base,
|
||||
unsigned int bypass, unsigned int delay)
|
||||
{
|
||||
unsigned int reg;
|
||||
cadence_qspi_apb_controller_disable(reg_base);
|
||||
|
||||
reg = readl(reg_base + CQSPI_READLCAPTURE);
|
||||
|
||||
if (bypass)
|
||||
reg |= (1 << CQSPI_READLCAPTURE_BYPASS_LSB);
|
||||
else
|
||||
reg &= ~(1 << CQSPI_READLCAPTURE_BYPASS_LSB);
|
||||
|
||||
reg &= ~(CQSPI_READLCAPTURE_DELAY_MASK
|
||||
<< CQSPI_READLCAPTURE_DELAY_LSB);
|
||||
|
||||
reg |= ((delay & CQSPI_READLCAPTURE_DELAY_MASK)
|
||||
<< CQSPI_READLCAPTURE_DELAY_LSB);
|
||||
|
||||
writel(reg, reg_base + CQSPI_READLCAPTURE);
|
||||
|
||||
cadence_qspi_apb_controller_enable(reg_base);
|
||||
return;
|
||||
}
|
||||
|
||||
void cadence_qspi_apb_config_baudrate_div(void *reg_base,
|
||||
unsigned int ref_clk_hz, unsigned int sclk_hz)
|
||||
{
|
||||
unsigned int reg;
|
||||
unsigned int div;
|
||||
|
||||
cadence_qspi_apb_controller_disable(reg_base);
|
||||
reg = readl(reg_base + CQSPI_REG_CONFIG);
|
||||
reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
|
||||
|
||||
div = ref_clk_hz / sclk_hz;
|
||||
|
||||
if (div > 32)
|
||||
div = 32;
|
||||
|
||||
/* Check if even number. */
|
||||
if ((div & 1)) {
|
||||
div = (div / 2);
|
||||
} else {
|
||||
if (ref_clk_hz % sclk_hz)
|
||||
/* ensure generated SCLK doesn't exceed user
|
||||
specified sclk_hz */
|
||||
div = (div / 2);
|
||||
else
|
||||
div = (div / 2) - 1;
|
||||
}
|
||||
|
||||
debug("%s: ref_clk %dHz sclk %dHz Div 0x%x\n", __func__,
|
||||
ref_clk_hz, sclk_hz, div);
|
||||
|
||||
div = (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
|
||||
reg |= div;
|
||||
writel(reg, reg_base + CQSPI_REG_CONFIG);
|
||||
|
||||
cadence_qspi_apb_controller_enable(reg_base);
|
||||
return;
|
||||
}
|
||||
|
||||
void cadence_qspi_apb_set_clk_mode(void *reg_base,
|
||||
unsigned int clk_pol, unsigned int clk_pha)
|
||||
{
|
||||
unsigned int reg;
|
||||
|
||||
cadence_qspi_apb_controller_disable(reg_base);
|
||||
reg = readl(reg_base + CQSPI_REG_CONFIG);
|
||||
reg &= ~(1 <<
|
||||
(CQSPI_REG_CONFIG_CLK_POL_LSB | CQSPI_REG_CONFIG_CLK_PHA_LSB));
|
||||
|
||||
reg |= ((clk_pol & 0x1) << CQSPI_REG_CONFIG_CLK_POL_LSB);
|
||||
reg |= ((clk_pha & 0x1) << CQSPI_REG_CONFIG_CLK_PHA_LSB);
|
||||
|
||||
writel(reg, reg_base + CQSPI_REG_CONFIG);
|
||||
|
||||
cadence_qspi_apb_controller_enable(reg_base);
|
||||
return;
|
||||
}
|
||||
|
||||
void cadence_qspi_apb_chipselect(void *reg_base,
|
||||
unsigned int chip_select, unsigned int decoder_enable)
|
||||
{
|
||||
unsigned int reg;
|
||||
|
||||
cadence_qspi_apb_controller_disable(reg_base);
|
||||
|
||||
debug("%s : chipselect %d decode %d\n", __func__, chip_select,
|
||||
decoder_enable);
|
||||
|
||||
reg = readl(reg_base + CQSPI_REG_CONFIG);
|
||||
/* docoder */
|
||||
if (decoder_enable) {
|
||||
reg |= CQSPI_REG_CONFIG_DECODE_MASK;
|
||||
} else {
|
||||
reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
|
||||
/* Convert CS if without decoder.
|
||||
* CS0 to 4b'1110
|
||||
* CS1 to 4b'1101
|
||||
* CS2 to 4b'1011
|
||||
* CS3 to 4b'0111
|
||||
*/
|
||||
chip_select = 0xF & ~(1 << chip_select);
|
||||
}
|
||||
|
||||
reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
|
||||
<< CQSPI_REG_CONFIG_CHIPSELECT_LSB);
|
||||
reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
|
||||
<< CQSPI_REG_CONFIG_CHIPSELECT_LSB;
|
||||
writel(reg, reg_base + CQSPI_REG_CONFIG);
|
||||
|
||||
cadence_qspi_apb_controller_enable(reg_base);
|
||||
return;
|
||||
}
|
||||
|
||||
void cadence_qspi_apb_delay(void *reg_base,
|
||||
unsigned int ref_clk, unsigned int sclk_hz,
|
||||
unsigned int tshsl_ns, unsigned int tsd2d_ns,
|
||||
unsigned int tchsh_ns, unsigned int tslch_ns)
|
||||
{
|
||||
unsigned int ref_clk_ns;
|
||||
unsigned int sclk_ns;
|
||||
unsigned int tshsl, tchsh, tslch, tsd2d;
|
||||
unsigned int reg;
|
||||
|
||||
cadence_qspi_apb_controller_disable(reg_base);
|
||||
|
||||
/* Convert to ns. */
|
||||
ref_clk_ns = (1000000000) / ref_clk;
|
||||
|
||||
/* Convert to ns. */
|
||||
sclk_ns = (1000000000) / sclk_hz;
|
||||
|
||||
/* Plus 1 to round up 1 clock cycle. */
|
||||
tshsl = CQSPI_CAL_DELAY(tshsl_ns, ref_clk_ns, sclk_ns) + 1;
|
||||
tchsh = CQSPI_CAL_DELAY(tchsh_ns, ref_clk_ns, sclk_ns) + 1;
|
||||
tslch = CQSPI_CAL_DELAY(tslch_ns, ref_clk_ns, sclk_ns) + 1;
|
||||
tsd2d = CQSPI_CAL_DELAY(tsd2d_ns, ref_clk_ns, sclk_ns) + 1;
|
||||
|
||||
reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
|
||||
<< CQSPI_REG_DELAY_TSHSL_LSB);
|
||||
reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
|
||||
<< CQSPI_REG_DELAY_TCHSH_LSB);
|
||||
reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK)
|
||||
<< CQSPI_REG_DELAY_TSLCH_LSB);
|
||||
reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
|
||||
<< CQSPI_REG_DELAY_TSD2D_LSB);
|
||||
writel(reg, reg_base + CQSPI_REG_DELAY);
|
||||
|
||||
cadence_qspi_apb_controller_enable(reg_base);
|
||||
return;
|
||||
}
|
||||
|
||||
void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
|
||||
{
|
||||
unsigned reg;
|
||||
|
||||
cadence_qspi_apb_controller_disable(plat->regbase);
|
||||
|
||||
/* Configure the device size and address bytes */
|
||||
reg = readl(plat->regbase + CQSPI_REG_SIZE);
|
||||
/* Clear the previous value */
|
||||
reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
|
||||
reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
|
||||
reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB);
|
||||
reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB);
|
||||
writel(reg, plat->regbase + CQSPI_REG_SIZE);
|
||||
|
||||
/* Configure the remap address register, no remap */
|
||||
writel(0, plat->regbase + CQSPI_REG_REMAP);
|
||||
|
||||
/* Disable all interrupts */
|
||||
writel(0, plat->regbase + CQSPI_REG_IRQMASK);
|
||||
|
||||
cadence_qspi_apb_controller_enable(plat->regbase);
|
||||
return;
|
||||
}
|
||||
|
||||
static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,
|
||||
unsigned int reg)
|
||||
{
|
||||
unsigned int retry = CQSPI_REG_RETRY;
|
||||
|
||||
/* Write the CMDCTRL without start execution. */
|
||||
writel(reg, reg_base + CQSPI_REG_CMDCTRL);
|
||||
/* Start execute */
|
||||
reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
|
||||
writel(reg, reg_base + CQSPI_REG_CMDCTRL);
|
||||
|
||||
while (retry--) {
|
||||
reg = readl(reg_base + CQSPI_REG_CMDCTRL);
|
||||
if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS_MASK) == 0)
|
||||
break;
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
if (!retry) {
|
||||
printf("QSPI: flash command execution timeout\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
/* Polling QSPI idle status. */
|
||||
if (!cadence_qspi_wait_idle(reg_base))
|
||||
return -EIO;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* For command RDID, RDSR. */
|
||||
int cadence_qspi_apb_command_read(void *reg_base,
|
||||
unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen,
|
||||
u8 *rxbuf)
|
||||
{
|
||||
unsigned int reg;
|
||||
unsigned int read_len;
|
||||
int status;
|
||||
|
||||
if (!cmdlen || rxlen > CQSPI_STIG_DATA_LEN_MAX || rxbuf == NULL) {
|
||||
printf("QSPI: Invalid input arguments cmdlen %d rxlen %d\n",
|
||||
cmdlen, rxlen);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
reg = cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
|
||||
|
||||
reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
|
||||
|
||||
/* 0 means 1 byte. */
|
||||
reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
|
||||
<< CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
|
||||
status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
|
||||
if (status != 0)
|
||||
return status;
|
||||
|
||||
reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
|
||||
|
||||
/* Put the read value into rx_buf */
|
||||
read_len = (rxlen > 4) ? 4 : rxlen;
|
||||
memcpy(rxbuf, ®, read_len);
|
||||
rxbuf += read_len;
|
||||
|
||||
if (rxlen > 4) {
|
||||
reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
|
||||
|
||||
read_len = rxlen - read_len;
|
||||
memcpy(rxbuf, ®, read_len);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */
|
||||
int cadence_qspi_apb_command_write(void *reg_base, unsigned int cmdlen,
|
||||
const u8 *cmdbuf, unsigned int txlen, const u8 *txbuf)
|
||||
{
|
||||
unsigned int reg = 0;
|
||||
unsigned int addr_value;
|
||||
unsigned int wr_data;
|
||||
unsigned int wr_len;
|
||||
|
||||
if (!cmdlen || cmdlen > 5 || txlen > 8 || cmdbuf == NULL) {
|
||||
printf("QSPI: Invalid input arguments cmdlen %d txlen %d\n",
|
||||
cmdlen, txlen);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
reg |= cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
|
||||
|
||||
if (cmdlen == 4 || cmdlen == 5) {
|
||||
/* Command with address */
|
||||
reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
|
||||
/* Number of bytes to write. */
|
||||
reg |= ((cmdlen - 2) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
|
||||
<< CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
|
||||
/* Get address */
|
||||
addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1],
|
||||
cmdlen >= 5 ? 4 : 3);
|
||||
|
||||
writel(addr_value, reg_base + CQSPI_REG_CMDADDRESS);
|
||||
}
|
||||
|
||||
if (txlen) {
|
||||
/* writing data = yes */
|
||||
reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
|
||||
reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
|
||||
<< CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
|
||||
|
||||
wr_len = txlen > 4 ? 4 : txlen;
|
||||
memcpy(&wr_data, txbuf, wr_len);
|
||||
writel(wr_data, reg_base +
|
||||
CQSPI_REG_CMDWRITEDATALOWER);
|
||||
|
||||
if (txlen > 4) {
|
||||
txbuf += wr_len;
|
||||
wr_len = txlen - wr_len;
|
||||
memcpy(&wr_data, txbuf, wr_len);
|
||||
writel(wr_data, reg_base +
|
||||
CQSPI_REG_CMDWRITEDATAUPPER);
|
||||
}
|
||||
}
|
||||
|
||||
/* Execute the command */
|
||||
return cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
|
||||
}
|
||||
|
||||
/* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */
|
||||
int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
|
||||
unsigned int cmdlen, const u8 *cmdbuf)
|
||||
{
|
||||
unsigned int reg;
|
||||
unsigned int rd_reg;
|
||||
unsigned int addr_value;
|
||||
unsigned int dummy_clk;
|
||||
unsigned int dummy_bytes;
|
||||
unsigned int addr_bytes;
|
||||
|
||||
/*
|
||||
* Identify addr_byte. All NOR flash device drivers are using fast read
|
||||
* which always expecting 1 dummy byte, 1 cmd byte and 3/4 addr byte.
|
||||
* With that, the length is in value of 5 or 6. Only FRAM chip from
|
||||
* ramtron using normal read (which won't need dummy byte).
|
||||
* Unlikely NOR flash using normal read due to performance issue.
|
||||
*/
|
||||
if (cmdlen >= 5)
|
||||
/* to cater fast read where cmd + addr + dummy */
|
||||
addr_bytes = cmdlen - 2;
|
||||
else
|
||||
/* for normal read (only ramtron as of now) */
|
||||
addr_bytes = cmdlen - 1;
|
||||
|
||||
/* Setup the indirect trigger address */
|
||||
writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
|
||||
plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
|
||||
|
||||
/* Configure SRAM partition for read. */
|
||||
writel(CQSPI_REG_SRAM_PARTITION_RD, plat->regbase +
|
||||
CQSPI_REG_SRAMPARTITION);
|
||||
|
||||
/* Configure the opcode */
|
||||
rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB;
|
||||
|
||||
#if (CONFIG_SPI_FLASH_QUAD == 1)
|
||||
/* Instruction and address at DQ0, data at DQ0-3. */
|
||||
rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
|
||||
#endif
|
||||
|
||||
/* Get address */
|
||||
addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
|
||||
writel(addr_value, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
|
||||
|
||||
/* The remaining lenght is dummy bytes. */
|
||||
dummy_bytes = cmdlen - addr_bytes - 1;
|
||||
if (dummy_bytes) {
|
||||
if (dummy_bytes > CQSPI_DUMMY_BYTES_MAX)
|
||||
dummy_bytes = CQSPI_DUMMY_BYTES_MAX;
|
||||
|
||||
rd_reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
|
||||
#if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD)
|
||||
writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);
|
||||
#else
|
||||
writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);
|
||||
#endif
|
||||
|
||||
/* Convert to clock cycles. */
|
||||
dummy_clk = dummy_bytes * CQSPI_DUMMY_CLKS_PER_BYTE;
|
||||
/* Need to minus the mode byte (8 clocks). */
|
||||
dummy_clk -= CQSPI_DUMMY_CLKS_PER_BYTE;
|
||||
|
||||
if (dummy_clk)
|
||||
rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
|
||||
<< CQSPI_REG_RD_INSTR_DUMMY_LSB;
|
||||
}
|
||||
|
||||
writel(rd_reg, plat->regbase + CQSPI_REG_RD_INSTR);
|
||||
|
||||
/* set device size */
|
||||
reg = readl(plat->regbase + CQSPI_REG_SIZE);
|
||||
reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
|
||||
reg |= (addr_bytes - 1);
|
||||
writel(reg, plat->regbase + CQSPI_REG_SIZE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
|
||||
unsigned int rxlen, u8 *rxbuf)
|
||||
{
|
||||
unsigned int reg;
|
||||
|
||||
writel(rxlen, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
|
||||
|
||||
/* Start the indirect read transfer */
|
||||
writel(CQSPI_REG_INDIRECTRD_START_MASK,
|
||||
plat->regbase + CQSPI_REG_INDIRECTRD);
|
||||
|
||||
if (qspi_read_sram_fifo_poll(plat->regbase, (void *)rxbuf,
|
||||
(const void *)plat->ahbbase, rxlen))
|
||||
goto failrd;
|
||||
|
||||
/* Check flash indirect controller */
|
||||
reg = readl(plat->regbase + CQSPI_REG_INDIRECTRD);
|
||||
if (!(reg & CQSPI_REG_INDIRECTRD_DONE_MASK)) {
|
||||
reg = readl(plat->regbase + CQSPI_REG_INDIRECTRD);
|
||||
printf("QSPI: indirect completion status error with reg 0x%08x\n",
|
||||
reg);
|
||||
goto failrd;
|
||||
}
|
||||
|
||||
/* Clear indirect completion status */
|
||||
writel(CQSPI_REG_INDIRECTRD_DONE_MASK,
|
||||
plat->regbase + CQSPI_REG_INDIRECTRD);
|
||||
return 0;
|
||||
|
||||
failrd:
|
||||
/* Cancel the indirect read */
|
||||
writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK,
|
||||
plat->regbase + CQSPI_REG_INDIRECTRD);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Opcode + Address (3/4 bytes) */
|
||||
int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
|
||||
unsigned int cmdlen, const u8 *cmdbuf)
|
||||
{
|
||||
unsigned int reg;
|
||||
unsigned int addr_bytes = cmdlen > 4 ? 4 : 3;
|
||||
|
||||
if (cmdlen < 4 || cmdbuf == NULL) {
|
||||
printf("QSPI: iInvalid input argument, len %d cmdbuf 0x%08x\n",
|
||||
cmdlen, (unsigned int)cmdbuf);
|
||||
return -EINVAL;
|
||||
}
|
||||
/* Setup the indirect trigger address */
|
||||
writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
|
||||
plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
|
||||
|
||||
writel(CQSPI_REG_SRAM_PARTITION_WR,
|
||||
plat->regbase + CQSPI_REG_SRAMPARTITION);
|
||||
|
||||
/* Configure the opcode */
|
||||
reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
|
||||
writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
|
||||
|
||||
/* Setup write address. */
|
||||
reg = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
|
||||
writel(reg, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
|
||||
|
||||
reg = readl(plat->regbase + CQSPI_REG_SIZE);
|
||||
reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
|
||||
reg |= (addr_bytes - 1);
|
||||
writel(reg, plat->regbase + CQSPI_REG_SIZE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
|
||||
unsigned int txlen, const u8 *txbuf)
|
||||
{
|
||||
unsigned int reg = 0;
|
||||
unsigned int retry;
|
||||
|
||||
/* Configure the indirect read transfer bytes */
|
||||
writel(txlen, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
|
||||
|
||||
/* Start the indirect write transfer */
|
||||
writel(CQSPI_REG_INDIRECTWR_START_MASK,
|
||||
plat->regbase + CQSPI_REG_INDIRECTWR);
|
||||
|
||||
if (qpsi_write_sram_fifo_push(plat, (const void *)txbuf, txlen))
|
||||
goto failwr;
|
||||
|
||||
/* Wait until last write is completed (FIFO empty) */
|
||||
retry = CQSPI_REG_RETRY;
|
||||
while (retry--) {
|
||||
reg = CQSPI_GET_WR_SRAM_LEVEL(plat->regbase);
|
||||
if (reg == 0)
|
||||
break;
|
||||
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
if (reg != 0) {
|
||||
printf("QSPI: timeout for indirect write\n");
|
||||
goto failwr;
|
||||
}
|
||||
|
||||
/* Check flash indirect controller status */
|
||||
retry = CQSPI_REG_RETRY;
|
||||
while (retry--) {
|
||||
reg = readl(plat->regbase + CQSPI_REG_INDIRECTWR);
|
||||
if (reg & CQSPI_REG_INDIRECTWR_DONE_MASK)
|
||||
break;
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
if (!(reg & CQSPI_REG_INDIRECTWR_DONE_MASK)) {
|
||||
printf("QSPI: indirect completion status error with reg 0x%08x\n",
|
||||
reg);
|
||||
goto failwr;
|
||||
}
|
||||
|
||||
/* Clear indirect completion status */
|
||||
writel(CQSPI_REG_INDIRECTWR_DONE_MASK,
|
||||
plat->regbase + CQSPI_REG_INDIRECTWR);
|
||||
return 0;
|
||||
|
||||
failwr:
|
||||
/* Cancel the indirect write */
|
||||
writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
|
||||
plat->regbase + CQSPI_REG_INDIRECTWR);
|
||||
return -1;
|
||||
}
|
||||
|
||||
void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)
|
||||
{
|
||||
unsigned int reg;
|
||||
|
||||
/* enter XiP mode immediately and enable direct mode */
|
||||
reg = readl(reg_base + CQSPI_REG_CONFIG);
|
||||
reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
|
||||
reg |= CQSPI_REG_CONFIG_DIRECT_MASK;
|
||||
reg |= CQSPI_REG_CONFIG_XIP_IMM_MASK;
|
||||
writel(reg, reg_base + CQSPI_REG_CONFIG);
|
||||
|
||||
/* keep the XiP mode */
|
||||
writel(xip_dummy, reg_base + CQSPI_REG_MODE_BIT);
|
||||
|
||||
/* Enable mode bit at devrd */
|
||||
reg = readl(reg_base + CQSPI_REG_RD_INSTR);
|
||||
reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
|
||||
writel(reg, reg_base + CQSPI_REG_RD_INSTR);
|
||||
}
|
||||
426
drivers/spi/designware_spi.c
Normal file
426
drivers/spi/designware_spi.c
Normal file
|
|
@ -0,0 +1,426 @@
|
|||
/*
|
||||
* Designware master SPI core controller driver
|
||||
*
|
||||
* Copyright (C) 2014 Stefan Roese <sr@denx.de>
|
||||
*
|
||||
* Very loosely based on the Linux driver:
|
||||
* drivers/spi/spi-dw.c, which is:
|
||||
* Copyright (c) 2009, Intel Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <errno.h>
|
||||
#include <malloc.h>
|
||||
#include <spi.h>
|
||||
#include <fdtdec.h>
|
||||
#include <linux/compat.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/clock_manager.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/* Register offsets */
|
||||
#define DW_SPI_CTRL0 0x00
|
||||
#define DW_SPI_CTRL1 0x04
|
||||
#define DW_SPI_SSIENR 0x08
|
||||
#define DW_SPI_MWCR 0x0c
|
||||
#define DW_SPI_SER 0x10
|
||||
#define DW_SPI_BAUDR 0x14
|
||||
#define DW_SPI_TXFLTR 0x18
|
||||
#define DW_SPI_RXFLTR 0x1c
|
||||
#define DW_SPI_TXFLR 0x20
|
||||
#define DW_SPI_RXFLR 0x24
|
||||
#define DW_SPI_SR 0x28
|
||||
#define DW_SPI_IMR 0x2c
|
||||
#define DW_SPI_ISR 0x30
|
||||
#define DW_SPI_RISR 0x34
|
||||
#define DW_SPI_TXOICR 0x38
|
||||
#define DW_SPI_RXOICR 0x3c
|
||||
#define DW_SPI_RXUICR 0x40
|
||||
#define DW_SPI_MSTICR 0x44
|
||||
#define DW_SPI_ICR 0x48
|
||||
#define DW_SPI_DMACR 0x4c
|
||||
#define DW_SPI_DMATDLR 0x50
|
||||
#define DW_SPI_DMARDLR 0x54
|
||||
#define DW_SPI_IDR 0x58
|
||||
#define DW_SPI_VERSION 0x5c
|
||||
#define DW_SPI_DR 0x60
|
||||
|
||||
/* Bit fields in CTRLR0 */
|
||||
#define SPI_DFS_OFFSET 0
|
||||
|
||||
#define SPI_FRF_OFFSET 4
|
||||
#define SPI_FRF_SPI 0x0
|
||||
#define SPI_FRF_SSP 0x1
|
||||
#define SPI_FRF_MICROWIRE 0x2
|
||||
#define SPI_FRF_RESV 0x3
|
||||
|
||||
#define SPI_MODE_OFFSET 6
|
||||
#define SPI_SCPH_OFFSET 6
|
||||
#define SPI_SCOL_OFFSET 7
|
||||
|
||||
#define SPI_TMOD_OFFSET 8
|
||||
#define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET)
|
||||
#define SPI_TMOD_TR 0x0 /* xmit & recv */
|
||||
#define SPI_TMOD_TO 0x1 /* xmit only */
|
||||
#define SPI_TMOD_RO 0x2 /* recv only */
|
||||
#define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
|
||||
|
||||
#define SPI_SLVOE_OFFSET 10
|
||||
#define SPI_SRL_OFFSET 11
|
||||
#define SPI_CFS_OFFSET 12
|
||||
|
||||
/* Bit fields in SR, 7 bits */
|
||||
#define SR_MASK 0x7f /* cover 7 bits */
|
||||
#define SR_BUSY (1 << 0)
|
||||
#define SR_TF_NOT_FULL (1 << 1)
|
||||
#define SR_TF_EMPT (1 << 2)
|
||||
#define SR_RF_NOT_EMPT (1 << 3)
|
||||
#define SR_RF_FULL (1 << 4)
|
||||
#define SR_TX_ERR (1 << 5)
|
||||
#define SR_DCOL (1 << 6)
|
||||
|
||||
#define RX_TIMEOUT 1000 /* timeout in ms */
|
||||
|
||||
struct dw_spi_platdata {
|
||||
s32 frequency; /* Default clock frequency, -1 for none */
|
||||
void __iomem *regs;
|
||||
};
|
||||
|
||||
struct dw_spi_priv {
|
||||
void __iomem *regs;
|
||||
unsigned int freq; /* Default frequency */
|
||||
unsigned int mode;
|
||||
|
||||
int bits_per_word;
|
||||
u8 cs; /* chip select pin */
|
||||
u8 tmode; /* TR/TO/RO/EEPROM */
|
||||
u8 type; /* SPI/SSP/MicroWire */
|
||||
int len;
|
||||
|
||||
u32 fifo_len; /* depth of the FIFO buffer */
|
||||
void *tx;
|
||||
void *tx_end;
|
||||
void *rx;
|
||||
void *rx_end;
|
||||
};
|
||||
|
||||
static inline u32 dw_readl(struct dw_spi_priv *priv, u32 offset)
|
||||
{
|
||||
return __raw_readl(priv->regs + offset);
|
||||
}
|
||||
|
||||
static inline void dw_writel(struct dw_spi_priv *priv, u32 offset, u32 val)
|
||||
{
|
||||
__raw_writel(val, priv->regs + offset);
|
||||
}
|
||||
|
||||
static inline u16 dw_readw(struct dw_spi_priv *priv, u32 offset)
|
||||
{
|
||||
return __raw_readw(priv->regs + offset);
|
||||
}
|
||||
|
||||
static inline void dw_writew(struct dw_spi_priv *priv, u32 offset, u16 val)
|
||||
{
|
||||
__raw_writew(val, priv->regs + offset);
|
||||
}
|
||||
|
||||
static int dw_spi_ofdata_to_platdata(struct udevice *bus)
|
||||
{
|
||||
struct dw_spi_platdata *plat = bus->platdata;
|
||||
const void *blob = gd->fdt_blob;
|
||||
int node = bus->of_offset;
|
||||
|
||||
plat->regs = (struct dw_spi *)fdtdec_get_addr(blob, node, "reg");
|
||||
|
||||
/* Use 500KHz as a suitable default */
|
||||
plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
|
||||
500000);
|
||||
debug("%s: regs=%p max-frequency=%d\n", __func__, plat->regs,
|
||||
plat->frequency);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void spi_enable_chip(struct dw_spi_priv *priv, int enable)
|
||||
{
|
||||
dw_writel(priv, DW_SPI_SSIENR, (enable ? 1 : 0));
|
||||
}
|
||||
|
||||
/* Restart the controller, disable all interrupts, clean rx fifo */
|
||||
static void spi_hw_init(struct dw_spi_priv *priv)
|
||||
{
|
||||
spi_enable_chip(priv, 0);
|
||||
dw_writel(priv, DW_SPI_IMR, 0xff);
|
||||
spi_enable_chip(priv, 1);
|
||||
|
||||
/*
|
||||
* Try to detect the FIFO depth if not set by interface driver,
|
||||
* the depth could be from 2 to 256 from HW spec
|
||||
*/
|
||||
if (!priv->fifo_len) {
|
||||
u32 fifo;
|
||||
|
||||
for (fifo = 2; fifo <= 257; fifo++) {
|
||||
dw_writew(priv, DW_SPI_TXFLTR, fifo);
|
||||
if (fifo != dw_readw(priv, DW_SPI_TXFLTR))
|
||||
break;
|
||||
}
|
||||
|
||||
priv->fifo_len = (fifo == 257) ? 0 : fifo;
|
||||
dw_writew(priv, DW_SPI_TXFLTR, 0);
|
||||
}
|
||||
debug("%s: fifo_len=%d\n", __func__, priv->fifo_len);
|
||||
}
|
||||
|
||||
static int dw_spi_probe(struct udevice *bus)
|
||||
{
|
||||
struct dw_spi_platdata *plat = dev_get_platdata(bus);
|
||||
struct dw_spi_priv *priv = dev_get_priv(bus);
|
||||
|
||||
priv->regs = plat->regs;
|
||||
priv->freq = plat->frequency;
|
||||
|
||||
/* Currently only bits_per_word == 8 supported */
|
||||
priv->bits_per_word = 8;
|
||||
|
||||
priv->tmode = 0; /* Tx & Rx */
|
||||
|
||||
/* Basic HW init */
|
||||
spi_hw_init(priv);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Return the max entries we can fill into tx fifo */
|
||||
static inline u32 tx_max(struct dw_spi_priv *priv)
|
||||
{
|
||||
u32 tx_left, tx_room, rxtx_gap;
|
||||
|
||||
tx_left = (priv->tx_end - priv->tx) / (priv->bits_per_word >> 3);
|
||||
tx_room = priv->fifo_len - dw_readw(priv, DW_SPI_TXFLR);
|
||||
|
||||
/*
|
||||
* Another concern is about the tx/rx mismatch, we
|
||||
* thought about using (priv->fifo_len - rxflr - txflr) as
|
||||
* one maximum value for tx, but it doesn't cover the
|
||||
* data which is out of tx/rx fifo and inside the
|
||||
* shift registers. So a control from sw point of
|
||||
* view is taken.
|
||||
*/
|
||||
rxtx_gap = ((priv->rx_end - priv->rx) - (priv->tx_end - priv->tx)) /
|
||||
(priv->bits_per_word >> 3);
|
||||
|
||||
return min3(tx_left, tx_room, (u32)(priv->fifo_len - rxtx_gap));
|
||||
}
|
||||
|
||||
/* Return the max entries we should read out of rx fifo */
|
||||
static inline u32 rx_max(struct dw_spi_priv *priv)
|
||||
{
|
||||
u32 rx_left = (priv->rx_end - priv->rx) / (priv->bits_per_word >> 3);
|
||||
|
||||
return min_t(u32, rx_left, dw_readw(priv, DW_SPI_RXFLR));
|
||||
}
|
||||
|
||||
static void dw_writer(struct dw_spi_priv *priv)
|
||||
{
|
||||
u32 max = tx_max(priv);
|
||||
u16 txw = 0;
|
||||
|
||||
while (max--) {
|
||||
/* Set the tx word if the transfer's original "tx" is not null */
|
||||
if (priv->tx_end - priv->len) {
|
||||
if (priv->bits_per_word == 8)
|
||||
txw = *(u8 *)(priv->tx);
|
||||
else
|
||||
txw = *(u16 *)(priv->tx);
|
||||
}
|
||||
dw_writew(priv, DW_SPI_DR, txw);
|
||||
debug("%s: tx=0x%02x\n", __func__, txw);
|
||||
priv->tx += priv->bits_per_word >> 3;
|
||||
}
|
||||
}
|
||||
|
||||
static int dw_reader(struct dw_spi_priv *priv)
|
||||
{
|
||||
unsigned start = get_timer(0);
|
||||
u32 max;
|
||||
u16 rxw;
|
||||
|
||||
/* Wait for rx data to be ready */
|
||||
while (rx_max(priv) == 0) {
|
||||
if (get_timer(start) > RX_TIMEOUT)
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
max = rx_max(priv);
|
||||
|
||||
while (max--) {
|
||||
rxw = dw_readw(priv, DW_SPI_DR);
|
||||
debug("%s: rx=0x%02x\n", __func__, rxw);
|
||||
|
||||
/*
|
||||
* Care about rx only if the transfer's original "rx" is
|
||||
* not null
|
||||
*/
|
||||
if (priv->rx_end - priv->len) {
|
||||
if (priv->bits_per_word == 8)
|
||||
*(u8 *)(priv->rx) = rxw;
|
||||
else
|
||||
*(u16 *)(priv->rx) = rxw;
|
||||
}
|
||||
priv->rx += priv->bits_per_word >> 3;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int poll_transfer(struct dw_spi_priv *priv)
|
||||
{
|
||||
int ret;
|
||||
|
||||
do {
|
||||
dw_writer(priv);
|
||||
ret = dw_reader(priv);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
} while (priv->rx_end > priv->rx);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
|
||||
const void *dout, void *din, unsigned long flags)
|
||||
{
|
||||
struct udevice *bus = dev->parent;
|
||||
struct dw_spi_priv *priv = dev_get_priv(bus);
|
||||
const u8 *tx = dout;
|
||||
u8 *rx = din;
|
||||
int ret = 0;
|
||||
u32 cr0 = 0;
|
||||
u32 cs;
|
||||
|
||||
/* spi core configured to do 8 bit transfers */
|
||||
if (bitlen % 8) {
|
||||
debug("Non byte aligned SPI transfer.\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
cr0 = (priv->bits_per_word - 1) | (priv->type << SPI_FRF_OFFSET) |
|
||||
(priv->mode << SPI_MODE_OFFSET) |
|
||||
(priv->tmode << SPI_TMOD_OFFSET);
|
||||
|
||||
if (rx && tx)
|
||||
priv->tmode = SPI_TMOD_TR;
|
||||
else if (rx)
|
||||
priv->tmode = SPI_TMOD_RO;
|
||||
else
|
||||
priv->tmode = SPI_TMOD_TO;
|
||||
|
||||
cr0 &= ~SPI_TMOD_MASK;
|
||||
cr0 |= (priv->tmode << SPI_TMOD_OFFSET);
|
||||
|
||||
priv->len = bitlen >> 3;
|
||||
debug("%s: rx=%p tx=%p len=%d [bytes]\n", __func__, rx, tx, priv->len);
|
||||
|
||||
priv->tx = (void *)tx;
|
||||
priv->tx_end = priv->tx + priv->len;
|
||||
priv->rx = rx;
|
||||
priv->rx_end = priv->rx + priv->len;
|
||||
|
||||
/* Disable controller before writing control registers */
|
||||
spi_enable_chip(priv, 0);
|
||||
|
||||
debug("%s: cr0=%08x\n", __func__, cr0);
|
||||
/* Reprogram cr0 only if changed */
|
||||
if (dw_readw(priv, DW_SPI_CTRL0) != cr0)
|
||||
dw_writew(priv, DW_SPI_CTRL0, cr0);
|
||||
|
||||
/*
|
||||
* Configure the desired SS (slave select 0...3) in the controller
|
||||
* The DW SPI controller will activate and deactivate this CS
|
||||
* automatically. So no cs_activate() etc is needed in this driver.
|
||||
*/
|
||||
cs = spi_chip_select(dev);
|
||||
dw_writel(priv, DW_SPI_SER, 1 << cs);
|
||||
|
||||
/* Enable controller after writing control registers */
|
||||
spi_enable_chip(priv, 1);
|
||||
|
||||
/* Start transfer in a polling loop */
|
||||
ret = poll_transfer(priv);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int dw_spi_set_speed(struct udevice *bus, uint speed)
|
||||
{
|
||||
struct dw_spi_platdata *plat = bus->platdata;
|
||||
struct dw_spi_priv *priv = dev_get_priv(bus);
|
||||
u16 clk_div;
|
||||
|
||||
if (speed > plat->frequency)
|
||||
speed = plat->frequency;
|
||||
|
||||
/* Disable controller before writing control registers */
|
||||
spi_enable_chip(priv, 0);
|
||||
|
||||
/* clk_div doesn't support odd number */
|
||||
clk_div = cm_get_spi_controller_clk_hz() / speed;
|
||||
clk_div = (clk_div + 1) & 0xfffe;
|
||||
dw_writel(priv, DW_SPI_BAUDR, clk_div);
|
||||
|
||||
/* Enable controller after writing control registers */
|
||||
spi_enable_chip(priv, 1);
|
||||
|
||||
priv->freq = speed;
|
||||
debug("%s: regs=%p speed=%d clk_div=%d\n", __func__, priv->regs,
|
||||
priv->freq, clk_div);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dw_spi_set_mode(struct udevice *bus, uint mode)
|
||||
{
|
||||
struct dw_spi_priv *priv = dev_get_priv(bus);
|
||||
|
||||
/*
|
||||
* Can't set mode yet. Since this depends on if rx, tx, or
|
||||
* rx & tx is requested. So we have to defer this to the
|
||||
* real transfer function.
|
||||
*/
|
||||
priv->mode = mode;
|
||||
debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dm_spi_ops dw_spi_ops = {
|
||||
.xfer = dw_spi_xfer,
|
||||
.set_speed = dw_spi_set_speed,
|
||||
.set_mode = dw_spi_set_mode,
|
||||
/*
|
||||
* cs_info is not needed, since we require all chip selects to be
|
||||
* in the device tree explicitly
|
||||
*/
|
||||
};
|
||||
|
||||
static const struct udevice_id dw_spi_ids[] = {
|
||||
{ .compatible = "snps,dw-spi-mmio" },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(dw_spi) = {
|
||||
.name = "dw_spi",
|
||||
.id = UCLASS_SPI,
|
||||
.of_match = dw_spi_ids,
|
||||
.ops = &dw_spi_ops,
|
||||
.ofdata_to_platdata = dw_spi_ofdata_to_platdata,
|
||||
.platdata_auto_alloc_size = sizeof(struct dw_spi_platdata),
|
||||
.priv_auto_alloc_size = sizeof(struct dw_spi_priv),
|
||||
.per_child_auto_alloc_size = sizeof(struct spi_slave),
|
||||
.probe = dw_spi_probe,
|
||||
};
|
||||
|
|
@ -159,7 +159,7 @@
|
|||
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
|
||||
#endif
|
||||
|
||||
/*
|
||||
/*
|
||||
* I2C support
|
||||
*/
|
||||
#define CONFIG_SYS_I2C
|
||||
|
|
@ -186,6 +186,37 @@ unsigned int cm_get_l4_sp_clk_hz(void);
|
|||
#endif
|
||||
#define CONFIG_CMD_I2C
|
||||
|
||||
/*
|
||||
* QSPI support
|
||||
*/
|
||||
#ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */
|
||||
#define CONFIG_CMD_DM
|
||||
#define CONFIG_DM
|
||||
#define CONFIG_DM_SPI
|
||||
#define CONFIG_DM_SPI_FLASH
|
||||
#define CONFIG_CADENCE_QSPI
|
||||
/* Enable multiple SPI NOR flash manufacturers */
|
||||
#define CONFIG_SPI_FLASH /* SPI flash subsystem */
|
||||
#define CONFIG_SPI_FLASH_STMICRO /* Micron/Numonyx flash */
|
||||
#define CONFIG_SPI_FLASH_SPANSION /* Spansion flash */
|
||||
#define CONFIG_SPI_FLASH_MTD
|
||||
/* QSPI reference clock */
|
||||
#ifndef __ASSEMBLY__
|
||||
unsigned int cm_get_qspi_controller_clk_hz(void);
|
||||
#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
|
||||
#endif
|
||||
#define CONFIG_CQSPI_DECODER 0
|
||||
#define CONFIG_CMD_SF
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_OF_CONTROL /* DW SPI is controlled via DT */
|
||||
#define CONFIG_CMD_DM
|
||||
#define CONFIG_DM
|
||||
#define CONFIG_DM_SPI
|
||||
#define CONFIG_DESIGNWARE_SPI
|
||||
#define CONFIG_CMD_SPI
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Serial Driver
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -1,14 +1,7 @@
|
|||
/*
|
||||
* Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de>
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H
|
||||
|
|
|
|||
Loading…
Reference in a new issue