mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 15:14:43 +00:00
Add support for Seagate BlackArmor NAS220
Add support for Seagate BlackArmor NAS220 Signed-off-by: Evgeni Dobrev <evgeni@studio-punkt.com>
This commit is contained in:
Evgeni Dobrev
Tom Rini
parent
4cf84ccbaf
commit
9637c4b2dd
8 changed files with 469 additions and 0 deletions
|
|
@ -57,6 +57,9 @@ config TARGET_DOCKSTAR
|
|||
config TARGET_GOFLEXHOME
|
||||
bool "GoFlex Home Board"
|
||||
|
||||
config TARGET_NAS220
|
||||
bool "BlackArmor NAS220"
|
||||
|
||||
endchoice
|
||||
|
||||
config SYS_SOC
|
||||
|
|
@ -80,5 +83,6 @@ source "board/LaCie/wireless_space/Kconfig"
|
|||
source "board/raidsonic/ib62x0/Kconfig"
|
||||
source "board/Seagate/dockstar/Kconfig"
|
||||
source "board/Seagate/goflexhome/Kconfig"
|
||||
source "board/Seagate/nas220/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
12
board/Seagate/nas220/Kconfig
Normal file
12
board/Seagate/nas220/Kconfig
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
if TARGET_NAS220
|
||||
|
||||
config SYS_BOARD
|
||||
default "nas220"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "Seagate"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "nas220"
|
||||
|
||||
endif
|
||||
6
board/Seagate/nas220/MAINTAINERS
Normal file
6
board/Seagate/nas220/MAINTAINERS
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
NAS220 BOARD
|
||||
M: Evgeni Dobrev <evgeni@studio-punkt.com>
|
||||
S: Maintained
|
||||
F: board/Seagate/nas220/
|
||||
F: include/configs/nas220.h
|
||||
F: configs/nas220_defconfig
|
||||
7
board/Seagate/nas220/Makefile
Normal file
7
board/Seagate/nas220/Makefile
Normal file
|
|
@ -0,0 +1,7 @@
|
|||
#
|
||||
# Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y := nas220.o
|
||||
151
board/Seagate/nas220/kwbimage.cfg
Normal file
151
board/Seagate/nas220/kwbimage.cfg
Normal file
|
|
@ -0,0 +1,151 @@
|
|||
#
|
||||
# Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com>
|
||||
#
|
||||
# Based on sheevaplug/kwbimage.cfg originally written by
|
||||
# Prafulla Wadaskar <prafulla@marvell.com>
|
||||
# (C) Copyright 2009
|
||||
# Marvell Semiconductor <www.marvell.com>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Refer doc/README.kwbimage for more details about how-to configure
|
||||
# and create kirkwood boot image
|
||||
#
|
||||
|
||||
# Boot Media configurations
|
||||
BOOT_FROM nand
|
||||
NAND_ECC_MODE default
|
||||
NAND_PAGE_SIZE 0x0200
|
||||
|
||||
# SOC registers configuration using bootrom header extension
|
||||
# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
|
||||
|
||||
# Configure RGMII-0 interface pad voltage to 1.8V
|
||||
DATA 0xFFD100e0 0x1b1b1b9b
|
||||
|
||||
#Dram initalization for SINGLE x16 CL=5 @ 400MHz
|
||||
DATA 0xFFD01400 0x43000618 # DDR Configuration register
|
||||
# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
|
||||
# bit23-14: zero
|
||||
# bit24: 1= enable exit self refresh mode on DDR access
|
||||
# bit25: 1 required
|
||||
# bit29-26: zero
|
||||
# bit31-30: 01
|
||||
|
||||
DATA 0xFFD01404 0x35143000 # DDR Controller Control Low
|
||||
# bit 4: 0=addr/cmd in smame cycle
|
||||
# bit 5: 0=clk is driven during self refresh, we don't care for APX
|
||||
# bit 6: 0=use recommended falling edge of clk for addr/cmd
|
||||
# bit14: 0=input buffer always powered up
|
||||
# bit18: 1=cpu lock transaction enabled
|
||||
# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
|
||||
# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
|
||||
# bit30-28: 3 required
|
||||
# bit31: 0=no additional STARTBURST delay
|
||||
|
||||
DATA 0xFFD01408 0x11012227 # DDR Timing (Low) (active cycles value +1)
|
||||
# bit7-4: TRCD
|
||||
# bit11- 8: TRP
|
||||
# bit15-12: TWR
|
||||
# bit19-16: TWTR
|
||||
# bit20: TRAS msb
|
||||
# bit23-21: 0x0
|
||||
# bit27-24: TRRD
|
||||
# bit31-28: TRTP
|
||||
|
||||
DATA 0xFFD0140C 0x00000819 # DDR Timing (High)
|
||||
# bit6-0: TRFC
|
||||
# bit8-7: TR2R
|
||||
# bit10-9: TR2W
|
||||
# bit12-11: TW2W
|
||||
# bit31-13: zero required
|
||||
|
||||
|
||||
DATA 0xFFD01410 0x0000000d # DDR Address Control
|
||||
# bit1-0: 00, Cs0width=x8
|
||||
# bit3-2: 11, Cs0size=1Gb
|
||||
# bit5-4: 00, Cs1width=nonexistent
|
||||
# bit7-6: 00, Cs1size =nonexistent
|
||||
# bit9-8: 00, Cs2width=nonexistent
|
||||
# bit11-10: 00, Cs2size =nonexistent
|
||||
# bit13-12: 00, Cs3width=nonexistent
|
||||
# bit15-14: 00, Cs3size =nonexistent
|
||||
# bit16: 0, Cs0AddrSel
|
||||
# bit17: 0, Cs1AddrSel
|
||||
# bit18: 0, Cs2AddrSel
|
||||
# bit19: 0, Cs3AddrSel
|
||||
# bit31-20: 0 required
|
||||
|
||||
DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
|
||||
# bit0: 0, OpenPage enabled
|
||||
# bit31-1: 0 required
|
||||
|
||||
DATA 0xFFD01418 0x00000000 # DDR Operation
|
||||
# bit3-0: 0x0, DDR cmd
|
||||
# bit31-4: 0 required
|
||||
|
||||
DATA 0xFFD0141C 0x00000632 # DDR Mode
|
||||
# bit2-0: 2, BurstLen=2 required
|
||||
# bit3: 0, BurstType=0 required
|
||||
# bit6-4: 4, CL=5
|
||||
# bit7: 0, TestMode=0 normal
|
||||
# bit8: 0, DLL reset=0 normal
|
||||
# bit11-9: 6, auto-precharge write recovery ????????????
|
||||
# bit12: 0, PD must be zero
|
||||
# bit31-13: 0 required
|
||||
|
||||
|
||||
DATA 0xFFD01420 0x00000040 # DDR Extended Mode
|
||||
# bit0: 0, DDR DLL enabled
|
||||
# bit1: 0, DDR drive strenght normal
|
||||
# bit2: 0, DDR ODT control lsd (disabled)
|
||||
# bit5-3: 000, required
|
||||
# bit6: 1, DDR ODT control msb, (disabled)
|
||||
# bit9-7: 000, required
|
||||
# bit10: 0, differential DQS enabled
|
||||
# bit11: 0, required
|
||||
# bit12: 0, DDR output buffer enabled
|
||||
# bit31-13: 0 required
|
||||
|
||||
DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
|
||||
# bit2-0: 111, required
|
||||
# bit3 : 1 , MBUS Burst Chop disabled
|
||||
# bit6-4: 111, required
|
||||
# bit7 : 0
|
||||
# bit8 : 0
|
||||
# bit9 : 0 , no half clock cycle addition to dataout
|
||||
# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
|
||||
# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
|
||||
# bit15-12: 1111 required
|
||||
# bit31-16: 0 required
|
||||
|
||||
DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
|
||||
# bit0: 1, Window enabled
|
||||
# bit1: 0, Write Protect disabled
|
||||
# bit3-2: 00, CS0 hit selected
|
||||
# bit23-4: ones, required
|
||||
# bit31-24: 0x07, Size (i.e. 128MB)
|
||||
|
||||
DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 0x0
|
||||
|
||||
DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
|
||||
|
||||
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
|
||||
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
|
||||
|
||||
DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
|
||||
DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
|
||||
# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
|
||||
# bit3-2: 01, ODT1 active NEVER!
|
||||
# bit31-4: zero, required
|
||||
|
||||
DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
|
||||
|
||||
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
|
||||
#bit0=1, enable DDR init upon this register write
|
||||
|
||||
DATA 0xffd01620 0x00465000
|
||||
|
||||
# End of Header extension
|
||||
DATA 0x0 0x0
|
||||
|
||||
118
board/Seagate/nas220/nas220.c
Normal file
118
board/Seagate/nas220/nas220.c
Normal file
|
|
@ -0,0 +1,118 @@
|
|||
/*
|
||||
* Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com>
|
||||
*
|
||||
* Based on sheevaplug.c originally written by
|
||||
* Prafulla Wadaskar <prafulla@marvell.com>
|
||||
* (C) Copyright 2009
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <miiphy.h>
|
||||
#include <asm/arch/soc.h>
|
||||
#include <asm/arch/mpp.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/*
|
||||
* default gpio configuration
|
||||
*/
|
||||
mvebu_config_gpio(NAS220_GE_OE_VAL_LOW, NAS220_GE_OE_VAL_HIGH,
|
||||
NAS220_GE_OE_LOW, NAS220_GE_OE_HIGH);
|
||||
|
||||
/* Multi-Purpose Pins Functionality configuration */
|
||||
static const u32 kwmpp_config[] = {
|
||||
MPP0_NF_IO2,
|
||||
MPP1_NF_IO3,
|
||||
MPP2_NF_IO4,
|
||||
MPP3_NF_IO5,
|
||||
MPP4_NF_IO6,
|
||||
MPP5_NF_IO7,
|
||||
MPP6_SYSRST_OUTn,
|
||||
MPP7_SPI_SCn,
|
||||
MPP8_TW_SDA,
|
||||
MPP9_TW_SCK,
|
||||
MPP10_UART0_TXD,
|
||||
MPP11_UART0_RXD,
|
||||
MPP12_GPO,
|
||||
MPP13_GPIO,
|
||||
MPP14_GPIO,
|
||||
MPP15_SATA0_ACTn,
|
||||
MPP16_SATA1_ACTn,
|
||||
MPP17_SATA0_PRESENTn,
|
||||
MPP18_NF_IO0,
|
||||
MPP19_NF_IO1,
|
||||
MPP20_GPIO,
|
||||
MPP21_GPIO,
|
||||
MPP22_GPIO,
|
||||
MPP23_GPIO,
|
||||
MPP24_GPIO,
|
||||
MPP25_GPIO,
|
||||
MPP26_GPIO,
|
||||
MPP27_GPIO,
|
||||
MPP28_GPIO,
|
||||
MPP29_GPIO,
|
||||
MPP30_GPIO,
|
||||
MPP31_GPIO,
|
||||
MPP32_GPIO,
|
||||
MPP33_GPIO,
|
||||
MPP34_GPIO,
|
||||
MPP35_GPIO,
|
||||
0
|
||||
};
|
||||
kirkwood_mpp_conf(kwmpp_config, NULL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/*
|
||||
* arch number of board
|
||||
*/
|
||||
gd->bd->bi_arch_number = MACH_TYPE_NAS220;
|
||||
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_RESET_PHY_R
|
||||
/* Configure and enable MV88E1116 PHY */
|
||||
void reset_phy(void)
|
||||
{
|
||||
u16 reg;
|
||||
u16 devadr;
|
||||
char *name = "egiga0";
|
||||
|
||||
if (miiphy_set_current_dev(name))
|
||||
return;
|
||||
|
||||
/* command to read PHY dev address */
|
||||
if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
|
||||
printf("Err..%s could not read PHY dev address\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable RGMII delay on Tx and Rx for CPU port
|
||||
* Ref: sec 4.7.2 of chip datasheet
|
||||
*/
|
||||
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
|
||||
miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
|
||||
reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
|
||||
miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
|
||||
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
|
||||
|
||||
/* reset the phy */
|
||||
miiphy_reset(name, devadr);
|
||||
|
||||
printf("88E1116 Initialized on %s\n", name);
|
||||
}
|
||||
#endif /* CONFIG_RESET_PHY_R */
|
||||
3
configs/nas220_defconfig
Normal file
3
configs/nas220_defconfig
Normal file
|
|
@ -0,0 +1,3 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_KIRKWOOD=y
|
||||
CONFIG_TARGET_NAS220=y
|
||||
168
include/configs/nas220.h
Normal file
168
include/configs/nas220.h
Normal file
|
|
@ -0,0 +1,168 @@
|
|||
/*
|
||||
* Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com>
|
||||
*
|
||||
* based on work from:
|
||||
* (C) Copyright 2009
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _CONFIG_NAS220_H
|
||||
#define _CONFIG_NAS220_H
|
||||
|
||||
/*
|
||||
* Machine type definition and ID
|
||||
*/
|
||||
#define MACH_TYPE_NAS220 MACH_TYPE_RD88F6192_NAS
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_NAS220
|
||||
#define CONFIG_IDENT_STRING "\nNAS 220"
|
||||
|
||||
/*
|
||||
* High Level Configuration Options (easy to change)
|
||||
*/
|
||||
#define CONFIG_FEROCEON_88FR131 /* #define CPU Core subversion */
|
||||
#define CONFIG_KW88F6192 /* SOC Name */
|
||||
#define CONFIG_SYS_GENERIC_BOARD
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
|
||||
|
||||
/* power-on led, regulator, sata0, sata1 */
|
||||
#define NAS220_GE_OE_VAL_LOW ((1 << 12)|(1 << 14)|(1 << 24)|(1 << 28))
|
||||
#define NAS220_GE_OE_VAL_HIGH (0)
|
||||
#define NAS220_GE_OE_LOW (~((1 << 12)|(1 << 14)|(1 << 24)|(1 << 28)))
|
||||
#define NAS220_GE_OE_HIGH (~(0))
|
||||
|
||||
/* PHY related */
|
||||
#define MV88E1116_LED_FCTRL_REG 10
|
||||
#define MV88E1116_CPRSP_CR3_REG 21
|
||||
#define MV88E1116_MAC_CTRL_REG 21
|
||||
#define MV88E1116_PGADR_REG 22
|
||||
#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
|
||||
#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
|
||||
|
||||
/*
|
||||
* Commands configuration
|
||||
*/
|
||||
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
|
||||
#include <config_cmd_default.h>
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_NAND
|
||||
#define CONFIG_CMD_SAVEENV
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_IDE
|
||||
#define CONFIG_SYS_LONGHELP
|
||||
#define CONFIG_AUTO_COMPLETE
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
|
||||
/*
|
||||
* mv-common.h should be defined after CMD configs since it used them
|
||||
* to enable certain macros
|
||||
*/
|
||||
#include "mv-common.h"
|
||||
|
||||
/* Remove or override few declarations from mv-common.h */
|
||||
#undef CONFIG_SYS_PROMPT /* previously defined in mv-common.h */
|
||||
#define CONFIG_SYS_PROMPT "nas220> "
|
||||
|
||||
/*
|
||||
* Environment variables configurations
|
||||
*/
|
||||
#ifdef CONFIG_CMD_NAND
|
||||
#define CONFIG_ENV_IS_IN_NAND
|
||||
#define CONFIG_ENV_SECT_SIZE 0x10000
|
||||
#else
|
||||
#define CONFIG_ENV_IS_NOWHERE
|
||||
#endif
|
||||
|
||||
#define CONFIG_ENV_SIZE 0x10000
|
||||
#define CONFIG_ENV_OFFSET 0xa0000
|
||||
|
||||
/*
|
||||
* Default environment variables
|
||||
*/
|
||||
#define CONFIG_BOOTCOMMAND ""
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"bootargs=console=ttyS0,115200\0" \
|
||||
"mtdparts=mtdparts=orion_nand:0xa0000@0x0(uboot),"\
|
||||
"0x010000@0xa0000(env),"\
|
||||
"0x500000@0xc0000(uimage),"\
|
||||
"0x1a40000@0x5c0000(rootfs)\0" \
|
||||
"mtdids=nand0=orion_nand\0"\
|
||||
"bootdelay=-1\0"\
|
||||
"autostart=no\0"\
|
||||
"autoload=no\0"
|
||||
|
||||
/*
|
||||
* Ethernet Driver configuration
|
||||
*/
|
||||
#ifdef CONFIG_CMD_NET
|
||||
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
|
||||
#define CONFIG_PHY_BASE_ADR 8
|
||||
#endif /* CONFIG_CMD_NET */
|
||||
|
||||
/*
|
||||
* USB/EHCI
|
||||
*/
|
||||
#ifdef CONFIG_CMD_USB
|
||||
#define CONFIG_USB_EHCI /* Enable EHCI USB support */
|
||||
#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */
|
||||
#define CONFIG_EHCI_IS_TDI
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_SUPPORT_VFAT
|
||||
#endif /* CONFIG_CMD_USB */
|
||||
|
||||
/*
|
||||
* File system
|
||||
*/
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_EXT4
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_JFFS2
|
||||
#define CONFIG_JFFS2_NAND
|
||||
#define CONFIG_JFFS2_LZO
|
||||
#define CONFIG_CMD_UBI
|
||||
#define CONFIG_CMD_UBIFS
|
||||
#define CONFIG_RBTREE
|
||||
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
|
||||
#define CONFIG_MTD_PARTITIONS
|
||||
#define CONFIG_CMD_MTDPARTS
|
||||
#define CONFIG_LZO
|
||||
|
||||
/*
|
||||
* SATA
|
||||
*/
|
||||
#ifdef CONFIG_MVSATA_IDE
|
||||
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
|
||||
#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* Device Tree
|
||||
*/
|
||||
#define CONFIG_OF_LIBFDT
|
||||
|
||||
/*
|
||||
* EFI partition
|
||||
*/
|
||||
#define CONFIG_EFI_PARTITION
|
||||
|
||||
/*
|
||||
* Date Time
|
||||
*/
|
||||
#ifdef CONFIG_CMD_DATE
|
||||
#define CONFIG_RTC_MV
|
||||
#endif /* CONFIG_CMD_DATE */
|
||||
|
||||
#define CONFIG_KIRKWOOD_GPIO
|
||||
|
||||
#endif /* _CONFIG_NAS220_H */
|
||||
|
||||
Loading…
Reference in a new issue