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https://github.com/AsahiLinux/u-boot
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arm, spl, at91: add spl support for the corvus board
replaces the at91bootstrap code with SPL code. make the spl image with: ./tools/mkimage -T atmelimage -d spl/u-boot-spl.bin spl/boot.bin this writes the length of the spl image into the 6th execption vector. This is needed from the ROM bootloader. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bo Shen <voice.shen@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
This commit is contained in:
Heiko Schocher
Tom Rini
parent
237e3793fb
commit
5b15fd980b
4 changed files with 151 additions and 18 deletions
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@ -203,6 +203,7 @@ config TARGET_PM9G45
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select CPU_ARM926EJS
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config TARGET_CORVUS
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select SUPPORT_SPL
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bool "Support corvus"
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select CPU_ARM926EJS
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@ -31,12 +31,10 @@
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_CMD_NAND
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static void corvus_nand_hw_init(void)
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{
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struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
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struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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unsigned long csa;
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/* Enable CS3 */
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@ -63,22 +61,111 @@ static void corvus_nand_hw_init(void)
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AT91_SMC_MODE_TDF_CYCLE(3),
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&smc->cs[3].mode);
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writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
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/* Configure RDY/BSY */
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at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
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at91_periph_clk_enable(ATMEL_ID_PIOC);
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/* Enable NandFlash */
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at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
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}
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#if defined(CONFIG_SPL_BUILD)
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#include <spl.h>
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#include <nand.h>
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void at91_spl_board_init(void)
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{
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/*
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* For on the sam9m10g45ek board, the chip wm9711 stay in the test
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* mode, so it need do some action to exit mode.
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*/
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at91_set_gpio_output(AT91_PIN_PD7, 0);
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at91_set_gpio_output(AT91_PIN_PD8, 0);
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at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
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at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
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at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
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at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
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at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
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corvus_nand_hw_init();
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/* Configure recovery button PINs */
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at91_set_gpio_input(AT91_PIN_PB7, 1);
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/* check if button is pressed */
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if (at91_get_gpio_value(AT91_PIN_PB7) == 0) {
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u32 boot_device;
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debug("Recovery button pressed\n");
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boot_device = spl_boot_device();
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switch (boot_device) {
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#ifdef CONFIG_SPL_NAND_SUPPORT
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case BOOT_DEVICE_NAND:
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nand_init();
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spl_nand_erase_one(0, 0);
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break;
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#endif
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}
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}
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}
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#include <asm/arch/atmel_mpddrc.h>
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static void ddr2_conf(struct atmel_mpddr *ddr2)
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{
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ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
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ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
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ATMEL_MPDDRC_CR_NR_ROW_14 |
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ATMEL_MPDDRC_CR_DIC_DS |
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ATMEL_MPDDRC_CR_DQMS_SHARED |
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ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
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ddr2->rtr = 0x24b;
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ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
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2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
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2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
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8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 75 ns */
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2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
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1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
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1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
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2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
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ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
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200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
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16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
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14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
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ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
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0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
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7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
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2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
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}
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void mem_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
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struct atmel_mpddr ddr2;
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unsigned long csa;
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ddr2_conf(&ddr2);
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/* enable DDR2 clock */
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writel(0x4, &pmc->scer);
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/* Chip select 1 is for DDR2/SDRAM */
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csa = readl(&mat->ebicsa);
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csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
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csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V;
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writel(csa, &mat->ebicsa);
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/* DDRAM2 Controller initialize */
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ddr2_init(ATMEL_BASE_CS6, &ddr2);
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}
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#endif
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#ifdef CONFIG_CMD_USB
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static void taurus_usb_hw_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
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at91_periph_clk_enable(ATMEL_ID_PIODE);
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at91_set_gpio_output(AT91_PIN_PD1, 0);
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at91_set_gpio_output(AT91_PIN_PD3, 0);
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@ -88,10 +175,8 @@ static void taurus_usb_hw_init(void)
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#ifdef CONFIG_MACB
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static void corvus_macb_hw_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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/* Enable clock */
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writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
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at91_periph_clk_enable(ATMEL_ID_EMAC);
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/*
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* Disable pull-up on:
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@ -1,3 +1,4 @@
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CONFIG_SPL=y
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CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH"
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CONFIG_ARM=y
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CONFIG_TARGET_CORVUS=y
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+S:CONFIG_ARM=y
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+S:CONFIG_TARGET_CORVUS=y
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@ -19,7 +19,6 @@
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#define MACH_TYPE_CORVUS 2066
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#define CONFIG_SYS_GENERIC_BOARD
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/*
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* Warning: changing CONFIG_SYS_TEXT_BASE requires
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* adapting the initial boot program.
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@ -27,7 +26,7 @@
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* hex number here!
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*/
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#define CONFIG_SYS_TEXT_BASE 0x73f00000
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#define CONFIG_SYS_TEXT_BASE 0x72000000
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#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
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@ -107,8 +106,6 @@
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/* our CLE is AD22 */
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#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
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#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
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#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8
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#endif
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/* Ethernet */
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@ -159,5 +156,54 @@
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*/
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#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \
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128*1024, 0x1000)
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/* Defines for SPL */
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_TEXT_BASE 0x300000
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#define CONFIG_SPL_MAX_SIZE (12 * 1024)
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#define CONFIG_SPL_STACK (16 * 1024)
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#define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE
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#define CONFIG_SPL_BSS_MAX_SIZE (2 * 1024)
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_BOARD_INIT
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#define CONFIG_SPL_GPIO_SUPPORT
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#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14)
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#define CONFIG_SPL_NAND_SUPPORT
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#define CONFIG_SPL_NAND_DRIVERS
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#define CONFIG_SPL_NAND_BASE
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#define CONFIG_SPL_NAND_ECC
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#define CONFIG_SPL_NAND_RAW_ONLY
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#define CONFIG_SPL_NAND_SOFTECC
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
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#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_SIZE (256*1024*1024)
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
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#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
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CONFIG_SYS_NAND_PAGE_SIZE)
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
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#define CONFIG_SYS_NAND_ECCSIZE 256
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
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48, 49, 50, 51, 52, 53, 54, 55, \
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56, 57, 58, 59, 60, 61, 62, 63, }
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#define CONFIG_SPL_ATMEL_SIZE
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#define CONFIG_SYS_MASTER_CLOCK 132096000
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#define AT91_PLL_LOCK_TIMEOUT 1000000
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#define CONFIG_SYS_AT91_PLLA 0x20c73f03
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#define CONFIG_SYS_MCKR 0x1301
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#define CONFIG_SYS_MCKR_CSS 0x1302
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#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC0
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#endif
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