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x86: quark: Add utility codes needed for MRC
Add various utility codes needed for Quark MRC. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Bin Meng
Simon Glass
parent
0a391b1c79
commit
38ad43e436
4 changed files with 2068 additions and 0 deletions
396
arch/x86/cpu/quark/hte.c
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396
arch/x86/cpu/quark/hte.c
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/*
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* Copyright (C) 2013, Intel Corporation
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* Ported from Intel released Quark UEFI BIOS
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* QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei
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*
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* SPDX-License-Identifier: Intel
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*/
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#include <common.h>
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#include <asm/arch/mrc.h>
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#include <asm/arch/msg_port.h>
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#include "mrc_util.h"
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#include "hte.h"
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/**
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* Enable HTE to detect all possible errors for the given training parameters
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* (per-bit or full byte lane).
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*/
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static void hte_enable_all_errors(void)
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{
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msg_port_write(HTE, 0x000200A2, 0xFFFFFFFF);
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msg_port_write(HTE, 0x000200A3, 0x000000FF);
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msg_port_write(HTE, 0x000200A4, 0x00000000);
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}
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/**
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* Go and read the HTE register in order to find any error
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*
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* @return: The errors detected in the HTE status register
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*/
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static u32 hte_check_errors(void)
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{
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return msg_port_read(HTE, 0x000200A7);
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}
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/**
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* Wait until HTE finishes
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*/
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static void hte_wait_for_complete(void)
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{
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u32 tmp;
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ENTERFN();
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do {} while ((msg_port_read(HTE, 0x00020012) & BIT30) != 0);
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tmp = msg_port_read(HTE, 0x00020011);
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tmp |= BIT9;
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tmp &= ~(BIT12 | BIT13);
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msg_port_write(HTE, 0x00020011, tmp);
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LEAVEFN();
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}
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/**
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* Clear registers related with errors in the HTE
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*/
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static void hte_clear_error_regs(void)
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{
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u32 tmp;
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/*
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* Clear all HTE errors and enable error checking
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* for burst and chunk.
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*/
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tmp = msg_port_read(HTE, 0x000200A1);
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tmp |= BIT8;
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msg_port_write(HTE, 0x000200A1, tmp);
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}
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/**
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* Execute a basic single-cache-line memory write/read/verify test using simple
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* constant pattern, different for READ_TRAIN and WRITE_TRAIN modes.
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*
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* See hte_basic_write_read() which is the external visible wrapper.
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*
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* @mrc_params: host structure for all MRC global data
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* @addr: memory adress being tested (must hit specific channel/rank)
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* @first_run: if set then the HTE registers are configured, otherwise it is
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* assumed configuration is done and we just re-run the test
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* @mode: READ_TRAIN or WRITE_TRAIN (the difference is in the pattern)
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*
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* @return: byte lane failure on each bit (for Quark only bit0 and bit1)
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*/
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static u16 hte_basic_data_cmp(struct mrc_params *mrc_params, u32 addr,
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u8 first_run, u8 mode)
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{
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u32 pattern;
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u32 offset;
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if (first_run) {
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msg_port_write(HTE, 0x00020020, 0x01B10021);
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msg_port_write(HTE, 0x00020021, 0x06000000);
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msg_port_write(HTE, 0x00020022, addr >> 6);
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msg_port_write(HTE, 0x00020062, 0x00800015);
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msg_port_write(HTE, 0x00020063, 0xAAAAAAAA);
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msg_port_write(HTE, 0x00020064, 0xCCCCCCCC);
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msg_port_write(HTE, 0x00020065, 0xF0F0F0F0);
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msg_port_write(HTE, 0x00020061, 0x00030008);
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if (mode == WRITE_TRAIN)
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pattern = 0xC33C0000;
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else /* READ_TRAIN */
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pattern = 0xAA5555AA;
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for (offset = 0x80; offset <= 0x8F; offset++)
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msg_port_write(HTE, offset, pattern);
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}
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msg_port_write(HTE, 0x000200A1, 0xFFFF1000);
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msg_port_write(HTE, 0x00020011, 0x00011000);
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msg_port_write(HTE, 0x00020011, 0x00011100);
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hte_wait_for_complete();
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/*
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* Return bits 15:8 of HTE_CH0_ERR_XSTAT to check for
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* any bytelane errors.
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*/
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return (hte_check_errors() >> 8) & 0xFF;
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}
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/**
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* Examine a single-cache-line memory with write/read/verify test using multiple
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* data patterns (victim-aggressor algorithm).
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*
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* See hte_write_stress_bit_lanes() which is the external visible wrapper.
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*
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* @mrc_params: host structure for all MRC global data
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* @addr: memory adress being tested (must hit specific channel/rank)
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* @loop_cnt: number of test iterations
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* @seed_victim: victim data pattern seed
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* @seed_aggressor: aggressor data pattern seed
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* @victim_bit: should be 0 as auto-rotate feature is in use
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* @first_run: if set then the HTE registers are configured, otherwise it is
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* assumed configuration is done and we just re-run the test
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*
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* @return: byte lane failure on each bit (for Quark only bit0 and bit1)
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*/
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static u16 hte_rw_data_cmp(struct mrc_params *mrc_params, u32 addr,
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u8 loop_cnt, u32 seed_victim, u32 seed_aggressor,
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u8 victim_bit, u8 first_run)
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{
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u32 offset;
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u32 tmp;
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if (first_run) {
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msg_port_write(HTE, 0x00020020, 0x00910024);
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msg_port_write(HTE, 0x00020023, 0x00810024);
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msg_port_write(HTE, 0x00020021, 0x06070000);
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msg_port_write(HTE, 0x00020024, 0x06070000);
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msg_port_write(HTE, 0x00020022, addr >> 6);
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msg_port_write(HTE, 0x00020025, addr >> 6);
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msg_port_write(HTE, 0x00020062, 0x0000002A);
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msg_port_write(HTE, 0x00020063, seed_victim);
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msg_port_write(HTE, 0x00020064, seed_aggressor);
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msg_port_write(HTE, 0x00020065, seed_victim);
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/*
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* Write the pattern buffers to select the victim bit
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*
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* Start with bit0
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*/
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for (offset = 0x80; offset <= 0x8F; offset++) {
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if ((offset % 8) == victim_bit)
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msg_port_write(HTE, offset, 0x55555555);
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else
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msg_port_write(HTE, offset, 0xCCCCCCCC);
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}
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msg_port_write(HTE, 0x00020061, 0x00000000);
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msg_port_write(HTE, 0x00020066, 0x03440000);
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msg_port_write(HTE, 0x000200A1, 0xFFFF1000);
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}
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tmp = 0x10001000 | (loop_cnt << 16);
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msg_port_write(HTE, 0x00020011, tmp);
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msg_port_write(HTE, 0x00020011, tmp | BIT8);
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hte_wait_for_complete();
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/*
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* Return bits 15:8 of HTE_CH0_ERR_XSTAT to check for
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* any bytelane errors.
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*/
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return (hte_check_errors() >> 8) & 0xFF;
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}
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/**
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* Use HW HTE engine to initialize or test all memory attached to a given DUNIT.
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* If flag is MRC_MEM_INIT, this routine writes 0s to all memory locations to
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* initialize ECC. If flag is MRC_MEM_TEST, this routine will send an 5AA55AA5
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* pattern to all memory locations on the RankMask and then read it back.
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* Then it sends an A55AA55A pattern to all memory locations on the RankMask
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* and reads it back.
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*
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* @mrc_params: host structure for all MRC global data
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* @flag: MRC_MEM_INIT or MRC_MEM_TEST
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*
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* @return: errors register showing HTE failures. Also prints out which rank
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* failed the HTE test if failure occurs. For rank detection to work,
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* the address map must be left in its default state. If MRC changes
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* the address map, this function must be modified to change it back
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* to default at the beginning, then restore it at the end.
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*/
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u32 hte_mem_init(struct mrc_params *mrc_params, u8 flag)
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{
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u32 offset;
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int test_num;
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int i;
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/*
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* Clear out the error registers at the start of each memory
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* init or memory test run.
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*/
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hte_clear_error_regs();
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msg_port_write(HTE, 0x00020062, 0x00000015);
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for (offset = 0x80; offset <= 0x8F; offset++)
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msg_port_write(HTE, offset, ((offset & 1) ? 0xA55A : 0x5AA5));
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msg_port_write(HTE, 0x00020021, 0x00000000);
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msg_port_write(HTE, 0x00020022, (mrc_params->mem_size >> 6) - 1);
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msg_port_write(HTE, 0x00020063, 0xAAAAAAAA);
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msg_port_write(HTE, 0x00020064, 0xCCCCCCCC);
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msg_port_write(HTE, 0x00020065, 0xF0F0F0F0);
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msg_port_write(HTE, 0x00020066, 0x03000000);
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switch (flag) {
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case MRC_MEM_INIT:
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/*
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* Only 1 write pass through memory is needed
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* to initialize ECC
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*/
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test_num = 1;
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break;
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case MRC_MEM_TEST:
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/* Write/read then write/read with inverted pattern */
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test_num = 4;
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break;
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default:
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DPF(D_INFO, "Unknown parameter for flag: %d\n", flag);
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return 0xFFFFFFFF;
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}
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DPF(D_INFO, "hte_mem_init");
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for (i = 0; i < test_num; i++) {
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DPF(D_INFO, ".");
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if (i == 0) {
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msg_port_write(HTE, 0x00020061, 0x00000000);
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msg_port_write(HTE, 0x00020020, 0x00110010);
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} else if (i == 1) {
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msg_port_write(HTE, 0x00020061, 0x00000000);
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msg_port_write(HTE, 0x00020020, 0x00010010);
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} else if (i == 2) {
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msg_port_write(HTE, 0x00020061, 0x00010100);
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msg_port_write(HTE, 0x00020020, 0x00110010);
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} else {
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msg_port_write(HTE, 0x00020061, 0x00010100);
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msg_port_write(HTE, 0x00020020, 0x00010010);
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}
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msg_port_write(HTE, 0x00020011, 0x00111000);
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msg_port_write(HTE, 0x00020011, 0x00111100);
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hte_wait_for_complete();
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/* If this is a READ pass, check for errors at the end */
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if ((i % 2) == 1) {
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/* Return immediately if error */
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if (hte_check_errors())
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break;
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}
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}
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DPF(D_INFO, "done\n");
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return hte_check_errors();
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}
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/**
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* Execute a basic single-cache-line memory write/read/verify test using simple
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* constant pattern, different for READ_TRAIN and WRITE_TRAIN modes.
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*
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* @mrc_params: host structure for all MRC global data
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* @addr: memory adress being tested (must hit specific channel/rank)
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* @first_run: if set then the HTE registers are configured, otherwise it is
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* assumed configuration is done and we just re-run the test
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* @mode: READ_TRAIN or WRITE_TRAIN (the difference is in the pattern)
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*
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* @return: byte lane failure on each bit (for Quark only bit0 and bit1)
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*/
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u16 hte_basic_write_read(struct mrc_params *mrc_params, u32 addr,
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u8 first_run, u8 mode)
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{
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u16 errors;
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ENTERFN();
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/* Enable all error reporting in preparation for HTE test */
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hte_enable_all_errors();
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hte_clear_error_regs();
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errors = hte_basic_data_cmp(mrc_params, addr, first_run, mode);
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LEAVEFN();
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return errors;
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}
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/**
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* Examine a single-cache-line memory with write/read/verify test using multiple
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* data patterns (victim-aggressor algorithm).
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*
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* @mrc_params: host structure for all MRC global data
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* @addr: memory adress being tested (must hit specific channel/rank)
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* @first_run: if set then the HTE registers are configured, otherwise it is
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* assumed configuration is done and we just re-run the test
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*
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* @return: byte lane failure on each bit (for Quark only bit0 and bit1)
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*/
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u16 hte_write_stress_bit_lanes(struct mrc_params *mrc_params,
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u32 addr, u8 first_run)
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{
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u16 errors;
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u8 victim_bit = 0;
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ENTERFN();
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/* Enable all error reporting in preparation for HTE test */
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hte_enable_all_errors();
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hte_clear_error_regs();
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/*
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* Loop through each bit in the bytelane.
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*
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* Each pass creates a victim bit while keeping all other bits the same
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* as aggressors. AVN HTE adds an auto-rotate feature which allows us
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* to program the entire victim/aggressor sequence in 1 step.
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*
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* The victim bit rotates on each pass so no need to have software
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* implement a victim bit loop like on VLV.
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*/
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errors = hte_rw_data_cmp(mrc_params, addr, HTE_LOOP_CNT,
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HTE_LFSR_VICTIM_SEED, HTE_LFSR_AGRESSOR_SEED,
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victim_bit, first_run);
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LEAVEFN();
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return errors;
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}
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/**
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* Execute a basic single-cache-line memory write or read.
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* This is just for receive enable / fine write-levelling purpose.
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*
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* @addr: memory adress being tested (must hit specific channel/rank)
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* @first_run: if set then the HTE registers are configured, otherwise it is
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* assumed configuration is done and we just re-run the test
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* @is_write: when non-zero memory write operation executed, otherwise read
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*/
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void hte_mem_op(u32 addr, u8 first_run, u8 is_write)
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{
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u32 offset;
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u32 tmp;
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hte_enable_all_errors();
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hte_clear_error_regs();
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if (first_run) {
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tmp = is_write ? 0x01110021 : 0x01010021;
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msg_port_write(HTE, 0x00020020, tmp);
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msg_port_write(HTE, 0x00020021, 0x06000000);
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msg_port_write(HTE, 0x00020022, addr >> 6);
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msg_port_write(HTE, 0x00020062, 0x00800015);
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msg_port_write(HTE, 0x00020063, 0xAAAAAAAA);
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msg_port_write(HTE, 0x00020064, 0xCCCCCCCC);
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msg_port_write(HTE, 0x00020065, 0xF0F0F0F0);
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msg_port_write(HTE, 0x00020061, 0x00030008);
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for (offset = 0x80; offset <= 0x8F; offset++)
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msg_port_write(HTE, offset, 0xC33C0000);
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}
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msg_port_write(HTE, 0x000200A1, 0xFFFF1000);
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msg_port_write(HTE, 0x00020011, 0x00011000);
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msg_port_write(HTE, 0x00020011, 0x00011100);
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hte_wait_for_complete();
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}
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44
arch/x86/cpu/quark/hte.h
Normal file
44
arch/x86/cpu/quark/hte.h
Normal file
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@ -0,0 +1,44 @@
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/*
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* Copyright (C) 2013, Intel Corporation
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* Ported from Intel released Quark UEFI BIOS
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* QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei
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*
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* SPDX-License-Identifier: Intel
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*/
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#ifndef _HTE_H_
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#define _HTE_H_
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enum {
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MRC_MEM_INIT,
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MRC_MEM_TEST
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};
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enum {
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READ_TRAIN,
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WRITE_TRAIN
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};
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/*
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* EXP_LOOP_CNT field of HTE_CMD_CTL
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*
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* This CANNOT be less than 4!
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*/
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#define HTE_LOOP_CNT 5
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/* random seed for victim */
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#define HTE_LFSR_VICTIM_SEED 0xF294BA21
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/* random seed for aggressor */
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#define HTE_LFSR_AGRESSOR_SEED 0xEBA7492D
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u32 hte_mem_init(struct mrc_params *mrc_params, u8 flag);
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u16 hte_basic_write_read(struct mrc_params *mrc_params, u32 addr,
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u8 first_run, u8 mode);
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u16 hte_write_stress_bit_lanes(struct mrc_params *mrc_params,
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u32 addr, u8 first_run);
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void hte_mem_op(u32 addr, u8 first_run, u8 is_write);
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#endif /* _HTE_H_ */
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1475
arch/x86/cpu/quark/mrc_util.c
Normal file
1475
arch/x86/cpu/quark/mrc_util.c
Normal file
File diff suppressed because it is too large
Load diff
153
arch/x86/cpu/quark/mrc_util.h
Normal file
153
arch/x86/cpu/quark/mrc_util.h
Normal file
|
|
@ -0,0 +1,153 @@
|
|||
/*
|
||||
* Copyright (C) 2013, Intel Corporation
|
||||
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
|
||||
*
|
||||
* Ported from Intel released Quark UEFI BIOS
|
||||
* QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei
|
||||
*
|
||||
* SPDX-License-Identifier: Intel
|
||||
*/
|
||||
|
||||
#ifndef _MRC_UTIL_H_
|
||||
#define _MRC_UTIL_H_
|
||||
|
||||
/* Turn on this macro to enable MRC debugging output */
|
||||
#undef MRC_DEBUG
|
||||
|
||||
/* MRC Debug Support */
|
||||
#define DPF debug_cond
|
||||
|
||||
/* debug print type */
|
||||
|
||||
#ifdef MRC_DEBUG
|
||||
#define D_ERROR 0x0001
|
||||
#define D_INFO 0x0002
|
||||
#define D_REGRD 0x0004
|
||||
#define D_REGWR 0x0008
|
||||
#define D_FCALL 0x0010
|
||||
#define D_TRN 0x0020
|
||||
#define D_TIME 0x0040
|
||||
#else
|
||||
#define D_ERROR 0
|
||||
#define D_INFO 0
|
||||
#define D_REGRD 0
|
||||
#define D_REGWR 0
|
||||
#define D_FCALL 0
|
||||
#define D_TRN 0
|
||||
#define D_TIME 0
|
||||
#endif
|
||||
|
||||
#define ENTERFN(...) debug_cond(D_FCALL, "<%s>\n", __func__)
|
||||
#define LEAVEFN(...) debug_cond(D_FCALL, "</%s>\n", __func__)
|
||||
#define REPORTFN(...) debug_cond(D_FCALL, "<%s/>\n", __func__)
|
||||
|
||||
/* Generic Register Bits */
|
||||
#define BIT0 0x00000001
|
||||
#define BIT1 0x00000002
|
||||
#define BIT2 0x00000004
|
||||
#define BIT3 0x00000008
|
||||
#define BIT4 0x00000010
|
||||
#define BIT5 0x00000020
|
||||
#define BIT6 0x00000040
|
||||
#define BIT7 0x00000080
|
||||
#define BIT8 0x00000100
|
||||
#define BIT9 0x00000200
|
||||
#define BIT10 0x00000400
|
||||
#define BIT11 0x00000800
|
||||
#define BIT12 0x00001000
|
||||
#define BIT13 0x00002000
|
||||
#define BIT14 0x00004000
|
||||
#define BIT15 0x00008000
|
||||
#define BIT16 0x00010000
|
||||
#define BIT17 0x00020000
|
||||
#define BIT18 0x00040000
|
||||
#define BIT19 0x00080000
|
||||
#define BIT20 0x00100000
|
||||
#define BIT21 0x00200000
|
||||
#define BIT22 0x00400000
|
||||
#define BIT23 0x00800000
|
||||
#define BIT24 0x01000000
|
||||
#define BIT25 0x02000000
|
||||
#define BIT26 0x04000000
|
||||
#define BIT27 0x08000000
|
||||
#define BIT28 0x10000000
|
||||
#define BIT29 0x20000000
|
||||
#define BIT30 0x40000000
|
||||
#define BIT31 0x80000000
|
||||
|
||||
/* Message Bus Port */
|
||||
#define MEM_CTLR 0x01
|
||||
#define HOST_BRIDGE 0x03
|
||||
#define MEM_MGR 0x05
|
||||
#define HTE 0x11
|
||||
#define DDRPHY 0x12
|
||||
|
||||
/* number of sample points */
|
||||
#define SAMPLE_CNT 3
|
||||
/* number of PIs to increment per sample */
|
||||
#define SAMPLE_DLY 26
|
||||
|
||||
enum {
|
||||
/* indicates to decrease delays when looking for edge */
|
||||
BACKWARD,
|
||||
/* indicates to increase delays when looking for edge */
|
||||
FORWARD
|
||||
};
|
||||
|
||||
enum {
|
||||
RCVN,
|
||||
WDQS,
|
||||
WDQX,
|
||||
RDQS,
|
||||
VREF,
|
||||
WCMD,
|
||||
WCTL,
|
||||
WCLK,
|
||||
MAX_ALGOS,
|
||||
};
|
||||
|
||||
void mrc_write_mask(u32 unit, u32 addr, u32 data, u32 mask);
|
||||
void mrc_alt_write_mask(u32 unit, u32 addr, u32 data, u32 mask);
|
||||
void mrc_post_code(uint8_t major, uint8_t minor);
|
||||
void delay_n(uint32_t ns);
|
||||
void delay_u(uint32_t ms);
|
||||
void select_mem_mgr(void);
|
||||
void select_hte(void);
|
||||
void dram_init_command(uint32_t data);
|
||||
void dram_wake_command(void);
|
||||
void training_message(uint8_t channel, uint8_t rank, uint8_t byte_lane);
|
||||
|
||||
void set_rcvn(uint8_t channel, uint8_t rank,
|
||||
uint8_t byte_lane, uint32_t pi_count);
|
||||
uint32_t get_rcvn(uint8_t channel, uint8_t rank, uint8_t byte_lane);
|
||||
void set_rdqs(uint8_t channel, uint8_t rank,
|
||||
uint8_t byte_lane, uint32_t pi_count);
|
||||
uint32_t get_rdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane);
|
||||
void set_wdqs(uint8_t channel, uint8_t rank,
|
||||
uint8_t byte_lane, uint32_t pi_count);
|
||||
uint32_t get_wdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane);
|
||||
void set_wdq(uint8_t channel, uint8_t rank,
|
||||
uint8_t byte_lane, uint32_t pi_count);
|
||||
uint32_t get_wdq(uint8_t channel, uint8_t rank, uint8_t byte_lane);
|
||||
void set_wcmd(uint8_t channel, uint32_t pi_count);
|
||||
uint32_t get_wcmd(uint8_t channel);
|
||||
void set_wclk(uint8_t channel, uint8_t rank, uint32_t pi_count);
|
||||
uint32_t get_wclk(uint8_t channel, uint8_t rank);
|
||||
void set_wctl(uint8_t channel, uint8_t rank, uint32_t pi_count);
|
||||
uint32_t get_wctl(uint8_t channel, uint8_t rank);
|
||||
void set_vref(uint8_t channel, uint8_t byte_lane, uint32_t setting);
|
||||
uint32_t get_vref(uint8_t channel, uint8_t byte_lane);
|
||||
|
||||
uint32_t get_addr(uint8_t channel, uint8_t rank);
|
||||
uint32_t sample_dqs(struct mrc_params *mrc_params, uint8_t channel,
|
||||
uint8_t rank, bool rcvn);
|
||||
void find_rising_edge(struct mrc_params *mrc_params, uint32_t delay[],
|
||||
uint8_t channel, uint8_t rank, bool rcvn);
|
||||
uint32_t byte_lane_mask(struct mrc_params *mrc_params);
|
||||
uint32_t check_rw_coarse(struct mrc_params *mrc_params, uint32_t address);
|
||||
uint32_t check_bls_ex(struct mrc_params *mrc_params, uint32_t address);
|
||||
void lfsr32(uint32_t *lfsr_ptr);
|
||||
void clear_pointers(void);
|
||||
void print_timings(struct mrc_params *mrc_params);
|
||||
|
||||
#endif /* _MRC_UTIL_H_ */
|
||||
Loading…
Reference in a new issue