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https://github.com/AsahiLinux/u-boot
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arm, at91, spl: add spl support for the taurus board
replaces the at91bootstrap code with SPL code. make the spl image with: ./tools/mkimage -T atmelimage -d spl/u-boot-spl.bin spl/boot.bin this writes the length of the spl image into the 6th execption vector. This is needed from the ROM bootloader. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
This commit is contained in:
Heiko Schocher
Tom Rini
parent
5abc00d020
commit
237e3793fb
4 changed files with 127 additions and 13 deletions
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@ -207,6 +207,7 @@ config TARGET_CORVUS
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select CPU_ARM926EJS
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config TARGET_TAURUS
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select SUPPORT_SPL
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bool "Support taurus"
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select CPU_ARM926EJS
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@ -21,6 +21,8 @@
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/at91sam9_sdramc.h>
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#include <asm/arch/clk.h>
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#include <linux/mtd/nand.h>
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#include <atmel_mci.h>
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#include <asm/arch/at91_spi.h>
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#include <spi.h>
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@ -30,7 +32,6 @@
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_CMD_NAND
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static void taurus_nand_hw_init(void)
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{
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struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
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@ -63,15 +64,77 @@ static void taurus_nand_hw_init(void)
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/* Enable NandFlash */
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at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
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}
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#if defined(CONFIG_SPL_BUILD)
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#include <spl.h>
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#include <nand.h>
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void matrix_init(void)
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{
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struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
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writel((readl(&mat->scfg[3]) & (~AT91_MATRIX_SLOT_CYCLE))
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| AT91_MATRIX_SLOT_CYCLE_(0x40),
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&mat->scfg[3]);
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}
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void at91_spl_board_init(void)
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{
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taurus_nand_hw_init();
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/* Configure recovery button PINs */
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at91_set_gpio_input(AT91_PIN_PA31, 1);
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/* check if button is pressed */
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if (at91_get_gpio_value(AT91_PIN_PA31) == 0) {
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u32 boot_device;
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debug("Recovery button pressed\n");
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boot_device = spl_boot_device();
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switch (boot_device) {
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#ifdef CONFIG_SPL_NAND_SUPPORT
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case BOOT_DEVICE_NAND:
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nand_init();
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spl_nand_erase_one(0, 0);
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break;
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#endif
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}
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}
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}
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void mem_init(void)
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{
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struct at91_matrix *ma = (struct at91_matrix *)ATMEL_BASE_MATRIX;
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struct sdramc_reg setting;
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at91_sdram_hw_init();
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setting.cr = (AT91_SDRAMC_NC_9 |
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AT91_SDRAMC_NR_13 |
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AT91_SDRAMC_CAS_3 |
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AT91_SDRAMC_NB_4 |
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AT91_SDRAMC_DBW_32 |
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AT91_SDRAMC_TWR_VAL(3) |
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AT91_SDRAMC_TRC_VAL(9) |
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AT91_SDRAMC_TRP_VAL(3) |
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AT91_SDRAMC_TRCD_VAL(3) |
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AT91_SDRAMC_TRAS_VAL(6) |
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AT91_SDRAMC_TXSR_VAL(10));
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setting.mdr = AT91_SDRAMC_MD_SDRAM;
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setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000;
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writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC |
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AT91_MATRIX_VDDIOMSEL_3_3V | AT91_MATRIX_EBI_IOSR_SEL,
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&ma->ebicsa);
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sdramc_initialize(ATMEL_BASE_CS1, &setting);
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}
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#endif
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#ifdef CONFIG_MACB
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static void taurus_macb_hw_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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/* Enable EMAC clock */
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writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
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at91_periph_clk_enable(ATMEL_ID_EMAC0);
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/*
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* Disable pull-up on:
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@ -119,12 +182,12 @@ int board_mmc_init(bd_t *bd)
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int board_early_init_f(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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/* Enable clocks for all PIOs */
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writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
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(1 << ATMEL_ID_PIOC),
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&pmc->pcer);
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at91_periph_clk_enable(ATMEL_ID_PIOA);
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at91_periph_clk_enable(ATMEL_ID_PIOB);
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at91_periph_clk_enable(ATMEL_ID_PIOC);
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at91_seriald_hw_init();
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return 0;
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}
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@ -149,7 +212,6 @@ int board_init(void)
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/* adress of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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at91_seriald_hw_init();
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#ifdef CONFIG_CMD_NAND
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taurus_nand_hw_init();
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#endif
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@ -1,3 +1,4 @@
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CONFIG_SPL=y
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CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS"
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CONFIG_ARM=y
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CONFIG_TARGET_TAURUS=y
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+S:CONFIG_ARM=y
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+S:CONFIG_TARGET_TAURUS=y
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@ -34,7 +34,7 @@
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*/
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#define CONFIG_SYS_TEXT_BASE 0x23f00000
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#define CONFIG_SYS_TEXT_BASE 0x21000000
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/* ARM asynchronous clock */
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#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
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@ -168,4 +168,54 @@
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#define CONFIG_SYS_MALLOC_LEN \
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ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
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/* Defines for SPL */
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_TEXT_BASE 0x0
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#define CONFIG_SPL_MAX_SIZE (11 * 1024)
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#define CONFIG_SPL_STACK (16 * 1024)
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#define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE
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#define CONFIG_SPL_BSS_MAX_SIZE (3 * 1024)
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_BOARD_INIT
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#define CONFIG_SPL_GPIO_SUPPORT
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#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14)
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#define CONFIG_SPL_NAND_SUPPORT
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#define CONFIG_SYS_USE_NANDFLASH 1
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#define CONFIG_SPL_NAND_DRIVERS
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#define CONFIG_SPL_NAND_BASE
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#define CONFIG_SPL_NAND_ECC
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#define CONFIG_SPL_NAND_RAW_ONLY
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#define CONFIG_SPL_NAND_SOFTECC
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
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#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_SIZE (256*1024*1024)
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
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#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
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CONFIG_SYS_NAND_PAGE_SIZE)
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
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#define CONFIG_SYS_NAND_ECCSIZE 256
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
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48, 49, 50, 51, 52, 53, 54, 55, \
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56, 57, 58, 59, 60, 61, 62, 63, }
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#define CONFIG_SPL_ATMEL_SIZE
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#define CONFIG_SYS_MASTER_CLOCK 132096000
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#define AT91_PLL_LOCK_TIMEOUT 1000000
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#define CONFIG_SYS_AT91_PLLA 0x202A3F01
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#define CONFIG_SYS_MCKR 0x1300
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#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR)
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#define CONFIG_SYS_AT91_PLLB 0x10193F05
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#endif
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