mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 15:14:43 +00:00
x86: Add chromebook_link board
This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
parent
c03c951b06
commit
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18 changed files with 438 additions and 0 deletions
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@ -12,9 +12,32 @@ choice
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config TARGET_COREBOOT
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bool "Support coreboot"
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help
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This target is used for running U-Boot on top of Coreboot. In
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this case Coreboot does the early inititalisation, and U-Boot
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takes over once the RAM, video and CPU are fully running.
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U-Boot is loaded as a fallback payload from Coreboot, in
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Coreboot terminology. This method was used for the Chromebook
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Pixel when launched.
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config TARGET_CHROMEBOOK_LINK
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bool "Support Chromebook link"
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help
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This is the Chromebook Pixel released in 2013. It uses an Intel
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i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of
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SDRAM. It has a Panther Point platform controller hub, PCIe
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WiFi and Bluetooth. It also includes a 720p webcam, USB SD
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reader, microphone and speakers, display port and 32GB SATA
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solid state drive. There is a Chrome OS EC connected on LPC,
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and it provides a 2560x1700 high resolution touch-enabled LCD
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display.
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endchoice
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source "arch/x86/cpu/ivybridge/Kconfig"
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source "board/chromebook-x86/coreboot/Kconfig"
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source "board/google/chromebook_link/Kconfig"
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endmenu
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@ -13,6 +13,7 @@
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#include <ns16550.h>
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#include <asm/msr.h>
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#include <asm/cache.h>
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#include <asm/cpu.h>
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#include <asm/io.h>
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#include <asm/arch-coreboot/tables.h>
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#include <asm/arch-coreboot/sysinfo.h>
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171
arch/x86/cpu/ivybridge/Kconfig
Normal file
171
arch/x86/cpu/ivybridge/Kconfig
Normal file
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#
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# From Coreboot src/northbridge/intel/sandybridge/Kconfig
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#
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# Copyright (C) 2010 Google Inc.
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#
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# SPDX-License-Identifier: GPL-2.0
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config NORTHBRIDGE_INTEL_SANDYBRIDGE
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bool
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select CACHE_MRC_BIN
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select CPU_INTEL_MODEL_206AX
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config NORTHBRIDGE_INTEL_IVYBRIDGE
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bool
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select CACHE_MRC_BIN
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select CPU_INTEL_MODEL_306AX
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if NORTHBRIDGE_INTEL_SANDYBRIDGE
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config VGA_BIOS_ID
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string
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default "8086,0106"
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config CACHE_MRC_SIZE_KB
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int
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default 256
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config MRC_CACHE_BASE
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hex
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default 0xff800000
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config MRC_CACHE_LOCATION
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hex
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depends on !CHROMEOS
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default 0x1ec000
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config MRC_CACHE_SIZE
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hex
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depends on !CHROMEOS
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default 0x10000
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config DCACHE_RAM_BASE
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hex
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default 0xff7f0000
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config DCACHE_RAM_SIZE
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hex
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default 0x10000
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endif
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if NORTHBRIDGE_INTEL_IVYBRIDGE
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config VGA_BIOS_ID
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string
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default "8086,0166"
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config EXTERNAL_MRC_BLOB
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bool
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default n
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config CACHE_MRC_SIZE_KB
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int
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default 512
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config MRC_CACHE_BASE
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hex
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default 0xff800000
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config MRC_CACHE_LOCATION
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hex
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depends on !CHROMEOS
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default 0x370000
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config MRC_CACHE_SIZE
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hex
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depends on !CHROMEOS
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default 0x10000
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config DCACHE_RAM_BASE
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hex
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default 0xff7e0000
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config DCACHE_RAM_SIZE
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hex
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default 0x20000
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endif
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if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE
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config HAVE_MRC
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bool "Add a System Agent binary"
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help
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Select this option to add a System Agent binary to
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the resulting U-Boot image. MRC stands for Memory Reference Code.
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It is a binary blob which U-Boot uses to set up SDRAM.
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Note: Without this binary U-Boot will not be able to set up its
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SDRAM so will not boot.
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config DCACHE_RAM_MRC_VAR_SIZE
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hex
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default 0x4000
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help
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This is the amount of CAR (Cache as RAM) reserved for use by the
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memory reference code. This should be set to 16KB (0x4000 hex)
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so that MRC has enough space to run.
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config MRC_FILE
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string "Intel System Agent path and filename"
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depends on HAVE_MRC
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default "systemagent-ivybridge.bin" if NORTHBRIDGE_INTEL_IVYBRIDGE
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default "systemagent-sandybridge.bin" if NORTHBRIDGE_INTEL_SANDYBRIDGE
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help
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The path and filename of the file to use as System Agent
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binary.
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select SMM_TSEG
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select ARCH_BOOTBLOCK_X86_32
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select ARCH_ROMSTAGE_X86_32
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select ARCH_RAMSTAGE_X86_32
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select SMP
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select SSE2
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select UDELAY_LAPIC
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select CPU_MICROCODE_IN_CBFS
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select TSC_SYNC_MFENCE
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select HAVE_INTEL_ME
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config SMM_TSEG_SIZE
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hex
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default 0x800000
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config ENABLE_VMX
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bool "Enable VMX for virtualization"
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default n
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help
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Virtual Machine Extensions are provided in many x86 CPUs. These
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provide various facilities for allowing a host OS to provide an
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environment where potentially several guest OSes have only
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limited access to the underlying hardware. This is achieved
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without resorting to software trapping and/or instruction set
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emulation (which would be very slow).
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Intel's implementation of this is called VT-x. This option enables
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VT-x this so that the OS that is booted by U-Boot can make use of
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these facilities. If this option is not enabled, then the host OS
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will be unable to support virtualisation, or it will run very
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slowly.
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endif
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config CPU_INTEL_SOCKET_RPGA989
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bool
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if CPU_INTEL_SOCKET_RPGA989
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config SOCKET_SPECIFIC_OPTIONS # dummy
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def_bool y
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select MMX
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select SSE
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select CACHE_AS_RAM
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config CACHE_MRC_BIN
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bool
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default n
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endif
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9
arch/x86/cpu/ivybridge/Makefile
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9
arch/x86/cpu/ivybridge/Makefile
Normal file
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#
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# Copyright (c) 2014 Google, Inc
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += car.o
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obj-y += cpu.o
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obj-y += sdram.o
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20
arch/x86/cpu/ivybridge/car.S
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20
arch/x86/cpu/ivybridge/car.S
Normal file
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/*
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* Copyright (c) 2014 Google, Inc
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*
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* From Coreboot file cpu/intel/model_206ax/cache_as_ram.inc
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*
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* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
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* Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan)
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* Copyright (C) 2007-2008 coresystems GmbH
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* Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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/* Note: ebp must not be touched in this code */
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.globl car_init
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car_init:
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/* TODO: Add cache-as-RAM init here */
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jmp car_init_ret
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42
arch/x86/cpu/ivybridge/cpu.c
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42
arch/x86/cpu/ivybridge/cpu.c
Normal file
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/*
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* Copyright (c) 2014 Google, Inc
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* (C) Copyright 2008
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* Graeme Russ, graeme.russ@gmail.com.
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*
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* Some portions from coreboot src/mainboard/google/link/romstage.c
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* Copyright (C) 2007-2010 coresystems GmbH
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* Copyright (C) 2011 Google Inc.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <asm/cpu.h>
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#include <asm/processor.h>
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DECLARE_GLOBAL_DATA_PTR;
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int arch_cpu_init(void)
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{
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int ret;
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timer_set_base(rdtsc());
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ret = x86_cpu_init_f();
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if (ret)
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return ret;
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return 0;
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}
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int print_cpuinfo(void)
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{
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char processor_name[CPU_MAX_NAME_LEN];
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const char *name;
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/* Print processor name */
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name = cpu_get_name(processor_name);
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printf("CPU: %s\n", name);
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return 0;
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}
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20
arch/x86/cpu/ivybridge/sdram.c
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20
arch/x86/cpu/ivybridge/sdram.c
Normal file
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/*
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* Copyright (c) 2011 The Chromium OS Authors.
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* (C) Copyright 2010,2011
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* Graeme Russ, <graeme.russ@gmail.com>
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*
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* Portions from Coreboot mainboard/google/link/romstage.c
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* Copyright (C) 2007-2010 coresystems GmbH
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* Copyright (C) 2011 Google Inc.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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int dram_init(void)
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{
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/* TODO: Set up DRAM */
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return 0;
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}
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@ -1,4 +1,5 @@
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dtb-y += link.dtb \
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chromebook_link.dtb \
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alex.dtb
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targets += $(dtb-y)
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1
arch/x86/dts/chromebook_link.dts
Symbolic link
1
arch/x86/dts/chromebook_link.dts
Symbolic link
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link.dts
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10
arch/x86/include/asm/arch-ivybridge/gpio.h
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10
arch/x86/include/asm/arch-ivybridge/gpio.h
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/*
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* Copyright (c) 2014, Google Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _X86_ARCH_GPIO_H_
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#define _X86_ARCH_GPIO_H_
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#endif /* _X86_ARCH_GPIO_H_ */
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15
board/google/chromebook_link/Kconfig
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15
board/google/chromebook_link/Kconfig
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if TARGET_CHROMEBOOK_LINK
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config SYS_BOARD
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default "chromebook_link"
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config SYS_VENDOR
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default "google"
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config SYS_SOC
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default "ivybridge"
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config SYS_CONFIG_NAME
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default "chromebook_link"
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endif
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6
board/google/chromebook_link/MAINTAINERS
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6
board/google/chromebook_link/MAINTAINERS
Normal file
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CHROMEBOOK LINK BOARD
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M: Simon Glass <sjg@chromium.org>
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S: Maintained
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F: board/google/chromebook_link/
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F: include/configs/chromebook_link.h
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F: configs/chromebook_link_defconfig
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15
board/google/chromebook_link/Makefile
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15
board/google/chromebook_link/Makefile
Normal file
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#
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# Copyright (c) 2011 The Chromium OS Authors.
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# (C) Copyright 2008
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# Graeme Russ, graeme.russ@gmail.com.
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2002
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# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += link.o
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17
board/google/chromebook_link/link.c
Normal file
17
board/google/chromebook_link/link.c
Normal file
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/*
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* Copyright (C) 2014 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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int arch_early_init_r(void)
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{
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return 0;
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}
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int board_early_init_r(void)
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{
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return 0;
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}
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7
board/google/common/Makefile
Normal file
7
board/google/common/Makefile
Normal file
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#
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# Copyright (c) 2014 Google, Inc
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += early_init.o
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10
board/google/common/early_init.S
Normal file
10
board/google/common/early_init.S
Normal file
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/*
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* Copyright (c) 2014 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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.globl early_board_init
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early_board_init:
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/* No 32-bit board specific initialisation */
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jmp early_board_init_ret
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10
configs/chromebook_link_defconfig
Normal file
10
configs/chromebook_link_defconfig
Normal file
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CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000"
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CONFIG_X86=y
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CONFIG_TARGET_CHROMEBOOK_LINK=y
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CONFIG_OF_CONTROL=y
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CONFIG_OF_SEPARATE=y
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CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
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CONFIG_HAVE_MRC=y
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CONFIG_SMM_TSEG_SIZE=0x800000
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CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
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CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
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60
include/configs/chromebook_link.h
Normal file
60
include/configs/chromebook_link.h
Normal file
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/*
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* Copyright (c) 2011 The Chromium OS Authors.
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* (C) Copyright 2008
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* Graeme Russ, graeme.russ@gmail.com.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <configs/x86-common.h>
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#define CONFIG_SYS_CAR_ADDR 0xff7e0000
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#define CONFIG_SYS_CAR_SIZE (128 * 1024)
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#define CONFIG_SYS_MONITOR_LEN (1 << 20)
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#define CONFIG_BOARD_EARLY_INIT_R
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#define CONFIG_NR_DRAM_BANKS 8
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#define CONFIG_COREBOOT_SERIAL
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||||
#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \
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PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
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{PCI_VENDOR_ID_INTEL, \
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PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
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{PCI_VENDOR_ID_INTEL, \
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PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
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{PCI_VENDOR_ID_INTEL, \
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PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
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/*
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* These common x86 features are not yet supported, but are added in
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* follow-on patches in this series. Add undefs here to avoid every patch
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||||
* having to put things back into x86-common.h
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||||
*/
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#undef CONFIG_INTEL_ICH6_GPIO
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#undef CONFIG_DM_GPIO
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#undef CONFIG_CMD_GPIO
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#undef CONFIG_VIDEO
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#undef CONFIG_CFB_CONSOLE
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#undef CONFIG_SYS_EARLY_PCI_INIT
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#undef CONFIG_PCI
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||||
#undef CONFIG_ICH_SPI
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#undef CONFIG_SPI
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#undef CONFIG_CMD_SPI
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||||
#undef CONFIG_CMD_SF
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#undef CONFIG_USB_EHCI
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#undef CONFIG_CMD_USB
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#undef CONFIG_CMD_SCSI
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||||
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||||
#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
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"stdout=vga,serial\0" \
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"stderr=vga,serial\0"
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||||
|
||||
#endif /* __CONFIG_H */
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Loading…
Reference in a new issue