Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-29 16:10:58 +00:00
Code Issues Projects Releases Packages Wiki Activity

Exynos542x: Move exynos5420_get_pll_clk up and rename

Browse source 
Moving exynos5420_get_pll_clk function definition up in the
code to keep it together with rest of SoC_get_pll_clk functions.
This makes code more legible and also removes the need of
declaration when called before the position of definition in
code. Also, renaming exynos5420_get_pll_clk to
exynos542x_get_pll_clk because it is being used for both Exynos
5420 and 5800.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
Akshay Saraswat 2015-02-04 16:00:00 +05:30 committed by Minkyu Kang
parent d606ded1db
commit 325eb18c77
1 changed files with 41 additions and 41 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

82
arch/arm/cpu/armv7/exynos/clock.c
View file

@ -263,6 +263,46 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
return fout;
}
/* exynos542x: return pll clock frequency */
static unsigned long exynos542x_get_pll_clk(int pllreg)
{
struct exynos5420_clock *clk =
(struct exynos5420_clock *)samsung_get_base_clock();
unsigned long r, k = 0;
switch (pllreg) {
case APLL:
r = readl(&clk->apll_con0);
break;
case MPLL:
r = readl(&clk->mpll_con0);
break;
case EPLL:
r = readl(&clk->epll_con0);
k = readl(&clk->epll_con1);
break;
case VPLL:
r = readl(&clk->vpll_con0);
k = readl(&clk->vpll_con1);
break;
case BPLL:
r = readl(&clk->bpll_con0);
break;
case RPLL:
r = readl(&clk->rpll_con0);
k = readl(&clk->rpll_con1);
break;
case SPLL:
r = readl(&clk->spll_con0);
break;
default:
printf("Unsupported PLL (%d)\n", pllreg);
return 0;
}
return exynos_get_pll_clk(pllreg, r, k);
}
static struct clk_bit_info *get_clk_bit_info(int peripheral)
{
int i;
@ -382,46 +422,6 @@ unsigned long clock_get_periph_rate(int peripheral)
return 0;
}
/* exynos5420: return pll clock frequency */
static unsigned long exynos5420_get_pll_clk(int pllreg)
{
struct exynos5420_clock *clk =
(struct exynos5420_clock *)samsung_get_base_clock();
unsigned long r, k = 0;
switch (pllreg) {
case APLL:
r = readl(&clk->apll_con0);
break;
case MPLL:
r = readl(&clk->mpll_con0);
break;
case EPLL:
r = readl(&clk->epll_con0);
k = readl(&clk->epll_con1);
break;
case VPLL:
r = readl(&clk->vpll_con0);
k = readl(&clk->vpll_con1);
break;
case BPLL:
r = readl(&clk->bpll_con0);
break;
case RPLL:
r = readl(&clk->rpll_con0);
k = readl(&clk->rpll_con1);
break;
case SPLL:
r = readl(&clk->spll_con0);
break;
default:
printf("Unsupported PLL (%d)\n", pllreg);
return 0;
}
return exynos_get_pll_clk(pllreg, r, k);
}
/* exynos4: return ARM clock frequency */
static unsigned long exynos4_get_arm_clk(void)
{
@ -1603,7 +1603,7 @@ unsigned long get_pll_clk(int pllreg)
{
if (cpu_is_exynos5()) {
if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_get_pll_clk(pllreg);
return exynos542x_get_pll_clk(pllreg);
return exynos5_get_pll_clk(pllreg);
} else {
if (proid_is_exynos4412())