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x86: Add Intel Crown Bay board dts file

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Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Bin Meng 2014-12-12 21:05:24 +08:00 committed by Simon Glass
parent 2795573a8c
commit 568868dda9
2 changed files with 55 additions and 1 deletions
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3
arch/x86/dts/Makefile
View file

@ -1,6 +1,7 @@
dtb-y += link.dtb \
chromebook_link.dtb \
alex.dtb
alex.dtb \
crownbay.dtb
targets += $(dtb-y)

53
arch/x86/dts/crownbay.dts Normal file
View file

@ -0,0 +1,53 @@
/*
* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
/include/ "coreboot.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "Intel Crown Bay";
compatible = "intel,crownbay", "intel,queensbay";
config {
silent_console = <0>;
};
gpioa {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0 0x20>;
bank-name = "A";
};
gpiob {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0x20 0x20>;
bank-name = "B";
};
serial {
reg = <0x3f8 8>;
clock-frequency = <115200>;
};
chosen { };
memory { device_type = "memory"; reg = <0 0>; };
spi {
#address-cells = <1>;
#size-cells = <0>;
compatible = "intel,ich7";
spi-flash@0 {
reg = <0>;
compatible = "sst,25vf016b", "spi-flash";
memory-map = <0xffe00000 0x00200000>;
};
};
};